阅读说明：本技术 快速精度下降检测器电路及其方法 (Fast degradation detector circuit and method ) 是由 詹姆斯·R·隆柏格 于 2021-07-27 设计创作，主要内容包括：本申请提供了快速精度下降检测器电路及其方法。在一个实施例中,一种下降检测器电路,包括：参考振荡器；多个延迟线,其被配置为从所述参考振荡器接收信号；以及逻辑,其被配置为基于所述电压调节器的输出以及所述多个延迟线中的各延迟线的输出来检测所述电压调节器中的下降。(The present application provides a fast degradation of precision detector circuit and method thereof. In one embodiment, a droop detector circuit, comprising: a reference oscillator; a plurality of delay lines configured to receive signals from the reference oscillator; and logic configured to detect a droop in the voltage regulator based on an output of the voltage regulator and an output of each of the plurality of delay lines.)

1. A droop detector circuit, comprising:

a reference oscillator;

a plurality of delay lines configured to receive signals from the reference oscillator; and

logic configured to detect a droop in a voltage regulator based on an output of the voltage regulator and an output of each of the plurality of delay lines.

2. The droop detector circuit of claim 1, wherein each of the plurality of delay lines has a staggered start according to a signal of the reference oscillator.

3. The droop detector circuit of claim 2, wherein the logic is configured to evaluate the droop every respective clock cycle for each of the respective plurality of delay lines.

4. The droop detector circuit of claim 3, wherein the logic is further configured to: evaluating two or more of the plurality of delay lines to enable detection of a sustained droop over a corresponding plurality of clock cycles.

5. The droop detector circuit of claim 1, wherein the logic is further configured to evaluate a difference between an output of the voltage regulator, vdd, and ground, vss.

6. The droop detector circuit of claim 1, wherein the reference oscillator operates continuously over a plurality of periods associated with the delay line.

7. The droop detector circuit of claim 1, wherein the plurality of delay lines and logic are programmable.

8. The droop detector circuit of claim 7, wherein the plurality of delay lines and the logic are programmably configured to trigger according to a constant voltage level of the voltage regulator output relative to ground.

9. The droop detector circuit of claim 7, wherein the plurality of delay lines and the logic are programmably configured to trigger according to a percentage voltage level of the voltage regulator output relative to ground.

10. The droop detector circuit of claim 1, wherein the logic comprises a pair of D-type flip-flops for each of the plurality of delay lines, and a combinational logic circuit receiving a respective input from one of the D-type flip-flops of the pair.

11. The droop detector circuit of claim 1, further comprising said voltage regulator.

12. The droop detector circuit of claim 1, wherein said plurality of delay lines are matched.

13. A drop detection method, comprising:

generating a signal from a reference oscillator;

applying a phase delay in a signal received from the reference oscillator over a plurality of delay lines; and

detecting a droop in the voltage regulator based on receiving an output of the voltage regulator and an output from each of the plurality of delay lines.

14. The drop detection method of claim 13, further comprising: staggering the start of the plurality of delay lines with respect to the signal of the reference oscillator.

15. The drop detection method of claim 14, further comprising: for each of the respective plurality of delay lines, a droop is evaluated every respective clock cycle.

16. The drop detection method of claim 15, further comprising: based on evaluating two or more of the plurality of delay lines to enable detection of a sustained droop over a corresponding plurality of clock cycles.

17. The drop detection method of claim 13, further comprising: the difference between the output of the voltage regulator, vdd, and ground, vss, is evaluated.

18. The drop detection method of claim 13, further comprising: mitigating the presence of the current surge by causing the reference oscillator to operate continuously for a plurality of periods associated with the delay line.

19. The drop detection method of claim 13, further comprising: programmably triggering detection based on a constant voltage level of the voltage regulator output relative to ground or a percentage voltage level of the voltage regulator output relative to ground.

Technical Field

The present invention relates generally to droop detection, and in particular to droop detection in microprocessors.

Background

Voltage regulators, and in particular, Voltage Regulator Modules (VRMs), are used to provide the appropriate supply voltage for microprocessors. Typically, the VRM is mounted to the motherboard via a solder connection or a slot designed to receive the VRM. Some VRMs provide a fixed supply voltage to the microprocessor, while others sense the required supply voltage from the microprocessor, thereby enabling variable regulation.

Microprocessors (e.g., when switching out of an idle or power saving state) may require rapid changes in load current, which presents challenges to VRMs. For example, a VRM may experience large step changes in load current over a period of time measured in nanoseconds. Voltage droop compensation is one technique used in these types of situations that intentionally increases the DC output impedance of the converter, thereby reducing its output as the load current increases. In effect, the voltage droop compensation reduces overshoot of the supplied voltage during large step changes in load current. Selecting the amount of voltage droop to apply is challenging because it typically involves knowledge of the worst-case transient load change that is difficult to predict. Voltage droop compensation requires maintaining near-fidelity to the desired supply voltage while accommodating transient loads without experiencing unacceptable levels of voltage droop that may be detrimental to performance (e.g., power starvation, and therefore reduced clock speed).

Disclosure of Invention

In one embodiment, a droop detector circuit includes: a reference oscillator; a plurality of delay lines configured to receive signals from the reference oscillator; and logic configured to detect a droop in the voltage regulator based on an output of the voltage regulator and an output of each of the plurality of delay lines.

Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.

Drawings

Various aspects of the invention may be better understood with reference to the following drawings. The components in the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Moreover, in the figures, like reference numerals designate corresponding parts throughout the several views.

FIG. 1 is a block diagram illustrating an embodiment of an example droop detection system including a droop detector coupled to a voltage regulator.

FIG. 2A is a schematic diagram illustrating an embodiment of an example ring oscillator for use in a droop detector.

Fig. 2B is a schematic diagram illustrating an embodiment of an example delay line used in a droop detector.

FIG. 2C is a schematic diagram illustrating an embodiment of example fall detection logic for use in a fall detector.

Fig. 2D is a schematic diagram illustrating example combinational logic used in a droop detector.

FIG. 3A is a schematic diagram illustrating an embodiment of an example droop reference apparatus in or coupled to a droop detector and including a programmable filter and a digital-to-analog converter.

FIG. 3B is a plot showing how an embodiment of a falling reference device aims to track unwanted high frequency noise and variations in voltage supply.

FIG. 3C is a schematic diagram illustrating an embodiment of an example circuit of a digital-to-analog converter of the falling reference device.

FIG. 4 is a flow diagram illustrating an embodiment of an example method performed by an embodiment of a falling reference device.

FIG. 5 is a flow diagram illustrating an embodiment of an example method performed by an embodiment of a droop detector.

Detailed Description

Certain embodiments of a droop detection system and method are disclosed that detect droop in a microprocessor and use the detection to adjust clock speed in an effort to improve microprocessor performance. In one embodiment, a fall detection system includes a fall detector having: a reference oscillator; a plurality of delay lines; and detection logic configured to detect a droop in the voltage regulator based on the outputs of the voltage regulator and the delay line. In some embodiments, a droop reference device is used in conjunction with a droop detector to reject high frequency noise and track the ramp up and ramp down of the supply voltage, providing a filtered and scaled version of the microprocessor voltage supply.

In short, the power consumed by a microprocessor may be affected by one or more of a variety of factors, including the type of instruction, the dispatch rate of the instruction, the data being operated on, and the like. A rapid change in the current drawn by the microprocessor, which may lead to voltage instability, may be triggered by a sudden change in any of these factors. For example, a rapid change in the current drawn by the on-chip circuitry may result in a temporary drop (or spike) in the supply voltage received from the voltage regulator, while the decrease in current may be reflected as a spike in the supply voltage. In addition, the switching speed of a transistor used in a microprocessor is a function of the voltage applied to its gate. For example, transistor switching speeds typically decrease at lower voltages. Thus, a drop in the regulator supply voltage may slow down the logic elements between the latches, which may cause a fault if these latches and the clock fed to them are not event local and run at full speed. Furthermore, the voltage drop may couple back to the input of the voltage regulator, which may cause other circuits on the chip to malfunction. Certain embodiments of the droop detection system prevent or mitigate erroneous operation of the microprocessor and/or devices located within the microprocessor by adjusting the clock speed until the droop subsides to accommodate these droop events.

Having summarized certain features of the fall detection system of the present invention, reference will now be made in detail to a description of the fall detection system as illustrated in the accompanying drawings. While the droop detection system will be described in connection with these drawings, it is not intended to be limited to the embodiment or embodiments disclosed herein. That is, while the invention is susceptible to modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail as sufficient to enable those skilled in the art to understand the invention. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. As used throughout this application, the word "may" is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words "include", "including", and "includes" mean including, but not limited to.

Various units, modules, circuits, logic, or other components may be described as being "configured to" perform a task or tasks. In this context, "configured to" is a broad recitation of structure, which is typically meant to "have circuitry or other physical structure that performs, or is capable of performing, one or more tasks during operation. The circuitry may be dedicated circuitry or more general processing circuitry that operates under the control of coded instructions. That is, terms such as "unit," "module," "circuit," "logic," and "component" may be used herein in describing certain aspects or features of various implementations of the invention. Those skilled in the art will appreciate that the corresponding features are implemented using circuits, whether special purpose circuits or more general purpose circuits that operate under the control of microcoded instructions.

Furthermore, a unit/module/circuit/logic/component may be configured to perform a task even when the unit/module/circuit/logic/component is not currently in operation. A unit/module/circuit/logic/component that is configured to perform one or more tasks is expressly not intended to be a functional limitation on the unit/module/circuit/logic/component. In this regard, those skilled in the art will appreciate that the specific structure or interconnection of circuit elements will typically be determined by a compiler of the design automation tool, such as a Register Transfer Language (RTL) compiler or the like. The RTL compiler operates on scripts that are very similar to assembly language code to compile the scripts into a form for the layout or fabrication of the final circuit.

That is, integrated circuits, such as the integrated circuit of the present invention, are designed using higher level software tools to model the desired functional operation of the circuit. As is well known, "electronic design automation" (or EDA) is a class of software tools used to design electronic systems, such as integrated circuits and the like. EDA tools are also used to program design functions into Field Programmable Gate Arrays (FPGAs). Hardware Description Languages (HDLs), such as Verilog and very high speed integrated circuit hardware description language (VHDL), are used to create high-level representations of circuits from which low-level representations and ultimately the actual wiring can be derived. In fact, EDA tools are considered essential to their design, as modern semiconductor chips can have billions of components. In practice, circuit designers use programming languages such as C/C + + to specify operating functions. The EDA software tool converts the specified function to RTL. A hardware description language (e.g., Verilog) then converts the RTL into a discrete gate netlist. The netlist defines the actual circuit produced by, for example, a foundry. Indeed, these tools are well known and understood for their role and use in facilitating the design process of electronic and digital systems and, therefore, need not be described herein.

Turning attention now to fig. 1, fig. 1 illustrates an embodiment of an example droop detection system 10, the droop detection system 10 including a droop detector 12 coupled to a voltage regulator 14. The voltage regulator 14 includes analog logic. The droop detector 12 comprises digital logic. From the top of the figure, vdd9 represents the power supply voltage. For example, a typical power supply voltage is 1.8 volts (V). vss9 is an analog (static) ground. vdd9 and vss9 are received onto the microprocessor. The output of the voltage regulator 14 is vdd 4. Vdd4 varies according to the analog voltage drop reference or drp _ vref received at the pin labeled vref. drp _ vref is a voltage reference. The enable pin, labeled en in fig. 1, receives the enable signal drp _ reg _ en. If no signal is received at the enable pin, this means that there is no output from the voltage regulator 14. For example, there may be situations where droop is insignificant, such as a microprocessor running at a slow clock speed but at a sufficiently high voltage, where a wide range of droop voltages can be tolerated. By not enabling the output of the voltage regulator 14, power may be saved.

vdd4 is provided to droop detector 12. As mentioned above, vss9 is analog ground. As explained further below, two supplies vdd4 and vss9 are used for the ring oscillator provided within the droop detector 12. The pin ph1 receives a clock ph1 generated by the microprocessor and is used to provide the appropriate synchronization to the clock domain. The other two input pins drp _ en and drp _ clr _ out are enable pins that receive drp _ en and drp _ clr _ out, respectively, which are known digital functions. As explained further below, the droop detector 12 includes output pins drp _ one, drp _ two, drp _ three, and drp _ four for providing an indication that droop has been detected over one or more delay line cycles.

In some embodiments, the droop detector 12 also includes a droop reference 16, which is described below in connection with fig. 3A-3C.

Referring now to FIG. 2A, a schematic representation of an embodiment of an exemplary ring oscillator 18 for use in the droop detector 12 is shown. The ring oscillator 18 includes an enable device 20 and a series of delay inverters collectively represented by a delay block 22. The enable device 20 includes a NAND gate that serves as an enable for the delay block 22. The enabling means 20 are labelled 4 and 9 indicating the power supply for the block (e.g. vdd4 and vss9 as explained in connection with fig. 1). The output of the enable means 20 is the reference oscillator signal (refosc) and the inputs include the falling enable (drp en) described in connection with fig. 1 and the last delayed inverter output of the delay block (refdrp < 115 >). Delay block 22 has a flag located thereon, i.e., falling oscillator or drposc < 115: 0> which is used to indicate that the delay block 22 is actually 116 such blocks (inverters or delay stages) arranged in series. Notably, the output of delay block 22 is a reference drop, or refdrp < 115: 0 >. For example, the output of the first stage or block of the delay block is the reference fall 0(refdrp _0), the output of the second stage or block is the reference fall 1(refdrp _1), followed by the reference falls 2, 3, 4 … … 115, similarly.

The inputs to delay block 22 initially comprise the output of enable device 20 (refosc), followed by respective blocks of delay block 22 feeding to the next block of delay block 22 (e.g., illustratively shown as respective output signals fed back to the inputs (refdrp < 114: 0 >). for example, the first input to the first block of delay block 22 is refosc. the second block of delay block 22 in series with the first block receives output refdrp < 0 >. the third block of delay block 22 in series with the second block receives output refdrp < 1>, and so on, until the last block of delay block 22 outputs refdrp < 115> (which is fed back to enable device 20), and processing continues. to represent this processing, delay block 22 only shows the input as initially being refsc, followed by output refdrp < 114: 0> (e.g., refdrp < 0>), refdrp < 1>, refdrp < 352 >),115, fig. 2A is a simplified diagram showing the 116 blocks of the delay block 22 arranged in series and their interaction with the enabling means 20. Thus, the ring oscillator 18 provides a continuous oscillating signal and, by doing so, avoids a start-up current surge (e.g., no di/dt induced inaccuracies because it is running continuously).

In effect, the ring oscillator 18 is powered down from the voltage regulator 14, with operation based on vdd4 and vss9(vdd4-vss 9). The period of the ring oscillator 18 is proportional to the voltage supplied.

Referring now to fig. 2B, an embodiment of an example delay line used in the droop detector 12 is shown. In one embodiment, there are four (4) delay line blocks (drpdelea-drpdeled) or 24A, 24B, 24C, and 24D, but in some embodiments fewer or additional delay line blocks may be used. In one embodiment, each delay line block 24 (hereinafter referred to broadly as 24A, 24B, 24C, and 24D) includes 67 (e.g., < 66: 0>) delay blocks or inverters arranged in series. In some embodiments, the number of blocks or stages per delay line block 24 may be different than the number used and is therefore contemplated to be within the scope of the present invention. The first stage or block of each delay line block 24 uses the output (refdrp) of the reference oscillator 18 and these outputs are used in an interleaved fashion as the initial input to each delay line block 24, followed by the delay line chain in each block 24. For example, one of the inputs to delay line block 24A (i.e., the first stage of delay line block 24A) is refdrp <4 >. One of the inputs to delay line block 24B (i.e., the first stage of delay line block 24B) is refdrp < 15 >. One of the inputs to delay line block 24C (i.e., the first stage of delay line block 24C) is refdrp < 30 >. One of the inputs to delay line block 24D (i.e., the first stage of delay line block 24D) is refdrp <45 >. Note that other stages used as inputs to the respective delay line blocks 24 to achieve staggered start may be used in some embodiments. It is noted that the delay line block 24 is shown in fig. 2B in a similar manner to the representation used for the reference oscillator 18 in fig. 2A. For example, the output of delay line block 24A is drpa < 71: 5>, which represents the corresponding output of the 67 stages starting after refdrp <4 >. Similarly, the outputs of delay line blocks 24B, 24C, and 24D are drpb < 82: 16>, drpc < 97: 31> and drpd < 112: 46 >.

Further illustratively, and with delay line block 24A as a representative example of the inputs and outputs of each delay line block 24, delay line block 24A includes a first stage or block that receives an initial input (refdrp < 4>) from reference oscillator 18. The second stage or block of the delay line block 24A receives the output drpa < 5> from the first stage or block. A third stage or block of the delay line block 24A receives the output drpa <6> from the second stage or block, and so on. In the figure, the input/output chain from one stage to the next stage among the blocks of the delay line block 24A is schematically represented as feedback from the output of the delay line block 24A to the input of the delay line block 24A. Similar descriptions using different staggered start values apply to the other delay line blocks 24B, 24C, and 24D and are therefore omitted here for brevity.

Associated with each of the delay lines 24 is additional circuitry for matching the ring oscillator 18 to the delay line blocks 24 in all stages and to a flip-flop that receives interleaved outputs from each of the delay line blocks, as shown in fig. 2C and described below. For example, when the ring oscillator 18 sends an output to enable a given delay line 24 (e.g., one or more of refdrp < 15>, refdrp < 30>, and refdrp <45> depending on the transition), matched loading must occur at the operational delay line 24. These matched loads are referred to as start loads or Ids, and are represented in fig. 2B as Idsa 26A (e.g., three of which, or < 2: 0>, correspond to level line communications drpa < 15>, drpa < 30> and drpa <45 >), Idsb 26B (two of which < 1: 0>, correspond to level line communications drpb < 30> and drpb <45 >), and Idsc 26C (one of which, or Ids _ C, corresponds to level line communications drpc <45 >).

In addition, ring oscillator 18 transmits signals to the flip-flops corresponding to each delay line block 24, and as described above, the flip-flops are signaled at stages refdrp <69>, refdrp <80>, refdrp <95>, and refdrp < 110 >. These matched loads are referred to as end loads or lde and are represented in FIG. 2B as ldeb 28A (e.g., one of them or ldeb, corresponding to level line communications drpb <69> (to the flip-flop)), ldec28B (two of them, < 1: 0>, corresponding to level line communications drpc <69> and drpc <80 >), and lded 28C (three of them, < 2: 0>, corresponding to level line communications drpd <69>, drpd <80> and drpd <95 >). Note that the values at which the ring oscillator 18 provides these signals may be different in some embodiments, and the values used herein are used to illustrate one example operation.

Furthermore, it should be understood by those skilled in the art that additional circuitry may be present in fig. 2B to account for parasitics, capacitances, and resistances. In other words, appropriate circuitry (not shown, but understood by those skilled in the art) may be used to maintain symmetry.

Turning attention now to fig. 2C, fig. 2C illustrates an embodiment of example droop detection logic 30 for use in the droop detector. The fall detection logic 30 includes four (4) branches corresponding to the outputs of four delay line blocks (fig. 2B), each branch including a pair of flip-flops 32, 34 for each of the delay lines. The droop detection logic 30 also includes combinational logic 36(drplog) that receives the outputs from the respective flip-flops 34 to determine the presence of droop and whether droop is sustained (over more than one cycle of the delay line). In one embodiment, the flip-flops 32 (hereinafter referred to broadly as 32A, 32B, 32C, and 32D), 34 (hereinafter referred to broadly as 34A, 34B, 34C, and 34D) comprise D-type flip-flops (e.g., D flip-flops, differential D flip-flops). Referring to the top flip-flop pair dff 032A and dff 434A depicted in FIG. 2C, dff 032A receives the ring oscillator output of a particular stage (e.g., refdrp <69>) at the d input and the corresponding stage output from delay line 24A (e.g., drpa <69>) at the clk input. dff 032A also receives a clock drp _ clr _ out (also shown in FIG. 1) at the clrb clock input. dff 032A outputs an intermediate output rdrpa (from q) to the d input of dff 434A. dff 434A also receives a clock input (ph1) at the clk input and a clock input drp _ clr _ out at the clrb input. dff 434A outputs sdrpab at output qb to the ab input of combinational logic (drplog) 36.

Using the top d1 branch comprising dff 032A and dff 434A as a representative example to illustrate the operation of droop detection logic 30, in practice, dff 032A receives the oscillator reference (refdrp <69>) and the output droop (drpa <69>) from delay line 24A, both from the same stage <69 >. If the drop (drpa <69>) is slower than the reference (refdrp <69>), then dff 032A captures the value. In fact, a slower drop reveals the presence (and therefore detection) of a drop. The reference drop (refdrp <69>) should be slower because it operates at a lower voltage. In other words, the droop (drpa <69>) should be faster because it operates at a higher (e.g., full) supply voltage. As an illustrative example, if the microprocessor is operating at 1 volt, and if it is desired to determine if there is a 10% drop in the power supply (e.g., vref to voltage regulator 14 is 90% or 900 millivolts (mV) of vdd 0), then ring oscillator 18 is operating at 900 mV. If the microprocessor drops beyond 900mV, then dff 032A detects this condition with the d input to dff 032A and the input to clk input.

With respect to dff 434A, as described above, dff 434A uses ph1 for its clock (to clrb) that is used to synchronize the output of dff 032A into the ph1 time domain (e.g., the global time domain of the microprocessor).

The next pair of flip-flops of the fall detection logic 30 (the next branch including dff 132B and dff 534B), dff 132B receives a stage output of the ring oscillator (refdrp <80 >) at the d input of dff 132B and the corresponding stage output from delay line 24B (drpb <80 >) at the clk input. The clock input is drp _ clr _ out at clrb and the output is rdrpb from the q output. In other words, dff 132B and dff 534B are identical in input/output arrangement to dff 032A and dff 434A, except that dff 132B begins at a different bit (e.g., <80 >). In other words, dff 132B is delayed in its stages relative to dff 032A, but each utilizes the same number of delay line stages (e.g., 67 stages) from delay line block 24 of fig. 2B.

Recall that the delay line 24 has staggered starts (e.g., < 4>, < 15>, < 30>, and <45 >), and thus the flip-flop 32 has a staggered start. Four matched delay lines 24A-24D with staggered starts enable at least one fall evaluation per high speed clock cycle by the fall detection logic 30, which allows for long delay lines. The longer delay line 24 reduces the variability observed in silicon (e.g., by a factor of 8). For example, the variability from one inverter to another may be large, but in many series cases, the variability is averaged (e.g., from 2 to 64, with variability of about 1/8 times the delay line period). Furthermore, the longer delay lines are slower than the clock cycle of the microprocessor (e.g., when running at full speed), so that at least one evaluation can be made during one clock cycle (ph1) with staggered starts between delay lines.

The other flip-flop pairs for the other branches dff 232C, dff 634C, dff 332D, dff 734D are identical to the arrangement of flip-flop pairs described above, with the interleaving starting (e.g., refdrp <95> for dff 232C, drpc <95>, and refdrp < 110>, < drpd < 110> for dff 332D), so the above description can be similarly extended for these pairs.

The combinational logic (drplog)36 shows four possible outputs, namely drp _ one, drp _ two, drp _ three, and drp _ four. In some embodiments, fewer or more outputs may be used and are therefore contemplated to be within the scope of the present invention. drplog 36 receives an indication of whether a dip has been detected based on inputs from the trigger 34 (e.g., at inputs ab, bb, cb, and db). When a dip is detected over more than one delay line cycle, such an event reveals a prolonged dip event (e.g., extending over two lengths or drp _ two, three lengths or drp _ three, etc.) output by drplog 36. The falling event should continue or exceed the fall of the reference relative to the entire length of the delay line 24. Note that there may be multiple sustained (subsequent) fall periods. The de-assertion of any or all of the droop events enables the microprocessor to resume high frequency operation.

When the drop lasts too long (e.g., when all four drp _ one, drp _ two, drp _ three, and drp _ four are triggered), the microprocessor may implement one of a number of different remedial actions. One remedy is to slow the clock down for the microprocessor (e.g., until the droop event subsides). In some embodiments, the microprocessor may cause a switch to another Phase Locked Loop (PLL) with a slower clock period (e.g., as signaled from the fall detection logic 30). Note that the triggering for remedial action may involve one, two, three, or four delay line drops. Evaluation over the plurality of delay lines 24 also minimizes variation. Fig. 2D illustrates an example embodiment of the combinational logic 36, which is conventional and therefore a discussion thereof is omitted herein for the sake of brevity.

Note that some embodiments of the droop detector 12 are configured to detect a rise in vss or a fall on vdd (e.g., the droop detector 12 measures vdd-vss), either of which may cause a slow down of the delay line. In contrast, conventional droop detectors assume that vss is static and does not move, and therefore rely only on the measurement of vdd.

Another benefit of some embodiments of the droop detector 12 is that because the ring oscillator 18 operates continuously (e.g., asynchronously with the chip), there is no start-up current surge associated with the droop detector 12. This is in contrast to other droop detectors which use a reference voltage delay line off the trigger gate and therefore run synchronously with the chip.

In addition, some embodiments of droop detector 12 may be programmed to trigger at a constant voltage level (e.g., vdd-vss) or a percentage of vdd-vss. This feature may enable the use of different instances of the droop detector in different areas of the microprocessor, or may permit operation with a Voltage Regulator Module (VRM) that provides dynamic voltage supply based on a Voltage Identification Definition (VID) that includes a set of bits. For example, once the VRM receives a VID that identifies the desired supply voltage, the VRM acts as a voltage regulator. The voltage regulator may provide the required constant voltage supply to the microprocessor. In some applications, the VID lines may be used by the microprocessor to indicate a desired voltage level to an onboard power converter (e.g., switch-mode, buck converter), which in turn adjusts its output accordingly.

In some embodiments of the droop detector, the need to track the ramp of the voltage supply while rejecting transient noise is particularly valuable because there is no need to regenerate the other reference supply voltage. In addition, it is also valuable to have the ability to select to have a constant voltage (e.g., not changing with the ramp of the power supply) because it provides design flexibility. Fig. 3A illustrates an embodiment of an example droop reference apparatus 38 of or coupled to a droop detector (e.g., droop detector 12) and including a programmable filter and a digital-to-analog converter. Note that the falling reference device 38 may be implemented as the falling reference device 16 shown in fig. 1. Typically, the descent reference device 38 provides a single reference for multiple descent detectors (e.g., whose positions are independent of the positions of the other detectors). In one embodiment, falling reference device 38 includes a serial arrangement of a programmable Low Pass Filter (LPF)40, a buffer 42, a digital-to-analog converter (DAC)44, followed by another buffer 46. Programmable LPF 40 receives the supply voltage (vdd _ cpu) of the microprocessor and control signal lpfbw (low pass filter bandwidth). In one embodiment, the control signal includes a 4-bit digital field that may be controlled by any one of a number of different sources (including a scan, fuse, microcode, digital logic, etc.). Control signal lpfbw controls what frequency programmable LPF 40 passes (or rejects). Programmable LPF 40 is configured to remove high frequency content from Vdd _ cpu.

With continuing reference to fig. 3A, and with further reference to fig. 3B, shown is a graph 48 schematically illustrating an example low pass filter input 50 (e.g., measured in voltage, Y-axis) versus a low pass filter output 52 (e.g., measured in time, X-axis) of the programmable LPF 40. As shown in fig. 3B, not only may vdd _ cpu have unwanted high frequency noise, but vdd _ cpu may change dynamically. During these changes, vdd _ cpu ramps up, or ramps down as disclosed in this example. Programmable LPF 40 tracks the slope of vdd _ cpu and rejects high frequency noise. The programmability of the LPF 40 (e.g., via the control signal lpfbw) allows the corner frequency to be adjusted.

Directing attention again to fig. 3A, buffers 42 and 46 provide the typical effect of transferring voltage from the high impedance device to the low impedance device with a relatively small current draw. Buffer 46 is used to drive the scaled and filtered vdd _ cpu to the rest of the circuitry of droop detector 12. Since the details of the buffer include known techniques, further discussion thereof is omitted for the sake of brevity.

DAC 44 is configured to provide scaling of the filtered vdd _ cpu. DAC 44 receives the output from programmable LPF 40 (via intervening buffer 42) and also receives a control signal (drp _ vref, as mentioned in connection with fig. 1). Drp _ vref through voltage regulator 14 is equal to (from fig. 1) vdd 4. In other words, drp _ vref is equal in voltage magnitude to vdd4, where vdd4 is generated as the output of voltage regulator 14 (e.g., consuming vdd9, e.g., 1.8 v). In one embodiment, drp _ vref is a 6-bit field that can be controlled by any of a number of different sources (including scans, fuses, microcode, digital logic, etc.).

Fig. 3C is a schematic diagram illustrating an embodiment of DAC 44. In one embodiment, DAC 44 is implemented as a resistor ladder having an R2R ladder configuration, as is known in the industry. As shown in fig. 3C, each branch is controlled by a digital input bit that switches between filtered vdd _ cpu (input) and analog ground (e.g., vss9 from fig. 1). Each logic gate (for each branch) receives a given bit configuration drp _ vref (e.g., drp _ vref [0],. drp _ vref [5 ]) of the control signal, where the resistor network causes the bits to be weighted in their contribution to the output.

Filtered, scaled vdd _ cpu [ (drp _ vref [ 5: 0])/(2^6) ] × filtered vdd _ cpu.

Note that falling reference device 38 is described above as a circuit of falling detector 12, but in some embodiments falling reference device 38 may include intervening circuitry between falling detector 12 and voltage regulator 14.

Having described certain embodiments of a descent detection system, it should be understood that one embodiment of an example method (represented as method 54 in FIG. 4) performed by an embodiment of a descent reference device includes: filtering (56) the supply voltage using a programmable low pass filter; and providing, by the digital-to-analog converter, a scaled version (58) of the filtered supply voltage.

Additionally, it should be appreciated that one embodiment of an exemplary method (represented as method 60 in FIG. 5) performed by an embodiment of a droop detector includes: generating a signal (62) from a reference oscillator; applying a phase delay (64) in a signal received from the reference oscillator over a plurality of delay lines; and detecting a droop (66) in the voltage regulator based on receiving the output of the voltage regulator and the output from each of the plurality of delay lines.

Any process descriptions or blocks in flow charts should be understood as representing modules, segments, logic, or portions of code which include one or more executable instructions for implementing specific logical functions or steps in the process, and alternate implementations are included within the scope of the embodiments in which functions may be executed out of order from that shown or discussed (including substantially concurrently or in a different order), depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Note that different combinations of the disclosed embodiments can be used, and thus reference to an embodiment or one embodiment is not meant to exclude features from that embodiment from being used with features from other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.