阅读说明：本技术 一种基于Ka波段相控阵雷达应用的延迟线电路 (A kind of delay line based on the application of Ka wave band phased-array radar ) 是由 张�浩 郭健 姚鸿 于 2019-07-31 设计创作，主要内容包括：本申请公布了一种基于Ka波段相控阵雷达应用的延迟线电路版图。在砷化镓衬底上布置有高电子迁移率晶体管。所述一种基于Ka波段相控阵雷达应用的延迟线由四级延迟线单元设计,延迟线单元通过参考支节和延迟支节串联一对单刀双掷开关构成。所述单刀双掷开关由两对高电子迁移率晶体管构成。晶体管栅极与高阻值电阻串联,并且连接直流电压源,构成直流偏置电路。所述单刀双掷开关通过偏置电路改变偏置电压控制射频通路选择,实现高精度延迟目的。本申请还公布了一种集成电路。本申请提供的基于Ka波段相控阵雷达应用的延迟线,具有低损耗、高延迟精度以及紧凑型电路尺寸等优点,适用于Ka波段相控阵雷达应用中。(The application discloses a kind of delay line domain based on the application of Ka wave band phased-array radar.High electron mobility transistor is disposed in gallium arsenide substrate.A kind of delay line based on the application of Ka wave band phased-array radar is designed by level Four delay line, and delay line is constituted by reference to detail and a pair of of single-pole double-throw switch (SPDT) of delay detail series connection.The single-pole double-throw switch (SPDT) is made of two pairs of high electron mobility transistor.Transistor gate is connected with high resistance measurement, and connects DC voltage source, constitutes DC bias circuit.The single-pole double-throw switch (SPDT) changes bias voltage by biasing circuit and controls radio frequency path selection, realizes high-precision delay purpose.A kind of integrated circuit is also disclosed in the application.Delay line provided by the present application based on the application of Ka wave band phased-array radar, has many advantages, such as low-loss, high latency precision and compact circuit size, suitable for the application of Ka wave band phased-array radar.)

1. a kind of delay line domain based on the application of Ka wave band phased-array radar, which is characterized in that cloth in gallium arsenide substrate It is equipped with high electron mobility transistor.

2. a kind of delay line domain based on the application of Ka wave band phased-array radar according to claim 1, feature It is, the delay line is designed by three-level delay line, is attached between delay line by impedance matching network.

3. a kind of delay line domain based on the application of Ka wave band phased-array radar according to claim 1, feature It is, delay line is made of reference detail and a pair of of single-pole double-throw switch (SPDT) of delay detail series connection.

4. a kind of delay line domain based on the application of Ka wave band phased-array radar according to claim 1, feature It is, single-pole double-throw switch (SPDT) is made of symmetrical two pairs of high electron mobility transistor, high electron mobility transistor grid and height Valued resistor series connection, and DC voltage bias circuit is connected to form with DC voltage source.

5. a kind of delay line domain based on the application of Ka wave band phased-array radar according to claim 1, feature Be, the single-pole double-throw switch (SPDT) in the delay line respectively by different DC biased voltage (V _state1、V _state2) realization pair The selection of different radio frequency access.

6. a kind of delay line domain based on the application of Ka wave band phased-array radar according to claim 1, feature It is, selects simple transmission line or T-shape detail with reference to detail in the delay cell.

7. a kind of delay line domain based on the application of Ka wave band phased-array radar according to claim 1, feature It is, the resonant element that delay detail selects capacitor and inductance to constitute, the resonant element can be multiple；In design different delays When unit, phase delay purpose is realized by adjusting resonant element quantity.

8. a kind of semiconductor integrated circuit, which is characterized in that any comprising claim 1 to 7 in the semiconductor integrated circuit A kind of circuit layout based on the application of Ka wave band phased-array radar described in.

Technical field

This application involves semiconductor integrated circuit field more particularly to a kind of prolonging based on the application of Ka wave band phased-array radar Slow line circuit layout.

Background technique

Ka wave band phased-array radar has own strategic significance in modern war；However, delay line is as phased array thunder Key technology in reaching also attracts attention more and more in recent years.Therefore, design there is low-loss, high-precision to postpone small Type delay line is equally of great significance.

Summary of the invention

The present invention provides a kind of delay line domains and integrated circuit based on the application of Ka wave band phased-array radar.It should Delay line is designed by multilevel delay line unit, has the characteristics that low-loss and high latency precision, is suitable for Ka wave band phased-array radar In.

Thus the technical solution adopted by the present invention is that: it is a kind of based on Ka wave band phased-array radar application delay line version Scheme, is disposed with high electron mobility transistor in gallium arsenide substrate.

The delay line is designed by three-level delay line, is connected between delay line by impedance matching network It connects.

Delay line is made of reference detail and a pair of of single-pole double-throw switch (SPDT) of delay detail series connection.

Single-pole double-throw switch (SPDT) is made of symmetrical two pairs of high electron mobility transistor, high electron mobility transistor grid with High resistance measurement series connection, and DC voltage bias circuit is connected to form with DC voltage source；It is realized by changing bias voltage The selection of different radio frequency access, and then realize the purpose of signal delay output.

Single-pole double-throw switch (SPDT) in the delay line respectively by different DC biased voltage (V _state1、V _state2) realize Selection to different radio frequency access.

Simple transmission line or T-shape detail are selected with reference to detail in the delay cell.

Postpone the resonant element that detail selects capacitor and inductance to constitute, it is different that resonant element quantity difference will lead to delay； When designing different delays unit, phase delay purpose is realized by adjusting resonant element quantity.

A kind of semiconductor integrated circuit is based on Ka wave band phased array comprising described one kind in the semiconductor integrated circuit The circuit layout of radar application.

The invention has the advantages that delay line of the present invention can be realized Ka wave band is compact, miniaturized circuit design.Meanwhile Low-loss, high latency precision can be realized using gallium arsenide substrate high electron mobility transistor, compared to INVENTIONConventional metal-oxide Semiconductor field, the delay line have more preferably loss, delay performance, suitable for the application of Ka wave band phased-array radar.

Detailed description of the invention

Fig. 1 delay line designs circuit diagram.

Fig. 2 single-pole double-throw switch (SPDT) circuit diagram.

The delay line design principle block diagram that Fig. 3 is applied based on Ka wave band phased-array radar.

The delay line domain that Fig. 4 the application case study on implementation is applied based on Ka wave band phased-array radar.

Specific embodiment

To keep the technical principle, feature and technical effect of technical scheme clearer, below in conjunction with specific implementation Technical scheme is described in detail in case.

Fig. 1 is the delay line design circuit theory that the application case study on implementation is applied based on Ka wave band phased-array radar Figure.The selection to reference detail and delay detail is realized by a pair of identical single-pole double-throw switch (SPDT), to realize that signal delay is defeated Purpose out.

Single-pole double-throw switch (SPDT) shown in Fig. 1 is made of symmetrical two pairs of high electron mobility transistor, and is distributed in portP ₁Two sides (shown in Fig. 2).High electron mobility transistor by different bias voltages (V _stage1、V _stage2) realize that different radio frequency is logical The selection on road, i.e. portP ₁To portP ₂Or portP ₁To portP ₃The selection of radio frequency path.The grid of high electron mobility transistor Pole connect high-impedance resistors (R _dc) realize bias circuit.

Delay line design principle block diagram based on the application of Ka wave band phased-array radar described in Fig. 3.It is more fine in order to realize Delay purpose, using three-level delay line design form.Maximum power is realized by impedance matching network between delay line Transmit purpose.Delay line bias voltage, which is split, meets the subsequent delay based on the application of Ka wave band phased-array radar in side The linearly On-wafer measurement demand of energy.

The delay line domain applied for the application case study on implementation based on Ka wave band phased-array radar described in Fig. 4.Delay Line unit biasing circuit is split in domain side, facilitates subsequent On-wafer measurement.Pass through impedance matching between three-level delay line Circuit is connected with each other, and realizes that circuit layout is compact, minimizes purpose, suitable for the application of Ka wave band phased-array radar.

The foregoing is merely the preferable case study on implementation of the application, all at this not to limit the protection scope of the application Apply within the spirit and principle of technical solution, any modification, equivalent substitution, improvement and etc. done should be included in this Shen Within the scope of please protecting.