阅读说明：本技术 绝缘栅极晶体管及其制备方法和应用 (Insulated gate transistor and its preparation method and application ) 是由 冯宇翔 张远浩 李媛媛 于 2019-08-19 设计创作，主要内容包括：本发明提出了绝缘栅极晶体管及其制作方法和应用。该绝缘栅极晶体管包括：漂移区；P阱区,设置在漂移区的一侧；有源区,设置在P阱区远离漂移区的一侧；栅极,设置在P阱区远离漂移区的一侧；发射极,设置在有源区和P阱区远离漂移区的一侧；缓冲层,设置在漂移区远离栅极的一侧；集电区,设置在缓冲层远离漂移区的一侧；集电极,设置在集电区远离漂移区的一侧；其中,集电区由多个P<Sup>+</Sup>离子掺杂的第一层和多个P<Sup>-</Sup>离子掺杂的第二层交替层叠设置。本发明所提出的绝缘栅极晶体管,其集电区由P<Sup>+</Sup>/P<Sup>-</Sup>复合结构层组成,优化少子的注入效率,降低关断损耗和反向电流对器件损坏的风险,有利于漂移区中载流子浓度的均匀分布,从而具有更加优化的动态和静态损耗。(The invention proposes insulated gate transistors and preparation method thereof and application.The insulated gate transistor includes: drift region；The side of drift region is arranged in p-well region；Side of the p-well region far from drift region is arranged in active area；Side of the p-well region far from drift region is arranged in grid；The side of active area and p-well region far from drift region is arranged in emitter；Side of the drift region far from grid is arranged in buffer layer；Side of the buffer layer far from drift region is arranged in collecting zone；Side of the collecting zone far from drift region is arranged in collector；Wherein, collecting zone is by multiple P + The first layer of ion doping and multiple P ‑ The alternately laminated setting of the second layer of ion doping.Insulated gate transistor proposed by the invention, collecting zone is by P + /P ‑ Composite construction layer composition optimizes the injection efficiency of few son, reduces turn-off power loss and reverse current to the risk of device failure, is conducive to being uniformly distributed for carrier concentration in drift region, to have more optimal dynamic and quiescent dissipation.)

1. a kind of insulated gate transistor characterized by comprising

Drift region；

The side of the drift region is arranged in p-well region, the p-well region；

Side of the p-well region far from the drift region is arranged in active area, the active area；

Side of the p-well region far from the drift region is arranged in grid, the grid；

The side of the active area and the p-well region far from the drift region is arranged in emitter, the emitter；

Side of the drift region far from the grid is arranged in buffer layer, the buffer layer；

Side of the buffer layer far from the drift region is arranged in collecting zone, the collecting zone；

Side of the collecting zone far from the drift region is arranged in collector, the collector；

Wherein, the collecting zone is by multiple first layers and the alternately laminated setting of multiple second layers, and the first layer is P⁺Ion is mixed Miscellaneous, the second layer is P^-Ion doping.

2. insulated gate transistor according to claim 1, which is characterized in that the first layer with a thickness of 120~ 150nm。

3. insulated gate transistor according to claim 1, which is characterized in that the second layer with a thickness of 80~ 100nm。

4. insulated gate transistor according to claim 1, which is characterized in that of the first layer and the second layer Number is respectively 2~4.

5. insulated gate transistor according to claim 1, which is characterized in that the P of the first layer⁺Ion doping concentration It is 5 × 10¹⁸~1 × 10¹⁹cm^-3；And/or

The P of the second layer^-Ion doping concentration is 1 × 10¹⁷~5 × 10¹⁷cm^-3。

6. a kind of method for preparing insulated gate transistor characterized by comprising

P ion injection is carried out to a surface of the substrate of N- ion doping, to form p-well region and drift region；

N is carried out far from the surface of the drift region to the p-well region⁺Ion implanting, to form active area；

Metal deposit is carried out on the surface of the active area, the p-well region and the drift region, to form grid and emitter；

N is carried out far from the surface of the grid to the drift region⁺Ion implanting, to form buffer layer；

P ion injection is carried out far from the surface of the drift region to the buffer layer, to form collecting zone, and the collecting zone by Multiple first layers and the successively alternately laminated setting of multiple second layers, also, the first layer is P⁺Ion doping, the second layer For P^-Ion doping；

Metal deposit is carried out far from the surface of the drift region in the collecting zone, to form collector.

7. according to the method described in claim 6, it is characterized in that, the step of formation collecting zone include:

P is carried out far from the surface of the drift region to the buffer layer^-Ion implanting, to form the second layer；

P is carried out far from the surface of the drift region to the second layer⁺Ion implanting, to form first layer；

It is alternately repeated the multiple P^-Ion implanting and the multiple P⁺Ion implanting, to form collecting zone.

8. the method according to the description of claim 7 is characterized in that the P^-The doping concentration of ion implanting is 5 × 10¹⁸~1 ×10¹⁹cm^-3；And/or the P^-+The doping concentration of ion implanting is 1 × 10¹⁷~5 × 10¹⁷cm^-3。

9. a kind of intelligent power module characterized by comprising

Circuit substrate is provided with wiring on the circuit substrate, and the wiring includes welding device region；

At least one insulated gate transistor according to any one of claims 1 to 8, the bottom side of the insulated gate transistor Face is welded in the welding device region, and the top side face of the insulated gate transistor bridges to the circuit cloth by metal connection Line.

10. a kind of air conditioner, which is characterized in that including intelligent power module as claimed in claim 9.

Technical field

The present invention relates to technical field of semiconductors, specifically, the present invention relates to insulated gate transistors and preparation method thereof And application.More specifically, the present invention relates to insulated gate transistor and preparation method thereof, intelligent power module and air conditioners.

Background technique

Insulated gate bipolar transistor (IGBT) has both the current capacity and insulating gate type field effect tube of bipolar transistor (BJT) (MOSFET) voltage controls feature, is a kind of high current, high-power switch device.It include grid (G), emitter in structure (E), collector (C) and drift region (N^-) and back side collecting zone (P⁺) etc., its working principle is that after grid reaches threshold voltage, Channel conducting, collecting zone inject few sub- hole to drift region, play the role of conductance modulation, and few son injection is more, and conduction loss is got over It is small.But corresponding tail currents effect will be bigger, turn-off power loss is bigger, therefore, conducting of the injection of few son concerning device And turn-off power loss.Also, there is also contradictory relations for the two, generally use at present collecting zone regional area minority carrier life time control or Reduce the tradeoff of the method optimization turn-on and turn-off loss of few sub- injection efficiency.

Summary of the invention

The present invention is the following discovery based on inventor and completes:

The present inventor has found in the course of the research, in order to shorten the service life of few son or reduce the injection effect of few son Rate, it will usually introduce local defect area in collecting zone, or introduce in collecting zone the N of the different conduction-types of isolation⁺Region Collecting zone short-circuit structure is set, and above method is to introduce that local conduction type is different or material in collecting zone below drift region Expect the inconsistent region of performance, after causing few son to be injected into drift region, the meeting in the transversely and horizontally concentration distribution of cellular drift region There are bigger uneven concentration.But in actual application process, carrier concentration profile in the drift region IGBT It unevenly also will increase the conduction loss of device, can have large effect to the performance of device instead.

So inventor designs one kind by P⁺/P^-The collecting zone of composite construction layer composition, can not only optimize the note of few son Enter efficiency, to accelerate the extraction speed of shutdown Shi Shaozi, improve turn-off speed, reduces current tail effect, and then reduce and close Breakdown consumption and reverse current are to the risk of device failure, in addition, being uniformly distributed for carrier concentration in drift region is also helped, from And make insulated gate transistor that there is more optimal dynamic and static loss.

In the first aspect of the present invention, the invention proposes a kind of insulated gate transistors.

According to an embodiment of the invention, the insulated gate transistor includes: drift region；P-well region, the p-well region setting In the side of the drift region；Side of the p-well region far from the drift region is arranged in active area, the active area；Grid, Side of the p-well region far from the drift region is arranged in the grid；Emitter, the emitter are arranged in the active area Side with the p-well region far from the drift region；Buffer layer, the buffer layer are arranged in the drift region far from the grid Side；Side of the buffer layer far from the drift region is arranged in collecting zone, the collecting zone；Collector, the current collection Side of the collecting zone far from the drift region is arranged in pole；Wherein, the collecting zone is by multiple first layers and multiple second The alternately laminated setting of layer, and the first layer is P⁺Ion doping, the second layer are P^-Ion doping.

Inventor has found that the insulated gate transistor of the embodiment of the present invention, collecting zone is by P⁺/P^-Composite junction Structure layer composition, can not only optimize the injection efficiency of few son, thus reduce turn-off power loss and reverse current to the risk of device failure, Being uniformly distributed for carrier concentration in drift region is also helped, to make it have more optimal dynamic loss and static damage Consumption.

In addition, insulated gate transistor according to the above embodiment of the present invention, can also have following additional technology special Sign:

According to an embodiment of the invention, the first layer with a thickness of 120~150nm.

According to an embodiment of the invention, the second layer with a thickness of 80~100nm.

According to an embodiment of the invention, the number of the first layer and the second layer is respectively 2~4.

According to an embodiment of the invention, the P of the first layer⁺Ion doping concentration is 5 × 10¹⁸~1 × 10¹⁹cm^-3；With/ Or, the P of the second layer^-Ion doping concentration is 1 × 10¹⁷~5 × 10¹⁷cm^-3。

In the second aspect of the present invention, the invention proposes a kind of methods for preparing insulated gate transistor.

According to an embodiment of the invention, the described method includes: carrying out P ion to a surface of the substrate of N- ion doping Injection, to form p-well region and drift region；N is carried out far from the surface of the drift region to the p-well region⁺Ion implanting, to be formed Active area；Metal deposit is carried out on the surface of the active area, the p-well region and the drift region, to form grid and transmitting Pole；N is carried out far from the surface of the grid to the drift region⁺Ion implanting, to form buffer layer；It is separate to the buffer layer The surface of the drift region carries out P ion injection, and to form collecting zone, and the collecting zone is by multiple first layers and multiple second Layer successively alternately laminated setting, also, the first layer is P⁺Ion doping, the second layer are P^-Ion doping；In the collection Electric area carries out metal deposit far from the surface of the drift region, to form collector.

Inventor has found that using the preparation method of the embodiment of the present invention, it can be by adjusting the agent of P ion injection Amount or Implantation Energy form P⁺/P^-The collecting zone of compound alternate laminated structure, so as to prepare, turn-off power loss is lower, reversed electricity Flow, dynamic loss lower to device failure risk and all more optimized insulated gate transistor of quiescent dissipation.

In addition, preparation method according to the above embodiment of the present invention, can also have the following additional technical features:

According to an embodiment of the invention, the step of formation collecting zone includes: to the buffer layer far from the drift The surface in area carries out P^-Ion implanting, to form the second layer；P is carried out far from the surface of the drift region to the second layer⁺Ion Injection, to form first layer；It is alternately repeated the multiple P^-Ion implanting and the multiple P⁺Ion implanting, to form collecting zone.

According to an embodiment of the invention, the P^-The doping concentration of ion implanting is 5 × 10¹⁸~1 × 10¹⁹cm^-3；With/ Or, the P^-+The doping concentration of ion implanting is 1 × 10¹⁷~5 × 10¹⁷cm^-3。

In the third aspect of the present invention, the invention proposes a kind of intelligent power module.

According to an embodiment of the invention, the intelligent power module includes: circuit substrate, it is provided on the circuit substrate Wiring, and the wiring includes welding device region；At least one above-mentioned insulated gate transistor, the insulated gate The bottom side of gated transistors is welded in the welding device region, and the top side face of the insulated gate transistor passes through metal connecting bridge It is connected to the wiring.

Inventor has found that the intelligent power module of the embodiment of the present invention, the shutdown of insulated gate transistor It is all more optimized that lower, reverse current lower to device failure risk, dynamic loss and quiescent dissipation is lost, to make intelligent power The loss of module is lower, longer life expectancy.It will be appreciated to those of skill in the art that being retouched above for insulated gate transistor The feature and advantage stated are still applied to the intelligent power module, and details are not described herein.

In the fourth aspect of the present invention, the invention proposes a kind of air conditioners.

According to an embodiment of the invention, the air conditioner includes above-mentioned intelligent power module.

Inventor has found that the air conditioner of the embodiment of the present invention, the loss of intelligent power module is lower and the longevity Order it is longer, to keep the stability of the long-time service of the air conditioner higher and longer life expectancy.Skilled artisans appreciate that , above for feature and advantage described in intelligent power module, it is still applied to the air conditioner, details are not described herein.

Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description Obviously, or practice through the invention is recognized.

Detailed description of the invention

Above-mentioned aspect combination following accompanying drawings of the invention explains the description of embodiment, in which:

Fig. 1 is the cross section structure schematic diagram of the insulated gate transistor of one embodiment of the invention；

Fig. 2 is the method flow schematic diagram for preparing insulated gate transistor of one embodiment of the invention；

Fig. 3 is the schematic top plan view that the exposure mask of active area is made in the preparation method of one embodiment of the invention.

Appended drawing reference

100 drift regions

200 p-well regions

210 mask regions

220 blank areas

300 active areas

400 grids

500 emitters

600 buffer layers

700 collecting zones

710 first layers

720 second layers

800 collectors

Specific embodiment

The embodiment of the present invention is described below in detail, those skilled in the art is it will be appreciated that following example is intended for solving The present invention is released, and is not construed as limitation of the present invention.Unless stated otherwise, it is not expressly recited in embodiment below specific Technology or conditions, those skilled in the art can be according to common technology or conditions in the art or according to product description It carries out.

In one aspect of the invention, the invention proposes a kind of insulated gate transistors.

According to an embodiment of the invention, with reference to Fig. 1, insulated gate transistor includes drift region 100, p-well region 200, active Area 300, grid 400, emitter 500, buffer layer 600, collecting zone 700 and collector 800；Wherein, the setting of p-well region 200 is being floated Move the side in area 100；Side of the p-well region 200 far from drift region 100 is arranged in active area 300；Grid 400 is arranged in p-well region 200 sides far from drift region 100；The side of active area 300 and p-well region 200 far from drift region 100 is arranged in emitter 500； Side of the drift region 100 far from grid 400 is arranged in buffer layer 600；Collecting zone 700 is arranged in buffer layer 600 far from drift region 100 side；And side of the collecting zone 700 far from drift region 100 is arranged in collector 800；Wherein, collecting zone 700 is by multiple First layer 710 and the alternately laminated setting of multiple second layers 720, and first layer 710 is P⁺Ion doping, the second layer 720 are P^-Ion Doping.It should be noted that herein " being stacked " specifically refer to from collector 800 on the direction of drift region 100 successively Be stacked, i.e., according to first layer 710, the second layer 720 ..., repetition period of first layer 710, the second layer 720 arranges repeatedly Column.

Inventor has found in the course of the research, compared with conventional single-layer and transparent collecting zone, P+/P^-What alternating was compounded to form Collecting zone, in device forward conduction, P⁺Layer is relative to P^-Few son that layer is injected into drift region 100 is relatively more, so P⁺Layer It ensure that less the injection efficiency in sub- hole, and P^-Layer reduces storage of few son in drift layer 100；In addition, P⁺/P^-Alternately shape At structure also may make hole toward drift layer 100 inject process it is more uniform, be conducive to carrier in drift region 100 It is uniformly distributed, and then is effectively improved the dynamic loss and shock resistance of device.

According to an embodiment of the invention, P⁺The specific thickness of the first layer 710 of ion doping, those skilled in the art can roots Factually the injection efficiency after the few son optimization in border is correspondingly designed.In some embodiments of the invention, the thickness of first layer 710 Degree can be 120~150nm, in this way, relatively thin P⁺Ion doping first layer 710 can further make hole past from collecting zone 700 The process that drift layer 100 injects is more uniform, to keep device performance more preferable.

According to an embodiment of the invention, P^-The specific thickness of the second layer 720 of ion doping, those skilled in the art can roots Factually the injection efficiency after the few son optimization in border is correspondingly designed.In some embodiments of the invention, the thickness of the second layer 720 Degree can be 80~100nm, in this way, relatively thin P^-The ion doping second layer 720 can further make hole past from collecting zone 700 The process that drift layer 100 injects is more uniform, to keep device performance more preferable.

According to an embodiment of the invention, P⁺The first layer 710 and P of ion doping^-The second layer 720 of ion doping it is specific Number, those skilled in the art can carry out phase according to few sub- charge velocity actual effect of optimization of the collecting zone 700 to drift region 100 It selects with answering.In some embodiments of the invention, the number of first layer 710 and the second layer 720 can be respectively 2~4, tool Body is for example all 2, in this way, the charge velocity of more optimized few son, so that the extraction speed of shutdown Shi Shaozi is further speeded up, into One step improves turn-off speed, more reduction current tail effect, and then further decreases turn-off power loss and reverse current and damage to device Bad risk.

According to an embodiment of the invention, the P of first layer 710⁺The P of ion and the second layer 720^-The specific doping concentration of ion It is not particularly limited, as long as first layer 710 is different from the P ion concentration of the second layer 720, those skilled in the art can root Factually border collecting zone 700 correspondingly selects the actual optimization effect of the charge velocity of few son.In some realities of the invention It applies in example, the P of first layer 710⁺Ion doping concentration can be 5 × 10¹⁸~1 × 10¹⁹cm^-3, and the P of the second layer 720^-Ion is mixed Miscellaneous concentration can be 1 × 10¹⁷~5 × 10¹⁷cm^-3, in this way, the second layer of the first layer 710 of high-dopant concentration and low doping concentration The collecting zone of 720 alternately laminated distribution compositions, can preferably optimize the charge velocity of few son, and be more advantageous to current-carrying in drift region Sub- concentration is uniformly distributed.

In conclusion according to an embodiment of the invention, the invention proposes a kind of insulated gate transistor, collecting zone by P⁺/P^-Composite construction layer composition, can not only optimize the injection efficiency of few son, to reduce turn-off power loss and reverse current to device The risk of damage also helps being uniformly distributed for carrier concentration in drift region, to make it have more optimal dynamic damage Consumption and quiescent dissipation.

In another aspect of the invention, the invention proposes a kind of methods for preparing insulated gate transistor.According to this The embodiment of invention, with reference to Fig. 2, which includes:

S100: P ion injection is carried out to a surface of the substrate of N- ion doping, to form p-well region and drift region.

In this step, P ion injection is carried out to a surface of the substrate of N- ion doping, to form 200 He of p-well region Drift region 100.According to an embodiment of the invention, the concrete shape of p-well region 200, those skilled in the art can be according to insulated gate electrode The structure design of transistor is correspondingly planned that details are not described herein.

S200: N is carried out far from the surface of drift region to p-well region⁺Ion implanting, to form active area.

In this step, N is carried out far from the surface of drift region 100 to p-well region 200⁺Ion implanting, to form active area 300.According to an embodiment of the invention, the concrete shape of active area 300, those skilled in the art can also be according to insulated gate electrode crystal The structure design of pipe is correspondingly planned that details are not described herein.

In some embodiments of the invention, it for the insulated gate transistor of silicon carbide (SiC) substrate, can be designed to Transversal device, as long as forming the insulating regions of isolation between cellular (i.e. single insulated gate transistor).Specifically, It, can first in one layer 1.5~3 microns of the positive extension of substrate (such as sputtering or chemical vapor deposition), (such as 2 is micro- with reference to Fig. 3 Rice) thick silica (SiO₂) protective layer, and mask regions 210 and window region 220 in Fig. 3 are etched by photoetching process, In, the process island (such as active area 200) of the corresponding multiple cellulars in mask regions 210, and between the corresponding multiple process islands of window region 220 Gap；Then, the temperature by high temperature tension technology at 500~700 degrees Celsius (such as 600 degrees centigrades) is betted Enter ion (such as B, P or N etc.), in this way, 210 protected seam of mask regions is protected without being influenced by ion implanting, window region 220 are influenced by ion implanting, and surfacing is generated deep energy level defect by bombardment damage, to make the material of window region 220 High-impedance state is presented in material, and then forms the insulating regions of isolation.Finally, again can be by mask regions by the method for wet etching The protective layer on 210 surfaces removes, in this way, can continue subsequent device technology.

With silicon carbide transversal device frequently with plough groove type table top interval mode compared with, local ion injects the height to be formed Hinder isolated area, neither be used in component between etch deep trench, without again in the trench fill spacer medium layer.Also, make The isolation that silicon carbide transversal device obtains electric property on the basis of planar technology is obtained, device is avoided and is easily led due to step The mask spreadability of cause is bad, metal connecting line is broken bad and complicated difficulty in process technical problem, moreover, real in the plane Existing device is effectively isolated, and is conducive to improve device integration.

S300: metal deposit is carried out on active area, p-well region and the surface of drift region, to form grid and emitter.

In this step, metal deposit is carried out on the surface of active area 300, p-well region 200 and drift region 100, can be formed Grid 400 and emitter 500.Specifically, p-well region 200 and the drift region 100 of 400 covering part of grid, and emitter 500 covers The active area 300 and p-well region 200 of cover.

According to an embodiment of the invention, the concrete mode of metal deposit, those skilled in the art can be according to grid 400 and hair The real material of emitter-base bandgap grading 500 is correspondingly selected, and specifically such as physical vaporous deposition (PVD), details are not described herein.

S400: N is carried out far from the surface of grid to drift region⁺Ion implanting, to form buffer layer.

In this step, N is carried out at the back side of substrate⁺Ion implanting carries out N far from the surface of grid to drift region⁺From Son injection, can form buffer layer 600.

S500: P ion injection is carried out far from the surface of drift region to buffer layer, to form collecting zone.

In this step, P ion injection is carried out far from the surface of drift region 200 to buffer layer 600, to form collecting zone 700, and collecting zone 700 is by multiple first layers 710 and the successively alternately laminated setting of multiple second layers 720, also, first layer 710 For P⁺Ion doping, the second layer 720 are P^-Ion doping.

In some embodiments of the invention, step S500 may include: S510 to buffer layer 600 far from drift region 100 Surface carry out P^-Ion implanting, to form the second layer 720；S520 carries out P far from the surface of drift region 100 to the second layer 720⁺ Ion implanting, to form first layer 710；S530 is alternately repeated multiple P^-Ion implanting and multiple P⁺Ion implanting, to form current collection Area 700.In this way, the collecting zone 700 produced is formed by different P ion implanted layers is compound.

According to an embodiment of the invention, the repetition period can be 2~4 times, in this way, forming 4~8 layers of P+/P- composite construction The collecting zone of layer composition, can preferably optimize the charge velocity of few son, so that the extraction speed of shutdown Shi Shaozi is further speeded up, Turn-off speed is further increased, more reduction current tail effect, and then further decreases turn-off power loss and reverse current to device The risk of damage.

In some embodiments of the invention, the P of first layer 710⁺Ion doping concentration can be 5 × 10¹⁸~1 × 10¹⁹cm^-3, and the P of the second layer 720^-Ion doping concentration can be 1 × 10¹⁷~5 × 10¹⁷cm^-3, in this way, high-dopant concentration The collecting zone of the alternately laminated distribution composition of the second layer 720 of first layer 710 and low doping concentration, can preferably optimize the note of few son Enter rate, and is more advantageous to being uniformly distributed for carrier concentration in drift region.

S600: metal deposit is carried out far from the surface of drift region in collecting zone, to form collector.

In this step, metal deposit is carried out far from the surface of drift region 100 in collecting zone 700, to form collector 800.In this way, the perfect insulated gate transistor of structure and function can be prepared.

In conclusion according to an embodiment of the invention, the invention proposes a kind of preparation method, it can be by adjusting P ion The dosage or Implantation Energy of injection form P⁺/P^-The collecting zone of compound alternate laminated structure, so as to prepare turn-off power loss more Low, reverse current is lower to device failure risk, dynamic loss and all more optimized insulated gate transistor of quiescent dissipation.

In another aspect of the invention, the invention proposes a kind of intelligent power module.

According to an embodiment of the invention, intelligent power module includes that circuit substrate and at least one above-mentioned insulated gate electrode are brilliant Body pipe；Wherein, wiring is provided on circuit substrate, and wiring includes welding device region；And insulated gate transistor Bottom side be welded in the welding device region, the top side face of insulated gate transistor bridges to the circuit by metal connection Wiring.

In conclusion according to an embodiment of the invention, insulated gate electrode is brilliant the invention proposes a kind of intelligent power module The turn-off power loss of body pipe is lower, reverse current is lower to device failure risk, dynamic loss and quiescent dissipation are all more optimized, thus Make that the loss of intelligent power module is lower, longer life expectancy.It will be appreciated to those of skill in the art that above for insulated gate electrode Feature and advantage described in transistor are still applied to the intelligent power module, and details are not described herein.

In another aspect of the invention, the invention proposes a kind of air conditioners.

According to an embodiment of the invention, air conditioner includes above-mentioned intelligent power module.

It should be noted that the air conditioner further includes necessary composition and knot other than above-mentioned intelligent power module Structure, specifically such as blower, compressor, heat exchanger, orifice union, wind guide component, chassis, panel, those skilled in the art can It is correspondingly designed and is supplemented according to the function of the air conditioner, details are not described herein.

In conclusion according to an embodiment of the invention, the invention proposes a kind of air conditioner, the damage of intelligent power module Lower and longer life expectancy is consumed, to keep the stability of the long-time service of the air conditioner higher and longer life expectancy.Those skilled in the art Member is, it is understood that be still applied to the air conditioner, herein not above for feature and advantage described in intelligent power module It repeats again.

In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.

In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three It is a etc., unless otherwise specifically defined.

In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples It closes and combines.

Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned Embodiment is changed, modifies, replacement and variant.