阅读说明：本技术 一种iii族氮化物晶体管外延结构和晶体管器件 (A kind of III-nitride transistor epitaxial structure and transistor device ) 是由 何佳琦 汪青 于洪宇 于 2019-09-09 设计创作，主要内容包括：本发明公开了一种III族氮化物晶体管外延结构。该III族氮化物晶体管外延结构包括衬底以及依次叠层在所述衬底上的成核层,缓冲层,沟道层和势垒层；所述衬底包括多个凹槽结构和位于所述凹槽结构之间的生长窗口；所述成核层位于所述衬底的所述生长窗口；所述缓冲层包括形成在合并区的沿所述生长窗口指向与其相邻的所述凹槽结构的方向外延生长的半极性Ⅲ族氮化物和形成在窗口区的沿与所述衬底所在平面垂直的方向外延生长的所述半极性Ⅲ族氮化物；所述沟道层和所述势垒层均为半极性Ⅲ族氮化物,所述合并区和所述窗口区均延伸到所述沟道层和所述势垒层。该III族氮化物晶体管外延结构有助于实现制备高电子迁移率、低横向漏电的增强型HEMT器件。(The invention discloses a kind of III-nitride transistor epitaxial structures.The III-nitride transistor epitaxial structure includes substrate and the successively nucleating layer of lamination over the substrate, buffer layer, channel layer and barrier layer；The substrate includes multiple groove structures and the growth window between the groove structure；The nucleating layer is located at the growth window of the substrate；The buffer layer includes III group-III nitride of semi-polarity for the direction epitaxial growth that the groove structure adjacent thereto is directed toward along the growth window for being formed in assembly section and III group-III nitride of the semi-polarity along the direction epitaxial growth vertical with plane where the substrate for being formed in window region；The channel layer and the barrier layer are III group-III nitride of semi-polarity, and the assembly section and the window region each extend to the channel layer and the barrier layer.The III-nitride transistor epitaxial structure helps to realize the enhanced HEMT device for preparing high electron mobility, low cross electric leakage.)

1. a kind of III-nitride transistor epitaxial structure, which is characterized in that the III-nitride transistor epitaxial structure Including the substrate and successively nucleating layer of lamination over the substrate, buffer layer, channel layer and barrier layer；

The substrate includes multiple groove structures and the growth window between the groove structure；

The nucleating layer is located at the growth window of the substrate；

The buffer layer includes the side that the groove structure adjacent thereto is directed toward along the growth window for being formed in assembly section To epitaxial growth III group-III nitride of semi-polarity and be formed in outside the edge direction vertical with plane where the substrate of window region Prolong III group-III nitride of the semi-polarity of growth；

The channel layer and the barrier layer are III group-III nitride of semi-polarity, and the assembly section and the window region each extend to The channel layer and the barrier layer.

2. III-nitride transistor epitaxial structure according to claim 1, which is characterized in that the nucleating layer includes It is multiple be scattered in the substrate surface at nuclear island；

Positioned at the closest growth window and the direction of growth at nuclear island of the groove structure boundary line and the lining The angle of plane is greater than 0 ° where substrate, and less than 90 °.

3. III-nitride transistor epitaxial structure according to claim 2, which is characterized in that the material at nuclear island Material is GaN or AlN.

4. III-nitride transistor epitaxial structure according to claim 1, which is characterized in that the groove structure is Bar shaped；Multiple groove structures extend in a first direction, and arrange in a second direction；The first direction and the second direction It is parallel with plane where the substrate；III group-III nitride of semi-polarity is hexagonal wurtzite structure, and the first direction is III group-III nitride of the semi-polarity of the assembly section projects to the direction a when hexagonal wurtzite structure (0001) face, and described Two directions intersect with the first direction.

5. III-nitride transistor epitaxial structure according to claim 4, which is characterized in that the groove structure quilt It is triangle, quadrangle or semicircle perpendicular to the section that the face of the first direction intercepts.

6. III-nitride transistor epitaxial structure according to claim 4, which is characterized in that the groove structure Depth is 0.5-1 μm.

7. III-nitride transistor epitaxial structure according to claim 4, which is characterized in that the groove structure Width is 1-10 μm.

8. III-nitride transistor epitaxial structure according to claim 4, which is characterized in that the groove structure is thrown The 20%-80% of the plane gross area where the projected area of plane accounts for the substrate where shadow to the substrate.

9. a kind of III-nitride transistor device, which is characterized in that including III group of any of claims 1-8 Nitride transistor epitaxial structure.

10. III-nitride transistor device according to claim 9, which is characterized in that further include electrode；

The electrode is set to the barrier layer far from the channel layer side, and is located in the assembly section.

Technical field

Outside semiconductor material of the embodiment of the present invention and device fabrication arts more particularly to a kind of III-nitride transistor Prolong structure and transistor device.

Background technique

The group III-nitrides such as AlN, GaN, InN and its ternary quaternary compound are direct band gap compound semiconductor material Material, they have the characteristics that broad stopband, high breakdown electric field and thermal conductivity, high electron mobility rate and resistant to chemical etching, can be complete Demand of the full up foot market to high-voltage converter part.

Currently, GaN base HEMT (High Electron Mobility Transistor, high electron mobility transistor) Structure is mainly the face the c polar material that epitaxial growth obtains on c surface sapphire and (111) face Si substrate.It is along the direction of growth On there are strong piezoelectricity and spontaneous polarization, the very big polarization bound charge of concentration is formed at heterojunction boundary, to energy Band structure generates modulating action, to form the two-dimensional electron gas of high concentration and high mobility.But also it is exactly this polarization effect It answers, so that its two-dimensional electron gas is difficult to control and exhausts, most of GaN of polar surface be used to make depletion type HEMT.In order to Enhanced GaN base HEMT is obtained, introduces in special doping (such as C doping) or technical process and passes through during the growth process The designs such as fluorine ion injection, grid slot, p-type grid carry out adjusting threshold voltage.But the obtained enhanced HEMT device of these methods Threshold voltage is usually lower, and processing step is complicated, and reliability is not suitable for extensive production and application still wait improve.

Summary of the invention

The present invention provides a kind of III-nitride transistor epitaxial structure and transistor device, the group III-nitride crystal Pipe epitaxial structure helps to realize the enhanced HEMT device for preparing high electron mobility, low cross electric leakage.

In a first aspect, the embodiment of the invention provides a kind of III-nitride transistor epitaxial structure, the epitaxial structure packet Include substrate and the successively nucleating layer of lamination over the substrate, buffer layer, channel layer and barrier layer；The substrate includes multiple Groove structure and the growth window between the groove structure；The nucleating layer is located at the growth window of the substrate Mouthful；The buffer layer includes the direction that the groove structure adjacent thereto is directed toward along the growth window for being formed in assembly section III group-III nitride of semi-polarity of epitaxial growth and the edge for being formed in window region the direction extension vertical with plane where the substrate III group-III nitride of the semi-polarity of growth；The channel layer and the barrier layer are III group-III nitride of semi-polarity, the conjunction And area and the window region each extend to the channel layer and the barrier layer.

Optionally, the nucleating layer include it is multiple be scattered in the substrate surface at nuclear island；Positioned at the closest life The direction of growth at nuclear island of long window and the groove structure boundary line and the angle of plane where the substrate are greater than 0 °, and less than 90 °.

Optionally, the material at nuclear island is GaN or AlN.

Optionally, the groove structure is bar shaped；Multiple groove structures extend in a first direction, and arrange in a second direction Column；The first direction is parallel with plane where the substrate with the second direction；III group-III nitride of semi-polarity is Hexagonal wurtzite structure, the first direction are that III group-III nitride of the semi-polarity of the assembly section projects to hexagonal wurtzite The direction a when structure (0001) face, the second direction are intersected with the first direction.

Optionally, the section that the groove structure is intercepted by the face perpendicular to the first direction is triangle, four Side shape or semicircle.

Optionally, the depth of the groove structure is 0.5-1 μm.

Optionally, the width of the groove structure is 1-10 μm.

Optionally, the projected area of plane accounts for plane where the substrate where the groove structure projects to the substrate Area 20%-80%.

Second aspect, the embodiment of the present application provide a kind of III-nitride transistor device, and the group III-nitride is brilliant Body tube device includes any one III-nitride transistor epitaxial structure that claim first aspect provides.

Optionally, the III-nitride transistor device further includes electrode；It is remote that the electrode is set to the barrier layer From the channel layer side, and it is located in the assembly section.

III-nitride transistor epitaxial structure provided by the embodiments of the present application, by the way that groove structure is arranged on substrate And growth window, nucleating layer are located at the growth window of substrate, so that the nucleating layer of groove structure and growth window handover region The groove structure that the direction of growth is directed towards by growth window, the nucleating layer direction of growth vertical substrates in other regions of growth window The plane at place；III group-III nitride of semi-polarity is epitaxially-formed buffering along the direction for the groove structure that growth window is directed towards The assembly section of layer, III group-III nitride of semi-polarity are epitaxially-formed the window of buffer layer along the direction vertical with the plane where substrate Mouth region；The channel layer and barrier layer of III group-III nitride of semi-polarity are set on buffer layer, and window region and assembly section extend to channel layer And barrier layer.Since III group-III nitride of semi-polarity is weaker along the polarized electric field of its direction of growth, two-dimensional electron gas is easy to exhaust, easily In preparing enhanced HEMT device；The a large amount of dislocation of window area edge generates bending, mutually buries in oblivion, in the half-shadow that assembly section is formed Property III group-III nitride have low-dislocation-density, the crystal quality and surface topography of transistor arrangement are remarkably improved, along electronics Mobility obtains low-dislocation-density on higher direction；In addition, III group-III nitride of semi-polarity that window region is formed is with higher Stacking fault can effectively inhibit electronics in the lateral leakage phenomenon of buffer layer, and therefore, which helps to realize preparation The enhanced HEMT device that high electron mobility, low cross leak electricity.

Detailed description of the invention

Fig. 1 is a kind of structural schematic diagram of III-nitride transistor epitaxial structure provided in an embodiment of the present invention；

Fig. 2 is a kind of structure of the groove structure of III-nitride transistor epitaxial structure provided in an embodiment of the present invention Schematic diagram；

The structure of the groove structure of Fig. 3 another III-nitride transistor epitaxial structure provided in an embodiment of the present invention Schematic diagram；

Fig. 4 is a kind of structural schematic diagram of III-nitride transistor device provided in an embodiment of the present invention；

Fig. 5 is a kind of process signal of the manufacturing method of III-nitride transistor device provided in an embodiment of the present invention Figure.

Specific embodiment

The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched State that the specific embodiments are only for explaining the present invention, rather than limitation of the invention.It also should be noted that for the ease of It describes, only the parts related to the present invention are shown rather than entire infrastructure in attached drawing.

Fig. 1 is a kind of structural schematic diagram of III-nitride transistor epitaxial structure provided in an embodiment of the present invention.Such as figure Shown in 1, the nucleating layer of lamination over the substrate including substrate 110 and successively of III-nitride transistor epitaxial structure 100 120, buffer layer 130, channel layer 140 and barrier layer 150；Substrate 110 is including multiple groove structures 111 and is located at groove structure Growth window 112 between 111；Nucleating layer 120 is located at the growth window 112 of substrate 110；Buffer layer 130 includes being formed in conjunction And III race of the semi-polarity nitridation of the direction epitaxial growth that groove structure 111 adjacent thereto is directed toward along growth window 112 in area 131 Object and III group-III nitride of semi-polarity along the direction epitaxial growth vertical with 110 place plane of substrate for being formed in window region 132； Channel layer 140 and barrier layer 150 are III group-III nitride of semi-polarity, and assembly section 131 and window region 132 each extend to channel layer 140 and the barrier layer 150.

Specifically, providing a substrate 110, one layer of positive photoresist is coated on substrate 110, using mask plate to photoresist It is exposed, develops and post bake, form the figure of groove structure 111 on a photoresist, then by etching technics by groove knot The pattern transfer of structure 111 has obtained the substrate 110 of fluted structure 111 to substrate 110, between two adjacent grooves structures 111 Region be growth window 112.The impurity for removing 110 surface of substrate, forms nucleating layer in the growth window 112 of substrate 110 120, the nucleating layer 120 for being formed in growth window 112 and 111 intersection of groove structure continues in growth course on triggering, gradually It is directed parallel to 110 place plane cross growth of substrate while far from 110 place plane longitudinal growth of substrate, produces dislocation line Raw bending.Direction of growth epitaxial growth of III group-III nitride of semi-polarity along buffer layer 130；Wherein, growth window 112 and groove knot Substrate is directed parallel to while III group-III nitride of semi-polarity of 111 intersection of structure is far from 110 place plane longitudinal growth of substrate 110 place plane cross growths, dislocation line generate bending (curved dotted line in Fig. 1) and form assembly section 131, and assembly section 131 is horizontal The partial dislocation defect that the partial dislocation defect generated to growth and longitudinal growth generate is cancelled out each other, and defect concentration is lower；It is raw III group-III nitride of semi-polarity in long 112 other regions of window is far from 110 place plane longitudinal growth of substrate, dislocation line vertical substrates 110 place planes (longitudinal dotted lines of vertical substrates in Fig. 1) form window region 132, and window region 132 has the stacking of higher density Fault.Continued growth semi-polarity channel layer 140 and semi-polarity barrier layer 150 on buffer layer 130, assembly section 131 and window region 132 vertical substrates, 110 place plane extends to channel layer 140 and barrier layer 150, and the defect of the assembly section 131 of channel layer 140 is close Low, electron mobility with higher is spent, the stacking fault with higher of window region 132 of channel layer 140 is formed electric from growing Sub- barrier layer.

The embodiment of the present application also can be used other modes and form groove structure, and the application is to groove structure, nucleating layer, channel The generation type of layer and barrier layer does not limit.

A kind of III-nitride transistor epitaxial structure provided by the embodiments of the present application, by the way that groove is arranged on substrate Structure and growth window, nucleating layer is located at the growth window of substrate, so that the nucleation of groove structure and growth window handover region The groove structure that the direction of growth of layer is directed towards by growth window, the nucleating layer direction of growth in other regions of growth window are vertical Plane where substrate；III group-III nitride of semi-polarity is epitaxially-formed along the direction for the groove structure that growth window is directed towards The assembly section of buffer layer, III group-III nitride of semi-polarity are epitaxially-formed buffer layer along the direction vertical with the plane where substrate Window region；The channel layer and barrier layer of III group-III nitride of semi-polarity are set on buffer layer, and window region and assembly section extend to ditch Channel layer and barrier layer.Since III group-III nitride of semi-polarity is weaker along the polarized electric field of its direction of growth, two-dimensional electron gas is easy consumption To the greatest extent, easily prepared enhanced HEMT device；There is low-dislocation-density in III group-III nitride of semi-polarity that assembly section is formed, it can be significant The crystal quality and surface topography for improving transistor arrangement, are obtaining low-dislocation-density along the higher direction of electron mobility； In addition, III group-III nitride of the semi-polarity stacking fault with higher that window region is formed, effectively can inhibit electronics in buffer layer Lateral leakage phenomenon, therefore, which, which helps to realize, prepares high electron mobility, low The enhanced HEMT device laterally leaked electricity.

Optionally, with continued reference to Fig. 1, substrate 110 is the foreign substrate of buffer layer 130, such as: m surface sapphire, the face m SiC Or the face (11h) single crystalline Si.

Optionally, with continued reference to Fig. 1, substrate 110 is the homo-substrate of buffer layer 130, such as: semi-polarity gallium nitride, half The semi-polarities group III-nitride such as polarity aluminium nitride.

Optionally, with continued reference to Fig. 1, nucleating layer 120 include it is multiple be scattered in 110 surface of substrate at nuclear island 121；It is located at The direction of growth and 110 place plane of substrate at nuclear island 121 of 111 boundary line of closest growth window 112 and groove structure Angle is greater than 0 °, and less than 90 °.

Substrate 110 is being gradually distance from nuclear island 121 due to 111 boundary line of closest growth window 112 and groove structure 110 place plane cross growth of substrate is directed parallel to while the plane longitudinal growth of place, so that its direction of growth was both uneven Row is also not orthogonal to 110 place plane of substrate in 110 place plane of substrate.

Optionally, with continued reference to Fig. 1, the material at nuclear island 121 is GaN or AlN.

Optionally, individually at the size of nuclear island 121 be 0.01-0.5 μm.

Fig. 2 is a kind of vertical view of the groove structure of III-nitride transistor epitaxial structure provided in an embodiment of the present invention Schematic diagram.Illustratively, as shown in Fig. 2, groove structure 111 is bar shaped；Multiple groove structures 111 extend in a first direction, edge Second direction arrangement；First direction is parallel with plane where substrate with second direction；III race's nitrogen of semi-polarity in above-described embodiment Compound is hexagonal wurtzite structure, and first direction is that III group-III nitride of semi-polarity of assembly section projects to hexagonal wurtzite structure (0001) direction a when face, second direction are intersected with first direction.

Fig. 3 is bowing for the groove structure of another III-nitride transistor epitaxial structure provided in an embodiment of the present invention Depending on schematic diagram.As shown in figure 3, groove structure 111 can also be along first direction continuously extends to substrate boundary, i.e., along first party To, only one groove structure 111, and its along first direction length and substrate along first direction equal length.

The application to groove mechanism 111 along first direction quantity with no restrictions.Groove structure is periodical in a second direction The plane of arrangement, first direction and second direction composition is parallel with plane where substrate, and first direction and second direction are uneven Row.

Optionally, the section intercepted with continued reference to Fig. 2 or Fig. 3, groove structure 111 by the face perpendicular to first direction For triangle, quadrangle or semicircle.

The shape for the cross-sectional image that the application is intercepted groove structure by the face perpendicular to first direction is with no restrictions.

Optionally, referring to Fig. 1, the depth of groove structure 111 is 0.5-1 μm.

Optionally, referring to figs. 2 and 3, the width of groove structure 111 is 1-10 μm.

Optionally, with continued reference to Fig. 2 and Fig. 3, the projected area of plane accounts for described where groove structure 111 projects to substrate The 20%-80% of the area of plane where substrate.

Optionally, referring to Fig. 1, buffer layer 130, channel layer 140 and barrier layer 150 are in semi-polarity GaN, AlN, InN Film, content gradually variational layer or the superlattice structure of at least one composition.

Optionally, with continued reference to Fig. 1, buffer layer 130 with a thickness of 0.8-5 μm, channel layer 140 with a thickness of 200- 800nm, barrier layer 150 with a thickness of 5-50nm.

Based on the same inventive concept, the present embodiment provides a kind of III-nitride transistor device, including it is mentioned-above Any one III-nitride transistor epitaxial structure.

Optionally, Fig. 4 is a kind of structural schematic diagram of III-nitride transistor device provided in an embodiment of the present invention. Referring to fig. 4, III-nitride transistor device 400 includes: transmistor epitaxial structure 100 and electrode 410；Electrode 410 is set to Barrier layer 150 is located in assembly section 131 far from 110 side of channel layer.

Specifically, electron beam evaporation plating, magnetron sputtering, physics gas can be used after the completion of transmistor epitaxial structure 100 is grown Mutually the process means such as deposition, chemical vapor deposition, dry etching are arranged in barrier layer 150 away from the assembly section 132 of 110 side of substrate Electrode 410 and passivation layer carry out device isolation in window region 131, can get HEMT device array, while carrying out device in the region The utilization rate for being able to ascend wafer is isolated in part.

A kind of III-nitride transistor device provided by the embodiments of the present application, III group-III nitride of semi-polarity are easily prepared Enhanced HEMT device；There is low-dislocation-density in III group-III nitride of semi-polarity that assembly section is formed, be remarkably improved transistor The crystal quality and surface topography of structure are obtaining low-dislocation-density along the higher direction of electron mobility；Window region is formed III group-III nitride of semi-polarity stacking fault with higher, can effectively inhibit electronics in the lateral leakage phenomenon of buffer layer, Reduce isolation sector width.Therefore, which is the increasing of a kind of high electron mobility, low cross electric leakage Strong type HEMT device；Additionally it is able to ascend the utilization rate of wafer.

Based on the same inventive concept, the present embodiment provides a kind of manufacturing method of III-nitride transistor device, Fig. 5 It is a kind of manufacturing method of III-nitride transistor device provided in an embodiment of the present invention, as shown in figure 5, group III-nitride The manufacturing method of transistor device includes:

510, one 2 inches of m surface sapphire substrates are provided and have periodic rectangular array (rectangle is 3 inches long, 10 μm wide, 6 μm of interval) mask plate, coating a layer thickness on substrate is 1 μm of positive photoresist, using mask plate to the photoresist It is exposed, develops and post bake, form the figure of cuboid grizzly bar array on a photoresist；Then using the etching such as RIE or ICP Technique in pattern transfer to substrate, will obtain graphical m surface sapphire substrate；

520, graphical m surface sapphire substrate 101 is put into the anti-of Metal Organic Vapor extension (MOCVD) equipment It answers on indoor pallet, is purged and toasted under 1100 DEG C, H2 atmosphere, remove surface impurity, then switch to NH₃Atmosphere Carry out nitrogen treatment；

530, reaction chamber is cooled to 600 DEG C, is passed through NH₃And trimethyl aluminium, island AlN nucleating layer is generated in substrate surface, Its thickness is about 40nm；

540, reaction chamber is warming up to 1200 DEG C, and island AlN nucleating layer is from growth window along the direction a of m surface sapphire substrate Laterally overgrown is carried out, semi-polarity is obtainedFace Al_0.45Ga_0.55N buffer layer, thickness are about 2 μm；

550, in semi-polarityFace Al_0.45Ga_0.55Continued growth semi-polarity on N buffer layer 103Face GaN Channel layer and semi-polarityFace Al_0.2Ga_0.8N barrier layer, thickness are respectively 300nm and 15nm, constitute semi-polarity GaN/ AlGaN hetero-junctions, two-dimensional electron gas surface density are 10¹²cm^-2Magnitude；

560, using techniques such as electron beam evaporation plating, magnetron sputtering, physical vapour deposition (PVD), chemical vapor deposition, dry etchings Means are in semi-polarityFace Al_0.2Ga_0.8N barrier layer carries out electrode and passivation layer preparation away from the assembly section of one side of substrate, Device isolation is carried out in window region.

The manufacturing method of III-nitride transistor device provided in an embodiment of the present invention is suitable for mentioned-above any A kind of III-nitride transistor device, the III-nitride transistor device that there is it to be applicable in is identical or has accordingly Beneficial effect, details are not described herein again.

Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation, It readjusts, be combined with each other and substitutes without departing from protection scope of the present invention.Therefore, although by above embodiments to this Invention is described in further detail, but the present invention is not limited to the above embodiments only, is not departing from present inventive concept In the case of, it can also include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.