阅读说明：本技术 一种高效的eeprom芯片自测试方法 (A kind of efficient eeprom chip self-test method ) 是由 孙晓霞 张建伟 于 2019-09-12 设计创作，主要内容包括：本发明提出一种高效的EEPROM芯片自测试方法。上位机只需发送一次命令请求,数字逻辑电路按照需求,自主发送写和读请求至EEPROM,上位机等待一定时间后,如果收到正确的返回数据,则认为此EEPROM测试完成。该发明解决生产测试耗时长、命令复杂等问题。(The present invention proposes a kind of efficient eeprom chip self-test method.Host computer need to only send a command request, and Digital Logical Circuits as desired, request to EEPROM, and host computer waits after a certain period of time, if receiving correct returned data, then it is assumed that this EEPROM test is completed by the autonomous write and read that sends.The invention solves production test, and time-consuming, orders the problems such as complicated.)

1. a kind of efficient eeprom chip self-test method, which is characterized in that host computer need to only send a command request, number Word logic circuit as desired, request to EEPROM, and host computer waits after a certain period of time, if received just by the autonomous write and read that sends True returned data, then it is assumed that this EEPROM test is completed.

2. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, host computer is only sent Primary simple order instruction.It is automatic to send write and read EEPROM request after Digital Logical Circuits parses this order.Instead of biography It unites cumbersome read-write sequence.

3. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, digital circuit with The interface of EEPROM is parallel data processing.

4. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, EEPROM interface is adopted Read-write clock is generally larger than IIC serial clock.

5. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, host computer sends life After order, Digital Logical Circuits need not return to the data read from EEPROM.4 flag bits only need to be returned to host computer, tell and work as Preceding detection is completed.

6. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, digital circuit is known The amount of storage of corresponding EEPROM, can do complete test to chip.

7. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, host computer order is opened Hair process is largely simplified, and reduces error probability.

8. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, it is waited in host computer It, can be simultaneously to other chip operations in the process of chip Returning mark position.

9. a kind of efficient eeprom chip self-test method as described in claim 1, it is characterised in that, EEPROM self-test The reduction of the various expenses of mode bring is obvious.Although this scheme can slightly increase some Digital Logic resources, It is to get off with valuable time cost trade-offs, such scheme can more highlight its practical value.

Technical field

The invention belongs to design of integrated circuit fields, specifically belong to erasable programmable memory (EEPROM) neck Domain.

Background technique

In general, several chips are had on a piece of IC wafers.After wafer production comes out, it should allow first Every chips enter test pattern, to carry out production test to chip, after production test passes through, then carry out scribing to wafer, It will take and encapsulate by the chip of production test.

Traditional eeprom chip is in the production test stage, since core number is huge on wafer, it is therefore desirable to expend big The time of amount goes to detect and exclude.Traditional test is referring to attached drawing 1: host computer sends bus format and mostly uses IIC/SPI greatly, this kind of Bus majority is serial data format, Digital Logical Circuits by serial bus format be converted into reading specified by EEPROM/ The timing of parallel form is write, and does corresponding operating.As shown in attached drawing 1, host computer needs to send a plurality of read/write command to EEPROM Chip, ability coverage test are complete.By taking iic bus common in attached drawing 2 and attached drawing 3 as an example, working frequency 200KHz sends one Write order occupies 29 clock cycle, elapsed time about 145ns；It sends a read command and occupies 38 clock cycle, consumption Time about 190ns.Operation duplicate in this way consumes great time cost.This batch testing, in order to save EEPROM's Testing time is usually only written and read first address, tests full sheet read-write, erasing operation, will not specially carry out core The inquiry and judgement of piece memory capacity, because doing consumption more testing times like that.

Summary of the invention

In order to solve the problem above-mentioned, the present invention proposes a kind of efficient EEPROM self-test method.Referring to attached drawing 4: this In invention, host computer need to only send a command request, Digital Logical Circuits as desired, it is autonomous send write and read request to EEPROM, host computer wait after a certain period of time, if receiving correct returned data, then it is assumed that this EEPROM test is completed.This In a scheme, there are several advantages:

1. host computer only sends primary simple order instruction.After Digital Logical Circuits parses this order, automatic send is write It is requested with EEPROM is read.Instead of the cumbersome read-write sequence of tradition.

2. the interface of digital circuit and EEPROM are parallel data processing.

The read-write clock that 3.EEPROM interface uses is generally larger than IIC serial clock.

4. after host computer sends order, Digital Logical Circuits need not return to the data read from EEPROM.4 need to only be returned Flag bit tells current detection to be completed to host computer.

5. digital circuit knows the amount of storage of corresponding EEPROM, complete test can be done to chip.

6. host computer command development process is largely simplified, error probability is reduced.

7., can be simultaneously to other chip operations in the process that host computer waits chip Returning mark position.

It can be seen that the reduction of the various expenses of EEPROM self test mode bring in the present invention is obvious. Although this scheme can slightly increase some Digital Logic resources, get off with valuable time cost trade-offs, such scheme is more Its practical value can be highlighted.

Detailed description of the invention

Fig. 1 is example tradition EERPOM readwrite tests mode of the present invention.

Fig. 2 is Example II C typical case write order timing of the present invention.

Fig. 3 is Example II C typical read command timing of the present invention.

Fig. 4 is a kind of efficient EEPROM readwrite tests mode system block diagram that example of the present invention proposes.

Fig. 5 is a kind of self-test command format that example of the present invention proposes

Specific embodiment

Below according to attached drawing 5, the typical realisation of this test is illustrated.In attached drawing 5, host computer sends in order and wraps Containing 8 bits commands, 8 bit self-defining data values, 2 bit parities；It only includes 4 bit flags that eeprom chip, which replys format, Data.In the whole series order, instruction value, data value, reply mark can be according to the realization definite values of Digital Logic, without spy It does not provide.In the order, making data value by oneself is for defining the data erasable to EEPROM, such as complete " 0 ", complete " 1 ", 8 ' h55 Or any other numerical value.Parity check bit does even parity check to instruction and user's self-defining data respectively, for ensuring to send The accuracy of order and data can be used as option to the function.

It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, is read in those skilled in the art After having read above content, a variety of modifications and substitutions of the invention all will be apparent.Above description and attached drawing is only It is only to implement example of the invention, but it should be appreciated that the description above is not considered as limitation of the present invention.