阅读说明：本技术 一种半导体器件及其制造方法 (A kind of semiconductor devices and its manufacturing method ) 是由 乔明 孟培培 张波 于 2019-09-06 设计创作，主要内容包括：本发明涉及一种半导体器件及其制造方法,属于功率半导体技术领域。所述的半导体器件由多个结构相同的元胞以叉指方式连接形成,所述的元胞结构包括第二导电类型衬底、第一导电类型轻掺杂外延层、扩散第二导电类型阱区、绝缘介质槽、第一导电类型耗尽型沟道区、具有第一导电类型的第一、第三重掺杂区,具有第二导电类型的第二重掺杂区、氧化介质层、金属阴极和金属阳极。本发明通过引入绝缘介质槽,不仅提升器件击穿电压,并且在槽底部与衬底之间形成新的横向沟道,起到优化恒流特性,提升动态阻抗的功能,可极大增强输出电流的稳定性。通过仿真得到器件耐压值为300V时,夹断电压在3.5V以下,动态阻抗可达200MΩ,具有非常好的恒流特性。(The present invention relates to a kind of semiconductor devices and its manufacturing methods, belong to power semiconductor technologies field.The semiconductor devices is connected with interdigited fashion by the identical cellular of multiple structures and is formed, the structure cell includes the second conductivity type substrate, the first conduction type lightly doped epitaxial layer, diffusion the second conduction type well region, dielectric slot, the first conduction type deplection type channel area, first with the first conduction type, third heavily doped region, the second heavily doped region, oxide isolation layer, metallic cathode and metal anode with the second conduction type.The present invention not only promotes device electric breakdown strength, and form new lateral channel between trench bottom and substrate, plays optimization constant-current characteristics, promote the function of motional impedance, can greatly enhance the stability of output electric current by introducing dielectric slot.When by emulation, to obtain device pressure voltage be 300V, pinch-off voltage, hereinafter, motional impedance is up to 200M Ω, has extraordinary constant-current characteristics in 3.5V.)

1. a kind of semiconductor devices, is connected with interdigited fashion by the identical cellular of multiple structures and formed, the structure cell includes Second conductivity type substrate (2), the first conduction type lightly doped epitaxial layer (3), oxide isolation layer (10), metallic cathode (11) and Metal anode (12)；There is the second conduction type well region (4) of diffusion, first to lead in first conduction type lightly doped epitaxial layer (3) Electric type deplection type channel area (6), the first heavily doped region (7), the second heavily doped region (8) and third heavily doped region (9), the first weight Doped region (7) and third heavily doped region (9) are the first conduction type, and the second heavily doped region (8) is the second conduction type；

The first conduction type lightly doped epitaxial layer (3) is located above the second conductivity type substrate (2), spreads the second conductive-type Type well region (4) is arranged in the first conduction type lightly doped epitaxial layer (3), and the first conduction type deplection type channel area (6) is located at The upper layer of first conduction type lightly doped epitaxial layer (3), the second heavily doped region (8) and the first heavily doped region (7) are located side by side at expansion Dissipate the section top of the second conduction type well region (4)；Third heavily doped region (9) is located at first conduction type and extension is lightly doped The upper layer side of layer (3)；

Oxide isolation floor (10) is located at the first part and the first conduction type deplection type channel area (6) of the first heavily doped region (7) On；Metallic cathode (11) is located at the second part of the first heavily doped region (7), the first part of the second heavily doped region (8) and oxidation On dielectric layer (10)；Metal anode (12) is located in the first part of third heavily doped region (9)；First heavily doped region (7) It is shorted with the second heavily doped region (8), and forms Ohmic contact, the third heavily doped region (9) and metal with metallic cathode (11) Anode (12) forms Ohmic contact；

It is characterized in that, being arranged between the second conduction type well region (4) and the two the first conduction type heavily doped regions (9) spreading Dielectric slot (5)；Oxide isolation layer (10) is also located at the second part of the second heavily doped region (8), third heavily doped region (9) On second part and dielectric slot (5).

2. a kind of semiconductor devices according to claim 1, which is characterized in that metallic cathode (11) and metal anode (12) Field plate structure is extended to form along the surface of oxide isolation layer (10).

3. a kind of semiconductor devices according to claim 1, which is characterized in that further include that the second conduction type of groove sidewall is mixed Miscellaneous area (13), groove sidewall the second conduction type doped region (13) are located at the second conduction type well region of dielectric slot (5) and diffusion (4) it between, and is contacted with the second conduction type well region (4) of diffusion and the first conduction type lightly doped epitaxial layer (3).

4. a kind of semiconductor devices according to claim 1, which is characterized in that further include buries oxide layer (15), bury oxidation Layer (15) is located between the second conductivity type substrate (2) and the first conduction type lightly doped epitaxial layer (3), and by the third weight The doping type of doped region (9) replaces with the second conduction type, forms the 4th heavily doped region (14).

5. a kind of semiconductor devices according to claim 3, which is characterized in that further include buries oxide layer (15), bury oxidation Layer (15) is located between the second conductivity type substrate (2) and the first conduction type lightly doped epitaxial layer (3), and by the third weight The doping of doped region (9) replaces with the second conduction type and is lightly doped, and forms the second conduction type lightly doped district.

6. a kind of semiconductor devices according to claim 1, which is characterized in that the filling material of the dielectric slot (5) Material is the mixture of silica, silicon nitride or silica and polysilicon.

7. a kind of semiconductor devices according to claim 1, which is characterized in that material used by the semiconductor devices For silicon or silicon carbide.

8. a kind of semiconductor devices according to claim 1, which is characterized in that first conduction type is N-type, described Second conduction type is p-type；Or first conduction type is p-type, second conduction type is N-type.

9. a kind of manufacturing method of semiconductor devices, which comprises the following steps:

The second conduction type silicon wafer is selected to be formed over the substrate as the second conductivity type substrate (2) using epitaxy technique First conduction type lightly doped epitaxial layer (3)；

The second conduction type well region (4) is spread in the formation being spaced in the first conduction type lightly doped epitaxial layer (3)；

Media slot is formed in the two sides for diffusion the second conduction type well region (4) that interval is formed, fills institute using insulating medium layer It gives an account of matter slot and forms dielectric slot (5)；

Using ion implantation technology, ion implanting is carried out on entire first conduction type lightly doped epitaxial layer (3) surface, forms the One conduction type deplection type channel area (6)；

On the upper layer two for the section top and the first conduction type lightly doped epitaxial layer (3) for spreading the second conduction type well region (4) End forms the first heavily doped region (7) and third heavily doped region (9)；

In the upper layer for spreading the second conduction type well region (4), the side of the first heavily doped region (7) forms the second heavily doped region (8)；

Oxide isolation layer (10) are formed in the first conduction type lightly doped epitaxial layer (3)；Photoetching simultaneously etches the oxide isolation Layer (10) forms ohm hole, deposits aluminum metal and anti-carves, forms metallic cathode (11) and metal anode (12)；

Passivation layer is deposited on oxide isolation layer (10), metallic cathode (11) and metal anode (12), etches the hole PAD；

Back note metal, forms back metal electrode below substrate.

10. the manufacturing method of semiconductor devices according to claim 9, which is characterized in that pass through multiple ion implanting shape At the second conduction type well region (4) of diffusion, wherein the energy and dosage of rear primary ions injection are lower than the injection of preceding primary ions Energy and dosage.

Technical field

The invention belongs to power semiconductor device technology fields, and in particular to a kind of semiconductor devices and its manufacturing method.

Background technique

Constant-current source is a kind of common electronic equipment and device, using fairly common in electronic circuit.Constant-current source is usual For protecting entire circuit, even if occurring spread of voltage in circuit or the case where load resistor value changes greatly, remain to protect Demonstrate,prove the stabilization of entire circuit supply current.Current regulator diode (CRD, Constant Regulating Diode) is a kind of common Semiconductor constant current device replaces common by multiple electronics such as transistor, voltage-stabiliser tube and resistance using diode as constant-current source The constant-current source of element composition realizes that circuit structure is simplified and minimized.Common current regulator diode output electric current is in several millis at present Pacify between tens milliamperes, can be used for directly driving load, due to having the characteristics that device volume is small, device reliability is high, make It has great advantage compared to conventional constant current source.In addition the peripheral circuit of current regulator diode is simple, easy to use, has been widely used In fields such as automatic control, instrument and meter and protection circuits.At present the forward break down voltage of current regulator diode be generally located at 30~ In the section 100V, there is a problem of that breakdown voltage is lower, while the constant current value that can be provided is also relatively low, and to guarantee compared with Gao Heng Flow valuve is necessarily required to biggish chip area, and then brings the promotion in cost.

Summary of the invention

The technical problem to be solved by the present invention is in view of the problems of the existing technology, provide a kind of semiconductor devices and Its manufacturing method.

In order to solve the above technical problems, the embodiment of the present invention provides a kind of semiconductor devices, by the identical member of multiple structures Born of the same parents connect to be formed with interdigited fashion, and extension is lightly doped including the second conductivity type substrate, the first conduction type in the structure cell Layer, oxide isolation layer, metallic cathode and metal anode；There is the second conductive-type of diffusion in first conduction type lightly doped epitaxial layer Type well region, the first conduction type deplection type channel area, the first heavily doped region, the second heavily doped region and third heavily doped region, first Heavily doped region and third heavily doped region are the first conduction type, and the second heavily doped region is the second conduction type；

The first conduction type lightly doped epitaxial layer is located above the second conductivity type substrate, spreads the second conduction type Well region is arranged in the first conduction type lightly doped epitaxial layer, and the first conduction type deplection type channel area is located at the first conduction type The upper layer of lightly doped epitaxial layer, the first heavily doped region and the second heavily doped region are located side by side at the portion of the second conduction type well region of diffusion Divide upper layer；Third heavily doped region is located at the upper layer side of the first conduction type lightly doped epitaxial layer；

Oxide isolation floor is located in the first part and the first conduction type deplection type channel area of the first heavily doped region；Metal Cathode is located in the first part and oxide isolation layer of the second part of the first heavily doped region, the second heavily doped region；Metal anode In the first part of third heavily doped region；First heavily doped region and the second heavily doped region are shorted, and and metallic cathode Ohmic contact is formed, the third heavily doped region and metal anode form Ohmic contact；

Spreading, dielectric slot is set between the second conduction type well region and the two the first conduction type heavily doped regions；Oxygen Change dielectric layer to be also located on the second part of the second heavily doped region, the second part of third heavily doped region and dielectric slot.

The beneficial effects of the present invention are: semiconductor devices of the invention injects knot in the epitaxial layer forms well region, in trap Channel is formed among area surface and two well regions, the form of double channel improves device constant current effect and motional impedance value, in addition, In Laterally using the pressure resistance of dielectric slot, medium groove depth and epitaxy layer thickness are rationally set, then between medium trench bottom and substrate The function that lateral channel can play optimization constant-current characteristics, promote motional impedance is formed, device outputting current steadily is greatly enhanced, In addition, playing the role of extension current path using dielectric slot structure in device inside and being exhausted as anode voltage increases Layer is lasting to be extended and then compresses to current path, and device outputting current steadily can be enhanced；Medium slot structure realizes The purpose of more excellent constant-current characteristics and more high voltage is obtained on smaller chip area.

Based on the above technical solution, the present invention can also be improved as follows.

Further, metallic cathode and metal anode extend to form field plate structure along the surface of oxide isolation layer.

Beneficial effect using above-mentioned further scheme is: device being made to obtain more high voltage value.

It further, further include groove sidewall the second conduction type doped region, groove sidewall the second conduction type doped region is located at Between the second conduction type well region of dielectric slot and diffusion, and it is light with the second conduction type well region of diffusion and the first conduction type The contact of doped epitaxial layer.

Beneficial effect using above-mentioned further scheme is: amplified medium trench bottom corner and JFET channel region exhaust effect Fruit not only reduces media slot corner peak electric field, promotes device pressure voltage, and improve device constant-current characteristics, increases device Motional impedance.

It further, further include buries oxide layer, buries oxide layer is located at the second conductivity type substrate and the first conduction type is light Between doped epitaxial layer, and the doping type of the third heavily doped region is replaced with into the second conduction type, it is heavily doped to form the 4th Miscellaneous area.

Beneficial effect using above-mentioned further scheme is: device anode is adulterated using the second conduction type, ambipolar to lead Power mode can increase constant current value；Longitudinal parasitic-PNP transistor electric leakage is isolated using buries oxide layer in side on substrate, can avoid bringing The excessive deterioration of device constant-current characteristics.

It further, further include buries oxide layer, buries oxide layer is located at the second conductivity type substrate and the first conduction type is light Between doped epitaxial layer, and the doping of the third heavily doped region is replaced with into the second conduction type and is lightly doped, formed second and lead Electric type lightly doped district.

Beneficial effect using above-mentioned further scheme is: it is to post in order to prevent that anode is lightly doped using the second conduction type Raw PNP transistor reduces hole current ratio by groove sidewall the second conduction type doped region premature breakdown, guarantees device Part constant-current characteristics.

Further, the packing material of the dielectric slot is silica, silicon nitride or silica and polysilicon Mixture.

Further, material used by the semiconductor devices is silicon or silicon carbide.

Further, first conduction type is N-type, and second conduction type is p-type；Or first conduction Type is p-type, and second conduction type is N-type.

In order to solve the above technical problems, the embodiment of the present invention also provides a kind of manufacturing method of semiconductor devices, including with Lower step:

Select the second conduction type silicon wafer as the second conductivity type substrate, using epitaxy technique, shape over the substrate At the first conduction type lightly doped epitaxial layer；

The second conduction type well region is spread in the formation being spaced in the first conduction type lightly doped epitaxial layer；

Media slot is formed in the two sides for diffusion the second conduction type well region that interval is formed, fills institute using insulating medium layer It gives an account of matter slot and forms dielectric slot；

Using ion implantation technology, ion implanting is carried out on entire first conduction type lightly doped epitaxial layer surface, is formed First conduction type deplection type channel area；

At the upper layer both ends for the section top and the first conduction type lightly doped epitaxial layer for spreading the second conduction type well region Form the first heavily doped region and third heavily doped region；

In the upper layer for spreading the second conduction type well region, the side of the first heavily doped region forms the second heavily doped region；

Oxide isolation layer is formed in the first conduction type lightly doped epitaxial layer；Photoetching simultaneously etches the oxide isolation layer shape At ohm hole, deposits aluminum metal and anti-carve, form metallic cathode and metal anode；

Passivation layer is deposited on oxide isolation layer, metallic cathode and metal anode, etches the hole PAD；

Back note metal, forms back metal electrode below substrate.

The beneficial effects of the present invention are: method, semi-conductor device manufacturing method of the invention injects knot in the epitaxial layer forms trap Area forms channel among well region surface and two well regions, and the form of double channel improves device constant current effect and motional impedance value, In addition, it is pressure-resistant using dielectric slot in transverse direction, medium groove depth and epitaxy layer thickness are rationally set, then medium trench bottom and lining The function that lateral channel can play optimization constant-current characteristics, promote motional impedance, greatly enhancing device output current are formed between bottom Stability, in addition, playing the role of extending current path in device inside, with anode voltage liter using dielectric slot structure Height, depletion layer are persistently extended and then are compressed to current path, can enhance device outputting current steadily；Medium slot structure is real The purpose that more excellent constant-current characteristics and more high voltage are obtained on smaller chip area is showed.

Based on the above technical solution, the present invention can also be improved as follows.

Further, the second conduction type well region of diffusion is formed by multiple ion implanting, wherein rear primary ions injection Energy and dosage be lower than preceding primary ions injection energy and dosage.

Beneficial effect using above-mentioned further scheme is: weakening surface channel and diffusion well region impurity compensation degree, drop Low surface depletion channel and JFET conducting channel transitional region width are easy to surface channel pinch off, reduce pinch-off voltage, lifter Part constant-current characteristics.

Detailed description of the invention

Fig. 1 (a)-Fig. 1 (d) is a kind of cross-section structure signal of semiconductor devices of first to fourth embodiment of the invention Figure；

Fig. 2 (a)-Fig. 2 (b) illustrates for a kind of structure cell of semiconductor devices of the present invention first to second embodiment Figure；

Fig. 3 is a kind of cellular process simulation schematic diagram of semiconductor devices of second embodiment of the invention；

Fig. 4 is a kind of current -voltage curve figure of semiconductor devices of second embodiment of the invention；

Fig. 5 is a kind of motional impedance-voltage curve of semiconductor devices of second embodiment of the invention；

Fig. 6 (a)-Fig. 6 (h) is that a kind of process flow of the manufacturing method of semiconductor devices of fifth embodiment of the invention is shown It is intended to；

Fig. 7 (a)-Fig. 7 (h) is that a kind of corresponding technique of manufacturing process of semiconductor devices of fifth embodiment of the invention is imitative True figure.

In attached drawing, parts list represented by the reference numerals are as follows:

1 (1), 1 (2) ... 1 (i) are structure cell, and i is positive integer, expression cellular number, the 2, second conductivity type substrate, 3, the first conduction type lightly doped epitaxial layer, 4, the second conduction type well region of diffusion, 5, dielectric slot, the 6, first conduction type Deplection type channel area, the 7, first heavily doped region, the 8, second heavily doped region, 9, third heavily doped region, 10, oxide isolation layer, 11, gold Belong to cathode, 12, metal anode, 13, groove sidewall the second conduction type doped region, the 14, the 4th heavily doped region, 15, buries oxide layer.

Specific embodiment

The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and It is non-to be used to limit the scope of the invention.

As shown in Fig. 1 (a), 2 (a), a kind of semiconductor devices that first embodiment of the invention provides is identical by multiple structures Cellular connect to be formed with interdigited fashion, the structure cell includes that the second conductivity type substrate 2, the first conduction type are lightly doped Epitaxial layer 3, oxide isolation layer 10, metallic cathode 11 and metal anode 12；Have in first conduction type lightly doped epitaxial layer 3 and expands Dissipate the second conduction type well region 4, the first conduction type deplection type channel area 6, the first heavily doped region 7, the second heavily doped region 8 and the Three heavily doped regions 9, the first heavily doped region 7 and third heavily doped region 9 are the first conduction type, and the second heavily doped region 8 is led for second Electric type；

The first conduction type lightly doped epitaxial layer 3 is located at 2 top of the second conductivity type substrate, spreads the second conductive-type Type well region 4 is arranged in the first conduction type lightly doped epitaxial layer 3, and the first conduction type deplection type channel area 6 is located at first and leads The upper layer of electric type lightly doped epitaxial layer 3, the first heavily doped region 7 and the second heavily doped region 8 are located side by side at the second conductive-type of diffusion The section top of type well region 4；Third heavily doped region 9 is located at the upper layer side of the first conduction type lightly doped epitaxial layer 3；

Oxide isolation floor 10 is located in the first part and the first conduction type deplection type channel area 6 of the first heavily doped region 7； Metallic cathode 11 is located at the second part of the first heavily doped region 7, the first part of the second heavily doped region 8 and oxide isolation layer 10 On；Metal anode 12 is located in the first part of third heavily doped region 9；First heavily doped region 7 and the second heavily doped region 8 are short It connects, and forms Ohmic contact with metallic cathode 11, the third heavily doped region 9 forms Ohmic contact with metal anode 12；

It is characterized in that, being arranged between the second conduction type well region 4 and the two the first conduction type heavily doped regions 9 spreading Dielectric slot 5；Oxide isolation layer 10 is also located at the second part of the second part of the second heavily doped region 8, third heavily doped region 9 On dielectric slot 5.

In above-described embodiment, semiconductor devices of the invention injects knot in the epitaxial layer and forms well region, on well region surface With deplection type channel and JFET channel are respectively formed among two well regions, the form of double channel improves device constant current effect and dynamic Impedance value.Laterally using the pressure resistance of dielectric slot, medium groove depth and epitaxial layer is rationally being arranged in semiconductor devices of the invention Thickness then forms the function that lateral channel can play optimization constant-current characteristics, promote motional impedance between medium trench bottom and substrate, Greatly enhancing device outputting current steadily, when emulation shows that device work is under 20V voltage conditions, every micron of dynamic resistance Anti- value is up to 200M Ω, has extremely excellent constant-current characteristics.Semiconductor devices of the invention uses dielectric slot structure, In Device inside play the role of extend current path, as anode voltage increases, depletion layer persistently extend in turn to current path into Row compression, can enhance device outputting current steadily；Medium slot structure is realized obtains more excellent constant current on smaller chip area The purpose of characteristic and more high voltage.

The number i of the cellular can be adjusted according to specific current capacity demand.Spread the second conduction type well region 4 Spacing can carry out appropriate adjustment, to guarantee surface the first conduction type deplection type channel area 6 prior to JFET channel region pinch off or two Person realizes pinch off simultaneously, obtains lower pinch-off voltage and more excellent constant current effect.

Below using the first conduction type as N-type, the second conduction type is p-type to introduce the working principle of the invention, at this point, The second conduction type well region 4 is spread for diffusion P type trap zone, and the first conduction type deplection type channel area 6 is N-type deplection type channel Area, the first heavily doped region 7 with the first conduction type are the first N-type heavily doped region, the second weight with the second conduction type Doped region 8 is the second p-type heavily doped region, and the third heavily doped region 9 with the first conduction type is third N-type heavily doped region, the One conduction type lightly doped epitaxial layer 3 is N-type lightly doped epitaxial layer.Working principle of the present invention is as follows:

The semiconductor devices is to be connected by multiple cellulars such as 1 (1), 1 (2) ... 1 (i) with interdigited fashion, cellular Number i can be adjusted according to specific current capacity demand.The present invention passes through in diffusion P type trap zone surface tune ditch injection Phosphonium ion makes surface compensate to form N-type deplection type channel area, then is implanted sequentially and to form the first N-type heavily doped region, the second p-type weight Doped region and third N-type heavily doped region.Dielectric slot is provided between diffusion P type trap zone and third N-type heavily doped region 5, lateral pressure resistance can be not only born, but also can play the role of extending current path.Media slot bottom transverse direction channel structure is in surface ditch After road exhausts, also it can continue to exhaust with the increase of anode voltage.Since all electric currents can flow through bottom lateral channel, and It is similar to the direction that channeled substrate knot exhausts vertical, therefore the flowed through path of device current persistently narrows, and dynamic electric resistor increases, Device has very high constant-current characteristics.

In real work, device metal anode 12 connects high potential, and metallic cathode 11 connects low potential, spreads P Depletion layer is formed between type well region and N-type lightly doped epitaxial layer, region forms vertical JFET ditch between two cellulars diffusion P type trap zone Road.As anode voltage increases, surface depletion channel depletion layer constantly extends upwards, and the broadening of depletion layer leads to conducting channel Region narrows.For channel before non-pinch off, characteristic is equivalent to a semiconductor resistor, and electric current increases with the increase of voltage and linearly Greatly, device state works in linear zone at this time；When anode voltage, which continues to increase to, keeps surface channel completely depleted, channel region By pinch off, anode voltage at this time is known as pinch-off voltage, after channel pinch off, continues growing anode voltage, pinch-off point is with anode electricity Slowly, device current, which is pushed the speed, to slow down for the increase variation of pressure, and device work at this time is in transitional region；Then it is further added by anode electricity Pressure, channel carriers speed reach saturation state, area's strong electrical field are depleted when reaching pinch-off point and is swept into the first N-type heavy doping Qu Zhong, pinch-off point and current value all no longer change substantially, and device works in constant current area.In the process, it is located at adjacent diffusion p-type Vertical JFET channel region both ends between well region also have similar folder of the depletion layer to centre extension since there is also pressure drops Disconnected process.After device realizes that pinch off enters constant current area, the lateral channel region between medium trench bottom and P type substrate is not yet Pinch off.After anode voltage continues growing, lateral channel can persistently be exhausted, and the circulation path of electric current persistently narrows, therefore can be made Device dynamic resistance is maintained at higher level, and device has very excellent constant-current characteristics.

In addition, spacing, Implantation Energy and the knot time of adjustment diffusion P type trap zone, make vertical-channel and surface depletion ditch Road area realizes pinch off simultaneously, can further promote device constant-current characteristics；Current value size can inject phosphonium ion by adjusting tune ditch Dosage, N-type deplection type channel section length and diffusion P type trap zone dosage are adjusted；Metallic cathode 11 and metal anode 12 can To extend to form field plate structure, Metal field plate adjustable in length, in conjunction with the common assisted depletion extension of p-type doped substrate to two sides Layer realizes the higher forward break down voltage of device.

As shown in Fig. 1 (b), 2 (b), a kind of semiconductor devices that second embodiment of the invention provides is in the present invention first On the basis of embodiment, metallic cathode 11 and metal anode 12 is made to extend to form field plate knot along the surface of oxide isolation layer 10 Structure.In the structure, field plate length is adjustable, can effectively shield high electric field peak value at media slot bottom corners, in optimised devices body Field distribution makes device obtain more high-breakdown-voltage.

As shown in Fig. 1 (c), a kind of semiconductor devices that third embodiment of the invention provides is implemented in the present invention first On the basis of example, the second conduction type of groove sidewall doped region 13 is also set up, the second conduction type of groove sidewall doped region 13 is located at exhausted Between the second conduction type well region (4) of edge media slot 5 and diffusion, and with diffusion the second conduction type well region 4 and the first conductive-type Type lightly doped epitaxial layer 3 contacts.

Above-described embodiment can amplified medium trench bottom turning and diffusion 4 lower zone of the second conduction type well region exhaust effect Fruit, optimized medium slot corner electric field promote device pressure voltage, and improve device constant-current characteristics, increase device motional impedance.

As shown in Fig. 1 (d), a kind of semiconductor devices that fourth embodiment of the invention provides is implemented in the present invention first It further include buries oxide layer 15, buries oxide layer 15 is located at the second conductivity type substrate 2 and the first conduction type is gently mixed on the basis of example Between miscellaneous epitaxial layer 3, and the doping type of the third heavily doped region 9 is replaced with into the second conduction type, it is heavily doped to form the 4th Miscellaneous area 14.

In above-described embodiment, semiconductor devices is bipolar device, and current density is big compared with monopole type device.Due to there are two types of Carrier participates in conductive, and not only current density is high under identical anode voltage, and due to the conductivity modulation effect in epitaxial layer, Device can be easier to be rapidly achieved saturation state, have lesser pinch-off voltage.Metal anode and cathode are extended to form to two sides Field plate structure alleviates oxide isolation trench bottom electric field concentration effect, effectively prevent device that premature breakdown occurs, and it is resistance to promote device Pressure value.For bipolar device, due to the second conduction type of positive contact area, the first conduction type lightly doped epitaxial layer and diffusion The intrinsic Earl benefit effect of the parasitic-PNP transistor that type well region is formed, device curve of output is in the increase of anode voltage It rises obviously, motional impedance value is smaller, and constant-current characteristics is generally poor.And in the embodiment of the present invention dielectric slot use, in slot Lateral channel structure is introduced between bottom and substrate, with the increase of anode voltage, effective channel thickness can narrow, and be equivalent to prolong The effective base width of parasitic-PNP transistor has been grown, there is certain inhibiting effect for Earl benefit effect, has guaranteed that device is higher dynamic State impedance value.And in view of the punchthrough issues of longitudinal parasitic-PNP transistor, using soi wafer structure, served as a contrast in the second conduction type It is provided with buries oxide layer 15 between bottom 2 and the first conduction type lightly doped epitaxial layer 3, it can be to avoid longitudinal parasitic-PNP transistor Electrical leakage problems can avoid the excessive deterioration for bringing device constant-current characteristics.

It optionally, further include buries oxide layer 15, buries oxide layer 15 is located at the second conductivity type substrate 2 and the first conduction type Between lightly doped epitaxial layer 3, and the doping of the third heavily doped region 9 is replaced with into the second conduction type and is lightly doped, forms the Two conduction type lightly doped districts.It is parasitism PNP crystal in order to prevent that anode in the structure is lightly doped using the second conduction type Pipe reduces hole current ratio by 13 premature breakdown of the second conduction type of groove sidewall doped region, guarantees device constant current Characteristic.

Optionally, the packing material of the dielectric slot 5 is silica, silicon nitride or silica and polysilicon Mixture.The packing material of the dielectric slot 5 can also be the mixing of other insulating materials or multiple material.In addition, absolutely The transverse width of edge media slot 5 is adjustable, so that device obtains different pressure voltages；Longitudinal depth of dielectric slot 5 is adjustable, And then changing current path length and trench bottom lateral channel thickness, optimised devices constant-current characteristics promotes device motional impedance value.

Optionally, material used by the semiconductor devices is silicon or silicon carbide.

Optionally, first conduction type is N-type, and second conduction type is p-type；Or first conductive-type Type is p-type, and second conduction type is N-type.P-type material substrate can be used in the second conductivity type substrate 2 at this time, plays to ditch Assisted depletion effect in road is accelerated JFET conducting channel and is exhausted, and pinch-off voltage can reach 3.5V or less.

By means of MEDICI device architecture simulation software to the structure cell of the semiconductor devices of second embodiment of the invention Device simulation is carried out, as shown in figure 3, the second conduction type is p-type using the first conduction type as N-type, positive pressure resistance is 300V, Illustrate simulation parameter for the semiconductor devices that electric current is about 1.4E-5A/ μm: initial silicon wafer thickness is about 250 μm, and p-type is gently mixed The concentration of miscellaneous substrate is 3.6E14cm^-3, the concentration of N-type lightly doped epitaxial layer is 2.5E15cm^-3, epitaxy layer thickness is about 10.5 μ M, diffusion P type trap zone mix boron, and surface peak concentration is 4.0E17cm^-3, well region junction depth is 4.0 μm, and transverse width is about 9.0 μm or so, the distance of two adjacent diffusion P type trap zones is 3.0 μm；Dielectric slot 5 uses earth silicon material, transverse direction Having a size of 10.0 μm, longitudinal size is 6.5 μm；The first N-type heavily doped region and third N-type heavily doped region as Ohmic contact are mixed Enter phosphorus, peak concentration 8.0E19cm^-3, junction depth is 0.5 μm, it is equally used for the second p-type heavily doped region incorporation boron of Ohmic contact, Peak concentration is also 8.0E19cm^-3, junction depth is 0.5 μm；For the length in deplection type channel area at 3.5 μm or so, the thickness of channel is big About 50nm, doping concentration 7.5E17cm^-3；Metallic cathode 11 and metal anode 12 with a thickness of 2.5 μm, and both across Media slot about 4.0um forms Metal field plate structure；The first N-type of cathode portion heavily doped region, deplection type channel area and the region JFET The oxidated layer thickness of top is 0.8um.As shown in figure 4, be computed it can be concluded that device pinch-off voltage in 3.5V hereinafter, pinch off Voltage and constant current value can be adjusted by adjusting implantation dosage, the deplection type channel area implantation dosage of diffusion P type trap zone, for The influence of the two parameters is the most significant for pinch-off voltage, while extension is lightly doped in two adjacent diffusion P type trap zone spacing, N-type Layer concentration also has some effects to device pinch-off behavior.It can be seen from the figure that after reaching constant current area, device current base Originally value is kept constant, there is very high motional impedance value, constant-current characteristics is very good.

As shown in figure 5, motional impedance value is 204M Ω, compared to general galvanostat when device work is under 20V voltage Part can promote more than ten times or more, have very high stability working normally output in interval range.N-type is reasonably adjusted gently to mix Extraordinary constant-current characteristics can be obtained in the parameters such as the thickness of miscellaneous epitaxial layer and concentration, the depth of dielectric slot 5.

As shown in Fig. 6 (a) -6 (h) and Fig. 7 (a) -7 (h), a kind of semiconductor device of fifth embodiment of the present invention offer The manufacturing method of part, comprising the following steps:

Select the second conduction type silicon wafer as the second conductivity type substrate 2, using epitaxy technique, shape over the substrate At the first conduction type lightly doped epitaxial layer 3；

The second conduction type well region 4 is spread in the formation being spaced in the first conduction type lightly doped epitaxial layer 3；

Media slot is formed in the two sides for the second conduction type of diffusion well region 4 that interval is formed, is filled using insulating medium layer The media slot forms dielectric slot 5；

Using ion implantation technology, ion implanting is carried out on entire first conduction type lightly doped epitaxial layer, 3 surface, is formed First conduction type deplection type channel area 6；

On the upper layer two for the section top and the first conduction type lightly doped epitaxial layer 3 for spreading the second conduction type well region 4 End forms the first heavily doped region 7 and third heavily doped region 9；

In the upper layer for spreading the second conduction type well region 4, the second heavily doped region is formed in the side of the first heavily doped region 7 8；

Oxide isolation layer 10 is formed in the first conduction type lightly doped epitaxial layer 3；Photoetching simultaneously etches the oxide isolation Layer 10 forms ohm hole, deposits aluminum metal and anti-carves, forms metallic cathode 11 and metal anode 12；

Passivation layer is deposited on oxide isolation layer 10, metallic cathode 11 and metal anode 12, etches the hole PAD；

Back note metal, forms back metal electrode below substrate.

In above-described embodiment, method, semi-conductor device manufacturing method of the invention injects knot in the epitaxial layer and forms well region, In Deplection type channel and JFET channel are respectively formed among well region surface and two well regions, the form of double channel improves device constant current effect Fruit and motional impedance value, in addition, using the pressure resistance of dielectric slot, medium groove depth and epitaxy layer thickness is rationally laterally arranged, The function that lateral channel can play optimization constant-current characteristics, promote motional impedance is then formed between medium trench bottom and substrate, greatly Enhance device outputting current steadily, also, use dielectric slot structure, is played in device inside and extend current path work With as anode voltage increases, depletion layer is persistently extended and then compressed to current path, and it is steady can to enhance device output current It is qualitative；Medium slot structure realizes the purpose that more excellent constant-current characteristics and more high voltage are obtained on smaller chip area.

Wherein, before being diffused P type trap zone 4 and injecting, pre-impregnated with hydrogen peroxide is carried out, then use photoetching process, and pass through ion Injection and the processing of high temperature knot form the second conduction type well region 4 of diffusion, and etching removes extra oxide layer, extra oxygen later Changing layer is the oxide layer generated by pre-impregnated with hydrogen peroxide and during the high temperature knot is handled, and is grown in device surface The oxide layer come.At this point, ion implantation energy is 80keV, the high temperature knot time is about 500 minutes；

Form the specific steps of insulating medium layer 5 are as follows: successively deposit on the surface of the first conduction type lightly doped epitaxial layer 3 Oxide layer and Si3N4 form media slot in the first conduction type lightly doped epitaxial layer 3 using lithography and etching technique, etching Insulating medium layer is deposited after falling Si3N4, etches the insulating medium layer and oxide layer on 3 surface of the first conduction type lightly doped epitaxial layer Dielectric slot 5 is formed afterwards；

Before carrying out the first heavily doped region 7 and being injected with third heavily doped region 9, pre-impregnated with hydrogen peroxide is carried out, photoetching work is then used Skill, then the first conductive type impurity is injected by ion implantation technology, to form the first heavily doped region 7 and third heavily doped region 9, the second conductive type impurity is injected using photoetching process, then by ion implantation technology, so that the second heavily doped region 8 is formed, Then etching removes extra oxide layer, and extra oxide layer is the oxide layer generated by pre-impregnated with hydrogen peroxide；

Formed the second conduction type well region 4 of diffusion, the first conduction type deplection type channel area 6, the first heavily doped region 7 with Before third heavily doped region 9, pre-impregnated with hydrogen peroxide is carried out to device, prevents subsequent impurity injection bring damage.The oxide isolation Layer 10 is dense oxide.

In addition, diffusion 4 implantation dosage of the second conduction type well region can be adjusted suitably, different first conduction types is cooperated to exhaust 6 implantation dosage of type channel region forms surface channel net doping dosage after the two impurity compensation, device is made to obtain the different magnitudes of current Grade；First conduction type deplection type channel area, 6 adjustable in length simultaneously, and then change device current value size and constant-current characteristics.

Optionally, the second conduction type well region 4 of diffusion is formed by multiple ion implanting, wherein rear primary ions injection Energy and dosage be lower than preceding primary ions injection energy and dosage.

Above-described embodiment weakens surface channel and diffusion well region impurity compensation degree, reduces surface depletion channel and leads with JFET Electric channel transitional region width is easy to surface channel pinch off, reduces pinch-off voltage, promotes device constant-current characteristics.Wherein, subsequent can It is formed by the pushing away trap process of short period.

Semiconductor devices proposed by the invention uses the second conductivity type substrate, and extension is lightly doped in the first conduction type In the suitable situation of thickness degree, can play two cellular of assisted depletion spread the second conduction type well region between the region JFET and its The effect of lower zone is accelerated JFET conducting channel and is exhausted, realizes lower pinch-off voltage and higher motional impedance；It is spreading It is provided with dielectric slot between second conduction type well region and third heavily doped region, it can be in conjunction with upper metal field plate structure It realizes on lesser chip area compared with high voltage value；Lateral conduction channel, channel are formed between medium trench bottom and substrate simultaneously Direction is exhausted perpendicular to current direction, and substrate further enhances device constant-current characteristics, institute to the assisted depletion effect of lateral channel The device designed has very high motional impedance value；And the introducing of dielectric slot is so that device inside current path length Increase, current direction preferably realizes device pinch-off behavior, device output perpendicular to direction is exhausted on most of current path With very high stability；Repeatedly injection can be used in manufacturing process and form the second conduction type well region of diffusion, shorten simultaneously The high temperature knot time weakens the second conduction type well region impurity compensation degree of surface depletion channel and diffusion, reduces surface depletion Channel and JFET conducting channel transitional region width are easy to surface channel pinch off, promote device constant current ability.Semiconductor of the present invention Length, medium groove width, the second conduction type well region of diffusion and the first conduction type deplection type channel area of device metal field plate The parameters such as dopant dose can be adjusted, and to meet different current classes and pressure voltage demand, increase the flexible of device design Property.

In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside", " up time The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.

In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three It is a etc., unless otherwise specifically defined.

In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc. Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.

In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below " One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.

In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples It closes and combines.

The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.