阅读说明：本技术 半导体器件及其形成方法 (Semiconductor devices and forming method thereof ) 是由 周飞 于 2018-05-25 设计创作，主要内容包括：一种半导体器件及其形成方法,方法包括：提供半导体衬底,半导体衬底上具有鳍部,鳍部包括若干层沿半导体衬底表面法线方向重叠的第一鳍部层、以及位于相邻两层第一鳍部层之间的第二鳍部层；形成伪栅极结构和位于伪栅极结构两侧的鳍部内的第一凹槽；去除第一凹槽侧壁的部分第一鳍部层以形成第一修正鳍部层和第一鳍部凹槽；在第一鳍部凹槽内形成阻挡层,阻挡层的材料为半导体材料,所述阻挡层内具有第一离子,第一离子填充所述阻挡层材料的原子间隙；在第一凹槽内形成具有源漏离子的源漏掺杂层；形成覆盖伪栅极结构侧壁的介质层；去除伪栅极结构和伪栅极结构覆盖的第二鳍部层形成栅开口；在栅开口内形成栅极结构。所述方法提高了半导体器件的性能。(A kind of semiconductor devices and forming method thereof, method includes: offer semiconductor substrate, there is fin, fin includes several layers along the first fin layer that semiconductor substrate surface normal direction is overlapped and the second fin layer between adjacent two layers the first fin layer in semiconductor substrate；Form dummy gate structure and the first groove in the fin of dummy gate structure two sides；Part the first fin layer of the first recess sidewall is removed to form the first amendment fin layer and the first fin groove；Barrier layer is formed in the first fin groove, the material on barrier layer is semiconductor material, has the first ion in the barrier layer, the first ion fills the atom gap of the barrier material；The source and drain doping layer with source and drain ion is formed in the first groove；Form the dielectric layer of covering dummy gate structure side wall；The the second fin layer for removing dummy gate structure and dummy gate structure covering forms grid opening；Gate structure is formed in grid are open.The method improves the performance of semiconductor devices.)

1. a kind of forming method of semiconductor devices characterized by comprising

Semiconductor substrate is provided, there is fin in semiconductor substrate, fin includes several layers along semiconductor substrate surface normal side The first fin layer to overlapping and the second fin layer between adjacent two layers the first fin layer；

It is developed across the dummy gate structure of fin, dummy gate structure covers the atop part surface and partial sidewall surface of fin；

The first groove is formed in the fin of dummy gate structure two sides；

Part the first fin layer of the first recess sidewall is removed to form the first amendment fin layer, and in adjacent second fin layer Between form the first fin groove, the first amendment fin layer side wall is relative to the second fin layer side walls collapse；

Barrier layer is formed in the first fin groove, the material on the barrier layer is semiconductor material, is had in the barrier layer First ion, first ion fill the atom gap of the barrier material；

After forming barrier layer, source and drain doping layer is formed in first groove, the source and drain doping layer has source and drain ion；

It is formed after source and drain doping layer, forms dielectric layer, the dielectric layer covering pseudo- grid in semiconductor substrate and fin Pole structure side wall；

The the second fin layer for removing dummy gate structure and dummy gate structure covering, in the dielectric layer and adjacent first corrects Grid opening is formed between fin layer；

Gate structure is formed in the grid are open, the gate structure surrounds the first amendment fin layer.

2. the forming method of semiconductor devices according to claim 1, which is characterized in that the forming step on the barrier layer It include: that initial resistance layer is formed in the first fin groove and the first groove after forming the first fin groove, it is described initial Barrier layer covers the first recess sidewall surface and the first bottom portion of groove surface；The part initial resistance layer is removed, exposes the Two fin layer side wall, form the barrier layer.

3. the forming method of semiconductor devices according to claim 2, which is characterized in that the material of the initial resistance layer Including silicon or SiGe；First ion includes carbon ion.

4. the forming method of semiconductor devices according to claim 3, which is characterized in that the formation of the initial resistance layer Technique includes epitaxial growth technology；The technique of the first ion is adulterated in initial resistance layer as doping process in situ.

5. the forming method of semiconductor devices according to claim 2, which is characterized in that removal part initial resistance layer Technique includes: isotropic dry etch process or isotropic wet-etching technology.

6. the forming method of semiconductor devices according to claim 1, which is characterized in that after forming barrier layer, form source Leak doped layer before, further includes: removal the first recess sidewall part the second fin layer, adjacent two layers first correct fin layer it Between formed the second fin groove and second amendment fin layer；Separation layer, the separation layer side wall are formed in the second fin groove It is flushed with dummy gate structure side wall.

7. the forming method of semiconductor devices according to claim 6, which is characterized in that the forming method of the separation layer It include: to form initial seal coat in first groove and the second fin groove；Using the dummy gate structure as mask etching The initial seal coat forms the separation layer up to exposing the first bottom portion of groove surface.

8. the forming method of semiconductor devices according to claim 7, which is characterized in that the formation of the initial seal coat Technique is one of chemical vapor deposition process, physical gas-phase deposition or atom layer deposition process or multiple combinations.

9. the forming method of semiconductor devices according to claim 6, which is characterized in that the material of the separation layer includes Silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.

10. the forming method of semiconductor devices according to claim 1, which is characterized in that form the fin structure Method includes: to form fin material membrane on the semiconductor substrate, and fin material membrane several layers are along semiconductor substrate surface method The the first fin film and the second fin film in adjacent two layers the first fin layer of line direction overlapping；In the fin material Patterned layer is formed on material film；Using the patterned layer as exposure mask, the fin material membrane is etched to form fin, and make first Fin film forms the first fin layer, and the second fin film is made to form the second fin layer.

11. the forming method of semiconductor devices according to claim 10, which is characterized in that the material of the first fin layer Expect different with the material of the second fin layer；The material of the first fin layer is monocrystalline silicon or monocrystalline germanium silicon；Second fin The material of layer is single-crystal silicon Germanium or monocrystalline silicon.

12. the forming method of semiconductor devices according to claim 1, which is characterized in that the dummy gate structure is also wrapped Include the side wall of covering dummy gate structure sidewall surfaces.

13. the forming method of semiconductor devices according to claim 1, which is characterized in that removal dummy gate structure and puppet The step of second fin layer of gate structure covering includes: to remove dummy gate structure after forming dielectric layer, formed in the dielectric layer Initial grid opening；The second amendment fin layer that initial grid opening exposes is removed, initial grid is made to be open to form the grid opening.

14. the forming method of semiconductor devices according to claim 1, which is characterized in that the shape of the source and drain doping layer It include epitaxial growth technology at technique；The technique of doped source and drain ion is doping process in situ in source and drain doping layer.

15. the forming method of semiconductor devices according to claim 14, which is characterized in that when the semiconductor devices is When P-type device, the material of the source and drain doping layer includes: silicon, germanium or SiGe；The source and drain ion is P-type ion, the source and drain Ion includes boron ion, BF^2-Ion or indium ion.

16. the forming method of semiconductor devices according to claim 14, which is characterized in that when the semiconductor devices is When N-type device, the material of the source and drain doping layer includes: silicon, GaAs or indium gallium arsenic；The source and drain ion is N-type ion, institute Stating source and drain ion includes phosphonium ion or arsenic ion.

17. the forming method of semiconductor devices according to claim 1, which is characterized in that the gate structure includes grid Dielectric layer and the grid layer on the gate dielectric layer.

18. the forming method of semiconductor structure according to claim 17, which is characterized in that the gate structure also wraps Include: positioned at the boundary layer of the grid open bottom, the gate dielectric layer covers boundary layer.

19. a kind of semiconductor devices characterized by comprising

Semiconductor substrate；

Fin in semiconductor substrate, the fin include that several layers are overlapped along semiconductor substrate surface normal direction One amendment fin layer；

Gate structure on the fin；The gate structure is also located at adjacent two layers first and corrects between fin layer；

Source and drain doping layer positioned at gate structure and side wall two sides, the source and drain doping layer have source and drain ion；

Barrier layer between the first amendment fin layer and source and drain doping layer, the material on the barrier layer are semiconductor material, There is the first ion, first ion fills the atom gap of the barrier material in the barrier layer；

Dielectric layer on semiconductor substrate, fin, gate structure and source and drain doping layer, dielectric layer cover gate structure sidewall With source and drain doping layer side wall and top surface, gate structure top surface is exposed.

Technical field

The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.

Background technique

With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density and higher The direction of integrated level is developed.Device is just widely used at present as most basic semiconductor devices, traditional planar device pair The control ability of channel current dies down, and generates short-channel effect and leads to leakage current, the final electrical property for influencing semiconductor devices Energy.

In order to overcome the short-channel effect of device, inhibit leakage current, the prior art proposes fin formula field effect transistor (Fin FET), fin formula field effect transistor are a kind of common multi-gate devices, and the structure of fin formula field effect transistor includes: position Fin and barrier layer in semiconductor substrate surface, the side wall of fin described in the barrier layer covering part, and barrier layer surface Lower than at the top of fin；Gate structure positioned at the top and sidewall surfaces of barrier layer surface and fin；Positioned at the grid knot Source region and drain region in the fin of structure two sides.

However, the performance for the semiconductor devices that the prior art is formed is poor.

Summary of the invention

The technical problem to be solved by the present invention is to provide a kind of semiconductor devices and forming method thereof, to improve semiconductor devices Performance.

In order to solve the above technical problems, the present invention provides a kind of forming method of semiconductor devices, comprising: provide semiconductor Substrate has fin in semiconductor substrate, and fin includes the first fin that several layers are overlapped along semiconductor substrate surface normal direction Portion's layer and the second fin layer between adjacent two layers the first fin layer；It is developed across the dummy gate structure of fin, pseudo- grid The atop part surface and partial sidewall surface of pole structure covering fin；It is recessed that first is formed in the fin of dummy gate structure two sides Slot；Part the first fin layer of the first recess sidewall is removed to form the first amendment fin layer, and in adjacent second fin layer Between form the first fin groove, the first amendment fin layer side wall is relative to the second fin layer side walls collapse；In the first fin Barrier layer is formed in portion's groove, the material on the barrier layer is semiconductor material, has the first ion in the barrier layer, described First ion fills the atom gap of the barrier material；After forming barrier layer, source and drain is formed in first groove and is mixed Diamicton, the source and drain doping layer have source and drain ion；It is formed after source and drain doping layer, is formed and be situated between in semiconductor substrate and fin Matter layer, the dielectric layer cover the dummy gate structure side wall；Remove the second fin of dummy gate structure and dummy gate structure covering Portion's layer is forming grid opening in the dielectric layer and between the first adjacent amendment fin layer；Grid are formed in the grid are open Pole structure, the gate structure surround the first amendment fin layer.

Optionally, the forming step on the barrier layer includes: after forming the first fin groove, in the first fin groove With formation initial resistance layer in the first groove, the initial resistance layer covers the first recess sidewall surface and the first bottom portion of groove table Face；The part initial resistance layer is removed, the second fin layer side wall is exposed, forms the barrier layer.

Optionally, the material of the initial resistance layer includes silicon or SiGe；First ion includes carbon ion.

Optionally, the formation process of the initial resistance layer includes epitaxial growth technology；Is adulterated in initial resistance layer The technique of one ion is doping process in situ.

Optionally, the technique for removing part initial resistance layer includes: isotropic dry etch process or isotropism Wet-etching technology.

Optionally, after forming barrier layer, before forming source and drain doping layer, further includes: the part the of the first recess sidewall of removal Two fin layers are corrected in adjacent two layers first and form the second fin groove and the second amendment fin layer between fin layer；Second Separation layer is formed in fin groove, the separation layer side wall and dummy gate structure side wall flush.

Optionally, the forming method of the separation layer includes: and is formed just in first groove and the second fin groove Beginning separation layer；Using the dummy gate structure as initial seal coat described in mask etching until exposing the first bottom portion of groove surface, Form the separation layer.

Optionally, the formation process of the initial seal coat be chemical vapor deposition process, physical gas-phase deposition or One of atom layer deposition process or multiple combinations.

Optionally, the material of the separation layer include silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or Carbon silicon oxynitride.

Optionally, the method for forming the fin structure includes: to form fin material membrane, fin on the semiconductor substrate The the first fin film and be located at the first fin of adjacent two layers that portion's material membrane several layers are overlapped along semiconductor substrate surface normal direction The second fin film in portion's layer；Patterned layer is formed on the fin material membrane；Using the patterned layer as exposure mask, institute is etched Fin material membrane is stated to form fin, and the first fin film is made to form the first fin layer, the second fin film is made to form the second fin Layer.

Optionally, the material of the material of the first fin layer and the second fin layer is different；The material of the first fin layer Material is monocrystalline silicon or monocrystalline germanium silicon；The material of the second fin layer is single-crystal silicon Germanium or monocrystalline silicon.

Optionally, the dummy gate structure further includes the side wall for covering dummy gate structure sidewall surfaces.

Optionally, the step of removing the second fin layer that dummy gate structure and dummy gate structure cover includes: to form medium After layer, dummy gate structure is removed, forms initial grid opening in the dielectric layer；Remove the second amendment fin that initial grid opening exposes Portion's layer makes initial grid be open to form the grid opening.

Optionally, the formation process of the source and drain doping layer includes epitaxial growth technology；The doped source in source and drain doping layer The technique for leaking ion is doping process in situ.

Optionally, when the semiconductor devices is P-type device, the material of the source and drain doping layer includes: silicon, germanium or silicon Germanium；The source and drain ion is P-type ion, and the source and drain ion includes boron ion, BF^2-Ion or indium ion.

Optionally, when the semiconductor devices is N-type device, the material of the source and drain doping layer includes: silicon, GaAs Or indium gallium arsenic；The source and drain ion is N-type ion, and the source and drain ion includes phosphonium ion or arsenic ion.

Optionally, the gate structure includes gate dielectric layer and the grid layer on the gate dielectric layer.

Optionally, the gate structure further include: positioned at the boundary layer of the grid open bottom, the gate dielectric layer covering Boundary layer.

The present invention also provides a kind of semiconductor devices, comprising: semiconductor substrate；Fin in semiconductor substrate, institute Stating fin includes the first amendment fin layer that several layers are overlapped along semiconductor substrate surface normal direction；On the fin Gate structure；The gate structure is also located at adjacent two layers first and corrects between fin layer；Positioned at gate structure and side wall two sides Source and drain doping layer, the source and drain doping layer have source and drain ion；Between the first amendment fin layer and source and drain doping layer Barrier layer, the material on the barrier layer are semiconductor material, have the first ion, the first ion filling in the barrier layer The atom gap of the barrier material；Dielectric layer on semiconductor substrate, fin, gate structure and source and drain doping layer, Dielectric layer covers gate structure sidewall and source and drain doping layer side wall and top surface, exposes gate structure top surface.

Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that

In the forming method for the semiconductor devices that technical solution of the present invention provides, removal part the first fin layer forms first Fin groove and the first amendment fin layer, form barrier layer in the first fin groove, and barrier layer is located at the first amendment fin layer Between the source and drain doping layer being subsequently formed, the material on the barrier layer is semiconductor material, has the first ion in barrier layer, The first ion in barrier layer fills the atom gap of the barrier material, block source and drain ion in source and drain doping layer into Enter barrier layer, enter in the atomic lattice gap of the first amendment fin layer to reduce the source and drain ion in source and drain doping layer, It reduces source and drain ion and enters channel region, reduce the probability of happening of short-channel effect, improve the performance of semiconductor devices.

Further, the position of the second amendment fin layer of dummy gate structure covering is subsequent will form gate structure, grid knot It is isolated between structure and source and drain doping layer by separation layer, separation layer determines grid along the size for being parallel to orientation The distance between pole structure and source and drain doping layer, separation layer increase distance between the two, reduce parasitism between the two Capacitor, to optimize the performance of semiconductor devices.

Detailed description of the invention

Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process；

Fig. 4 to Figure 16 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.

Specific embodiment

As described in background, the performance of the semiconductor devices of the prior art is poor.

Fig. 1 to Fig. 3 is a kind of structural schematic diagram of semiconductor devices forming process；

With reference to Fig. 1, semiconductor substrate 100 is provided, there is fin 110 and separation layer 101, fin in semiconductor substrate 100 110 include the first fin layer 111 that several layers be overlappeds along 100 surface normal direction of semiconductor substrate and positioned at adjacent two layers The second fin layer 112 in first fin layer has protective layer on fin 110.

With reference to Fig. 2, it is developed across the dummy gate structure 120 of fin 110；It is exposure mask with the dummy gate structure 120, removal The fin structure 110 of 120 two sides of dummy gate structure forms groove.

With reference to Fig. 3, source and drain doping layer 150, source and drain doping layer are epitaxially formed in the groove of 120 two sides of dummy gate structure There is source and drain doping ion in 150；It is formed after source and drain doping layer 150, removes pseudo- grid structure 120 and the second fin layer 112, shape It is open at grid；The grid be open in formed gate structure 160, the gate structure be also located at adjacent first fin layer 111 it Between.

To reduce the contact resistance between source and drain doping layer and the plug being subsequently formed, a kind of method is to improve source and drain doping The doping concentration of layer.Source and drain doping layer is high-concentration dopant, and the Doped ions of high-concentration dopant are easy to happen diffusion, hence into Channel region, so that there is source and drain doping ion, so as to cause short-channel effect, so that being formed by semiconductor devices in channel region Performance is poor.

In the present invention, by forming barrier layer between the first fin layer and source and drain doping layer, the material on barrier layer is half Conductor material has the first ion in the barrier layer, and the first ion fills the atom gap of the barrier material, so that source Source and drain ion in leakage doped layer cannot be introduced into the atomic lattice gap on barrier layer, to inhibit the source in source and drain doping layer It leaks Doped ions and enters the first fin layer, reduce short-channel effect, improve the performance of device.The method, which provides, partly to be led The performance of body device.

To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention Specific embodiment be described in detail.

Fig. 4 to Figure 16 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.

Fig. 4 and Fig. 5 are please referred to, Fig. 5 is the sectional view of the M-M1 along Fig. 4, provides semiconductor substrate 200, semiconductor substrate There is fin 210, fin 210 includes the first fin layer that several layers are overlapped along semiconductor substrate surface normal direction on 200 211 and the second fin layer 212 in the first fin of adjacent two layers layer 211.

The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；The semiconductor substrate 200 can also be with It is the semiconductor materials such as silicon, germanium, SiGe, GaAs；In the present embodiment, the material of the semiconductor substrate 200 is monocrystalline silicon.

The method for forming the fin 210 includes: formation fin material membrane, fin material in the semiconductor substrate 200 The first fin film that material film, which includes several layers, be overlapped along 200 surface normal direction of semiconductor substrate and positioned at adjacent two layers the The second fin film in one fin film；Patterned layer is formed on the fin material membrane；Using the patterned layer as exposure mask, carve The fin material membrane is lost to form fin 210, and the first fin film is made to form the first fin layer 211, makes the second fin film shape At the second fin layer 212.

First fin layer 211 is different with the material of the second fin layer 212.Specifically, the material of the first fin layer 211 For monocrystalline silicon, the material of the second fin layer 212 is monocrystalline germanium silicon；Or the material of the first fin layer 211 is monocrystalline Germanium silicon, the material of the second fin layer 212 are monocrystalline silicon.

In the present embodiment, the material of the first fin layer 211 is monocrystalline silicon, and the material of the second fin layer 212 is Monocrystalline germanium silicon.

With continued reference to Fig. 4 and Fig. 5, isolation structure 201 is formed in the semiconductor substrate 200, isolation structure 201 covers The partial sidewall of fin structure 210.

The top surface of the isolation structure 201 is lower than the top surface of fin 210.The material of the isolation structure 201 Including silica.

The method for forming the isolation structure 201 includes: that covering fin structure is formed in the semiconductor substrate 200 210 isolation structure film (not shown)；It is etched back to isolation structure film, forms the isolation structure 201.

The technique for forming the isolation structure film is depositing operation, such as fluid chemistry gas-phase deposition.Using fluidisation It learns gas-phase deposition and forms isolation structure film, keep the filling capacity of isolation structure film preferable.

In the present embodiment, further includes: before forming the isolation structure film, formed on 210 surface of fin structure Protective layer (not shown)；Protective layer is etched back to while being etched back to isolation structure film.

The material of the protective layer includes silicon oxide or silicon nitride.The effect of the protective layer includes: to form isolation junction In structure membrane process, steam is isolated, avoids consumption fin structure 210.

Referring to FIG. 6, being developed across the dummy gate structure of fin structure 210, dummy gate structure covers fin structure 210 Atop part surface and partial sidewall surface.

The dummy gate structure includes the side wall of dummy gate structure ontology and covering this body sidewall of dummy gate structure.The side Wall includes the first side wall 231 and the second side wall 241, and the first side wall 231 is located at this body sidewall of dummy gate structure, the second side wall 241 Positioned at 231 side wall of the first side wall.

In the present embodiment, the dummy gate structure ontology include: dummy gate layer 220 and be located at 220 top table of dummy gate layer The protective layer 202 in face.

The material of the dummy gate layer 220 includes: polysilicon.

The material of the protective layer 202 includes: silicon oxide or silicon nitride.

In other embodiments, the dummy gate structure ontology includes: pseudo- gate oxide and positioned at pseudo- gate oxide surface Dummy gate layer.The material of the puppet gate oxide includes silica.

First side wall 231 is located at dummy gate structure two sides, covers 220 sidewall surfaces of dummy gate structure.

First side wall 231 protects dummy gate structure during ion implanting forms lightly doped district, and can define light The position of doped region.

The forming step of first side wall 231 includes: in the isolation structure 201, fin structure 210 and dummy grid knot The first spacer material layer is formed on structure；It is etched back to the first spacer material layer, until exposing the fin protective layer 202 The top surface of top surface and pseudo- grid protective layer, forms on fin protective layer 202 and is covered in the dummy gate structure side wall The first side wall 231.

The formation process of the first spacer material layer is chemical vapor deposition process, physical gas-phase deposition or atom One of layer depositing operation or multiple combinations.The material of first side wall 231 include silica, silicon nitride, silicon oxynitride, Silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.

Second side wall 241 is located at 231 two sides of dummy gate structure 220 and the first side wall, covers 231 side wall of the first side wall Surface.

Second side wall is used to define the position of source and drain doping layer.

The forming step of second side wall 241 includes: in the isolation structure 201, fin structure 210, dummy grid knot Second side walling bed of material is formed on structure and the first side wall 231；It is etched back to second side walling bed of material, until exposing the fin The top surface of the top surface of portion's protective layer 202 and pseudo- grid protective layer forms on fin protective layer 202 and is covered in described the Second side wall 241 of one side wall, 231 side wall.

The formation process of second side walling bed of material is chemical vapor deposition process, physical gas-phase deposition or atom One of layer depositing operation or multiple combinations.The material of second side wall 241 include silica, silicon nitride, silicon oxynitride, Silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.

First side wall and the second side wall define the distance between the gate structure being subsequently formed and source and drain doping layer.

Referring to FIG. 7, being formed after dummy gate structure, the first groove 203 is formed in the fin of dummy gate structure two sides.

The method for forming first groove 203 includes: to etch the fin 210 using the dummy gate structure as exposure mask, The first groove 203 is formed in the fin 210 of dummy gate structure two sides.

First groove 203 provides space to be subsequently formed source and drain doping layer.

The technique for etching the fin 210 includes: anisotropic dry etch process or anisotropic wet etching Technique.

In the present embodiment, the technique for etching the fin 210 is anisotropic dry etch process, the dry etching The parameter of technique includes: that the etching gas of use includes HBr and Ar, wherein the flow velocity of HBr is 10sccm~1000sccm, Ar Flow velocity be 10sccm~1000sccm.

Referring to FIG. 8, being formed after the first groove 203, part the first fin layer 211 of 203 side wall of the first groove is removed To form the first amendment fin layer 213, first corrects 213 side wall of fin layer relative to 212 side walls collapse of the second fin layer, and The first fin groove 204 is formed between adjacent second fin layer 212.

The first fin groove 204 provides sky between adjacent second fin layer 212 to be subsequently formed barrier layer Between.

The side wall of the first amendment fin layer 213 is relative to the side wall protrusion of the dummy gate layer 220 or concordant.Institute Stating the first amendment fin layer 213 has perpendicular to the dummy gate structure extending direction and along the first of 210 extending direction of fin Width D 1, the dummy gate layer 220 have perpendicular to the dummy gate structure extending direction and along the of 210 extending direction of fin Two width Ds 2；First width D 1 is more than or equal to second width D 2, and first width D 1 is less than described second The summation of 241 thickness of width D 2 and 231 thickness of the first side wall and the second side wall.First width D 1 is 20nm~40nm, Second width D 2 is 15nm~28nm.

First width D 1 is less than second width D 2, and the width of the first amendment fin layer 213 is less than pseudo- grid The width of pole layer 220, the channel distance for the semiconductor devices being subsequently formed shorten, and carrier pathway becomes smaller, and device performance is deteriorated； When first width D 1 is excessive, the barrier layer being subsequently formed is shorter along the distance of fin extending direction, source and drain doping leafing ditch Road area is closer, and the source and drain ion in source and drain doping layer is easily accessible in channel region, inhibits the effect of short-channel effect poor.

The technique for removing part the first fin layer 211 is wet-etching technology.The etching liquid pair of the wet etching Silicon and SiGe have selection ratio well, can guarantee that the pattern of SiGe is unaffected while removing silicon.Institute in the present embodiment It is tetramethyl ammonium hydroxide solution that the parameter for stating wet-etching technology, which includes: etching liquid, and temperature is 20 degrees Celsius~80 degrees Celsius, The percent by volume of the tetramethyl ammonium hydroxide solution is 10%~80%.

In the present embodiment, the material of the first fin layer 211 is silicon, and the material of the second fin layer 212 is SiGe, tetramethyl used The selection ratio that base ammonium hydroxide etching liquid has just had.

Referring to FIG. 9, after forming the first fin groove 204, in the first fin groove 204 and the first groove 203 Initial resistance layer 205 is formed, the initial resistance layer 205 covers 203 sidewall surfaces of the first groove and 203 bottom table of the first groove Face.

The material of the initial resistance layer 205 is semiconductor material, has the first ion in the initial resistance layer, described First ion fills the atom gap of the barrier material.

The material of the initial resistance layer 205 includes silicon or SiGe；First ion includes carbon ion.

The formation process of the initial resistance layer 205 includes epitaxial growth technology；First is adulterated in initial resistance layer 205 The technique of ion is doping process in situ.

In the present embodiment, the material of the initial resistance layer 205 is silicon, and first ion is carbon ion.Described first The concentration of ion is 1.0E19atm/cm³~1.0E22atm/cm³.The initial resistance layer is formed using epitaxial growth technology 205, be epitaxially formed the initial resistance layer 205 technological parameter include: use gas include hydrogen, HCl gas, SiH₂Cl₂、PH₃And CH₃SiH₃Gas, the flow of hydrogen are 2000sccm~20000sccm, and the flow of HCl gas is 30sccm ~150sccm, SiH₂Cl₂Flow be 50sccm~1000sccm, PH₃Flow be 10sccm~2000sccm, CH₃SiH₃'s Flow is 50sccm~5000sccm, and chamber pressure is 10torr~600torr, and temperature is 650 degrees Celsius~850 degrees Celsius.

When the carbon ion excessive concentration, cluster defect easy to form；When the carbon ion concentration is too low, the resistance that is subsequently formed The limited amount of carbon ion in barrier, the then scarce capacity of barrier material lattice, the source and drain ion in source and drain doping layer still can Entered in the material lattice of channel region by barrier layer, inhibits short-channel effect scarce capacity.

Referring to FIG. 10, the removal part initial resistance layer 205 exposes the second fin after forming initial resistance layer 205 Portion's 212 side wall of layer, form barrier layer 206.

The barrier layer 206 is located in the first fin groove 204, and the barrier layer 206 is located at adjacent second fin layer 212 Between, in same plane, the barrier layer 206 also exposes the first groove for 206 side wall of barrier layer and 212 side wall of the second fin layer 204 bottom part surfaces.

The material on the barrier layer 206 is semiconductor material, has the first ion, the first ion in the barrier layer 206 Fill the atom gap of 206 material of barrier layer.

Barrier layer 206 is located between the first amendment fin layer 213 and the source and drain doping layer being subsequently formed, the barrier layer 206 material is semiconductor material, has the first ion in barrier layer 206, and the first ion in barrier layer 206 fills the resistance The atom gap of barrier material, the source and drain ion blocked in source and drain doping layer enter barrier layer 206, mix to reduce source and drain Source and drain ion in diamicton enters in the atomic lattice gap of the first amendment fin layer 213, reduces source and drain ion and enters channel region, The probability of happening for reducing short-channel effect improves the performance of device.

It includes: isotropic dry etch process or isotropic wet for removing the technique of part initial resistance layer 205 Method etching technics.

In the present embodiment, the technique of the removal part initial resistance layer 205 is isotropic dry etch process, institute Stating the gas that dry etch process parameter includes: use includes CF₄Gas, CH₃F gas and O₂, CF₄The flow of gas is 5sccm ~100sccm, CH₃The flow of F gas is 8sccm~50sccm, O₂Flow be 10sccm~100sccm, chamber pressure is 10mtorr~2000mtorr, source radio-frequency power are 50W~300W, and bias voltage is 30V~100V, and the time is 4 seconds~50 seconds.

In other embodiments, the step of removal part initial resistance layer 205 includes: to be etched back to the initial resistance layer 205, expose 203 bottom part surfaces of the first groove；Using the dummy gate structure as exposure mask, etching removal 210 side wall of fin Initial resistance layer 205, formed barrier layer 206.The etching technics is anisotropic dry etching.

Figure 11 is please referred to, after forming barrier layer 206, removes part the second fin layer 212, In of 203 side wall of the first groove Adjacent two layers first, which are corrected, forms the second fin groove 207 and the second amendment fin layer 214 between fin layer 213.

The second fin groove 207 is located between adjacent first amendment fin layer 213, provides to be subsequently formed separation layer Space.

The side wall of the second amendment fin layer 214 is relative to the side wall protrusion of the dummy gate layer 220 or concordant.Institute Stating the second amendment fin layer 214 has perpendicular to the dummy gate structure extending direction and along the third of 210 extending direction of fin Width D 3, the dummy gate layer 220 have perpendicular to the dummy gate structure extending direction and along the of 210 extending direction of fin Two width Ds 2；The third width D 3 is more than or equal to second width D 2, and the third width D 3 is less than described second The summation of 241 thickness of width D 2 and 231 thickness of the first side wall and the second side wall.The third width D 3 is 24nm~56nm.

The third width D 3 is less than second width D 2, and the width of the second amendment fin layer 214 is less than pseudo- grid The width of pole layer 220, the channel distance for the semiconductor devices being subsequently formed shorten, and carrier pathway becomes smaller, and device performance is deteriorated； When the third width D 3 is excessive, the separation layer distance being subsequently formed is shorter, the grid layer and source and drain doping layer being subsequently formed it Between be closer, parasitic capacitance between the two is larger.

Third width D 3 is greater than the first width D 1, and the difference of third width D 3 and the first width D 1 is 4nm~16nm.

The technique for removing part the second fin layer 212 is wet-etching technology.The wet etching solution to silicon and SiGe has selection ratio well, can guarantee that the pattern of silicon is unaffected while removing SiGe.It is wet described in the present embodiment The parameter of method etching includes: the solution that etching liquid is HCl gas, and temperature is 25 degrees Celsius~300 degrees Celsius, the HCl gas Solution percent by volume be 20%~90%.

In the present embodiment, the material of the first fin layer is silicon, and the material of the second fin layer is SiGe, used to be etched with HCl The selection ratio that liquid has just had.

Figure 12 is please referred to, after forming the second fin groove 207, in first groove 203 and the second fin groove 207 Form initial seal coat 208.

The initial seal coat 208 is to be subsequently formed separation layer 209 to provide material layer.

The initial seal coat 208 covers dummy gate structure top surface and sidewall surfaces, and the initial seal coat 208 is also Cover the barrier layer 206 for the fin 210 that 203 side wall of the first groove exposes and the side wall and the of the second amendment fin layer 214 The bottom surface of one groove 203.

The formation process of the initial seal coat 208 is chemical vapor deposition process, physical gas-phase deposition or atom One of layer depositing operation or multiple combinations.

The material of the initial seal coat 208 include silica, silicon nitride, silicon oxynitride, silicon oxide carbide, carbonitride of silicium or Carbon silicon oxynitride.

In the present embodiment, the initial seal coat 208, the initial seal coat 208 are formed using atom layer deposition process Material be silicon nitride.The atom layer deposition process parameter includes: the gas that uses for SiH₂Cl₂And NH₃Mixed gas, The flow of mixed gas is 1500sccm~4000sccm, and pressure is 1mtorr~10mtorr, and temperature is 200 degrees Celsius~600 Degree Celsius, frequency of depositing is 30 times~100 times.

Atom layer deposition process has good step coverage, and film forming is uniform, the separation layer of formation, in fin groove Filling effect it is good.

In other embodiments, the formation process of the initial seal coat 208 is chemical vapor deposition process, it is described initially every The material of absciss layer is silica.

Figure 13 is please referred to, after forming initial seal coat 208, using the dummy gate structure to be initially isolated described in mask etching Layer 208 forms separation layer 209 up to exposing 203 bottom surface of the first groove.

The separation layer 209 is located in the second fin groove 207,209 side wall of separation layer and 241 side wall of the second side wall It flushes；The separation layer 209 exposes the side of dummy gate structure top surface, the barrier layer 206 exposed in the first groove 203 203 bottom part surfaces of wall and the first groove.

The method for removing the part initial seal coat 208 includes: to be etched back to the initial seal coat 208, exposes puppet 203 bottom part surfaces of gate structure top surface and the first groove；Using the dummy gate structure as exposure mask, etching removal second The initial seal coat 208 of 210 side wall of 241 side wall of side wall and fin forms separation layer 209.

The technique for being etched back to the initial seal coat 208 is anisotropic dry etching, the dry etching parameter packet Include: the gas of use includes CF₄Gas and CHF₃Gas, CF₄The flow of gas is 8sccm~500sccm, CHF₃The stream of gas Amount is 30sccm~200sccm, and chamber pressure is 10mtorr~2000mtorr, and source radio-frequency power is 100W~1300W, biasing Voltage is 80V~500V, and the time is 4 seconds~500 seconds.

In the present embodiment, the technique of the initial seal coat 208 of etching removal 241 side wall of the second side wall and 210 side wall of fin For anisotropic dry etching, the dry etching parameter includes: that the gas of use includes CF₄Gas, CH₂F₂Gas and O₂, CF₄The flow of gas is 30sccm~200sccm, CH₂F₂The flow of gas is 8sccm~50sccm, O₂Flow be 2sccm ~30sccm, chamber pressure be 10mtorr~2000mtorr, source radio-frequency power be 100W~1000W, bias voltage be 30V~ 500V, time are 4 seconds~500 seconds.

In other embodiments, 241 side wall of the second side wall and 210 side wall of fin are removed using isotropic dry etching Initial seal coat 208.

The sidewall locations of second amendment fin layer 214 determine separation layer along parallel with the sidewall locations of the second side wall 241 In the size of orientation, the distance between the gate structure being subsequently formed and source and drain doping layer are also determined.

209 width of separation layer is narrow, is closer between subsequent gate structure and source and drain doping layer, therebetween parasitic electricity Hold larger, spacer width is wide, and farther out, source and drain doping layer answers channel region to distance between gate structure and source and drain doping layer Power is smaller, is unfavorable for performance of semiconductor device.

The separation layer 209 is connected with the second amendment fin 214, and 209 side wall of separation layer is flushed with 206 side wall of barrier layer, It is subsequent in the first groove 203 formed source and drain doping layer 250 after, the separation layer 209 is connected with source and drain doping layer 250, i.e., every Absciss layer 209 is located between source and drain doping layer 250 and the second amendment fin layer 214, and rear extended meeting is in the position of the second amendment fin layer 214 It sets to form gate structure, gate structure is isolated with source and drain doping layer 250 by separation layer 209, and distance increases therebetween, is reduced Parasitic capacitance between gate structure and source and drain doping layer, to optimize the performance of semiconductor devices.

Figure 14 is please referred to, after forming separation layer 209, forms source and drain doping layer 250, the source and drain in the first groove 203 Doped layer 250 has source and drain ion；It is formed after source and drain doping layer 250, in semiconductor substrate 200, fin 210 and dummy grid knot Dielectric layer 230 is formed on structure, dielectric layer 230 covers the dummy gate structure side wall.

The formation process of the source and drain doping layer 250 includes epitaxial growth technology；The doped source and drain in source and drain doping layer 250 The technique of ion is doping process in situ.

When the semiconductor devices is P-type device, the material of the source and drain doping layer includes: silicon, germanium or SiGe；It is described Source and drain ion is P-type ion, and the source and drain ion includes boron ion, BF2- ion or indium ion.When the semiconductor devices is N When type device, the material of the source and drain doping layer includes: silicon, GaAs or indium gallium arsenic；The source and drain ion is N-type ion, institute Stating source and drain ion includes phosphonium ion or arsenic ion.

In the present embodiment, the semiconductor devices is P-type device, and the material of the source and drain doping layer 250 is SiGe, described Source and drain ion is boron ion.In other embodiments, the semiconductor devices is N-type device, the material of the source and drain doping layer 250 For silicon, the source and drain ion is phosphonium ion.In one embodiment, source and drain doping layer is formed using ion implantation technology.

The dielectric layer 230 covers fin 210, source and drain doping layer 250 and dummy gate structure side wall, exposes dummy grid knot Structure top surface.

The forming method of the dielectric layer 230 includes: in source and drain doping layer 250, dummy gate structure, source and drain doping layer 250 Upper formation initial medium layer (not shown), initial medium layer cover the top surface and sidewall surfaces of dummy gate structure；Planarization The initial medium layer forms dielectric layer 230 until exposing the top surface of the protective layer 202 at the top of dummy gate structure.

The material of the dielectric layer 230 includes silica.

Figure 15 is please referred to, after forming dielectric layer 230, removes the second amendment that dummy gate layer 220 and dummy gate layer 220 cover Fin layer 214 is forming grid opening 260 in the dielectric layer 230 and between the first adjacent amendment fin layer 213.

The step of the second amendment fin layer 214 that removal dummy gate layer 220 and dummy gate layer 220 cover includes: that removal is pseudo- Grid layer 220 forms initial grid opening in dielectric layer 230；Remove the second amendment fin layer that initial grid opening exposes 214, make initial grid be open to form the grid opening 260.

It further include the protective layer 202 for removing 220 top of dummy gate layer before removal dummy gate layer 220.

In the present embodiment, the material of the first amendment fin layer 213 is silicon, and the material of the second amendment fin layer 214 is SiGe.The technique for the second amendment fin layer 214 that removal grid opening 260 exposes is dry etch process, and parameter includes: use Total gas include etching gas and diluent gas, etching gas includes HCl, and diluent gas includes N₂, etching gas occupies always The molar percentage of gas is 20%~90%, and temperature is 100 degrees Celsius~200 degrees Celsius.

In removing the dry etch process that the second amendment fin layer 214 that initial grid opening exposes uses, gas is etched Body includes HCl, and the chemical activity of HCl gas is preferable and the reaction rate of the second amendment fin layer 214 is very fast, makes dry etching Technique is bigger relative to the etching selection to the first amendment fin layer 213 to the second amendment fin layer 214.

In the present embodiment, the dry etch process that the second amendment fin layer 214 that initial grid opening exposes uses is removed, Correcting fin layer 214 relative to the etching selection ratio to the first amendment fin layer 213 to second is 50~200.

Figure 16 is please referred to, forms gate structure 270 in grid opening 260, the gate structure 270 surrounds first and repairs Positive fin layer 213.

The gate structure further include: positioned at the boundary layer of the grid open bottom, the gate dielectric layer covers boundary layer.

The gate structure 270 is also located between adjacent first fin layer 211, makes gate structure 270 around first in this way Fin layer 211 increases gate structure 270 to the control ability of channel.

The gate structure 270 includes across the gate dielectric layer (not shown) of fin structure 210 and on gate dielectric layer Gate electrode layer (not shown).The gate dielectric layer is located at the part of the surface of isolation structure 201, covers the first fin layer 211 Atop part surface and partial sidewall surface.Specifically, gate dielectric layer is located at side wall and the bottom of grid opening 260, gate dielectric layer Around the first fin layer 211；Gate electrode layer is located in grid opening 260, and gate electrode layer is also around the first fin layer 211.

The gate structure further include: positioned at the boundary layer of the grid open bottom, the gate dielectric layer covers boundary layer.

Gate dielectric layer material described in the present embodiment is high K medium material (dielectric coefficient is greater than 3.9)；The high K medium Material includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, oxidation Barium titanium, strontium oxide strontia titanium or aluminium oxide.

The material of the boundary layer includes silica.The technique for forming the boundary layer includes oxidation technology.The interface The effect of layer includes: the surface for repairing grid opening 260 bottoms first amendment fin layer 213.

In the present embodiment, further includes: in the technique for be formed boundary layer and after forming the technique of gate dielectric layer material, and It before carrying out forming the material of gate electrode layer, is made annealing treatment, so that boundary layer densifies.The temperature of the annealing At 1000 degrees Celsius or more, such as 1200 degrees Celsius.

The material of the gate electrode layer is metal, and the metal material includes one in copper, tungsten, nickel, chromium, titanium, tantalum and aluminium Kind or multiple combinations.

Correspondingly, the present embodiment also provides a kind of semiconductor devices formed using the above method, comprising: semiconductor substrate 200；Fin 210 in semiconductor substrate 200, the fin 210 include several layers along semiconductor substrate surface normal side Fin layer 213 is corrected to the first of overlapping；Gate structure 270 on the fin 210；The gate structure 270 also position It is corrected between fin layer 213 in adjacent two layers first；Source and drain doping layer in the fin 210 of 270 two sides of gate structure 250, the source and drain doping layer 250 has source and drain ion；Between the first amendment fin layer 213 and source and drain doping layer 250 Barrier layer 206, the material on the barrier layer 206 are semiconductor material, have the first ion in the barrier layer 206, first from The atom gap of son filling 206 material of barrier layer；Positioned at semiconductor substrate 200, fin 210, gate structure 270 and source and drain doping Dielectric layer 230 on layer 250, dielectric layer 230 cover 270 side wall of gate structure and 250 side wall of source and drain doping layer and top surface, Expose 270 top surface of gate structure.

The content of the semiconductor substrate 200 with reference to the foregoing embodiments, is no longer described in detail.

The structure of the gate structure 270 and the content of reference by location previous embodiment, are no longer described in detail.

The material of the source and drain doping layer 250 and the content of reference by location previous embodiment, are no longer described in detail.Although of the invention It discloses as above, but present invention is not limited to this.Anyone skilled in the art are not departing from the spirit and scope of the present invention It is interior, it can make various changes or modifications, therefore protection scope of the present invention should be defined by the scope defined by the claims..