阅读说明：本技术 半导体器件 (Semiconductor devices ) 是由 曹玟锡 李戴晛 李钟汉 朴洪培 李东洙 于 2019-02-26 设计创作，主要内容包括：半导体器件可以包括：从衬底突出的多个第一有源鳍,每个第一有源鳍在第一方向上延伸；从衬底突出的第二有源鳍；以及第一有源鳍上的多个相应的第一鳍式场效应晶体管(FinFET)。每个第一FinFET包括在与第一方向垂直的第二方向上延伸的第一栅结构,并且第一栅结构包括第一栅绝缘层和第一栅电极。第一FinFET形成在衬底的第一区域上,并且具有第一金属氧化物层作为第一栅绝缘层,并且第二FinFET在衬底的第二区域上形成在第二有源鳍上,并且第二FinFET不包括金属氧化物层,而包括第二栅绝缘层,第二栅绝缘层的底表面与第一金属氧化物层的底表面位于同一平面。(Semiconductor devices may include: from substrate multiple first active fins outstanding, and each first active fin extends in a first direction；From substrate the second active fin outstanding；And first multiple corresponding first fin formula field effect transistors (FinFET) in active fin.Each first FinFET includes the first grid structure upwardly extended in the second party vertical with first direction, and the first grid structure includes the first gate insulation layer and first gate electrode.First FinFET is formed on the first area of substrate, and have the first metal oxide layer as the first gate insulation layer, and the 2nd FinFET is formed in the second active fin on the second area of substrate, and the 2nd FinFET does not include metal oxide layer, and it is generally aligned in the same plane including the second gate insulation layer, the bottom surface of the second gate insulation layer and the bottom surface of the first metal oxide layer.)

1. a kind of semiconductor devices, comprising:

From substrate multiple first active fins outstanding, each described first active fin extends in a first direction；

From the substrate the second active fin outstanding；And

Multiple corresponding first fin formula field effect transistor FinFET in first active fin, wherein each described One FinFET includes the first grid structure upwardly extended in the second party intersected with the first direction, and the first grid knot Structure includes the first gate insulation layer and first gate electrode,

Wherein, the first FinFET is formed on the first area of the substrate, and there is the first metal oxide layer to make For first gate insulation layer, and

Wherein, the 2nd FinFET is formed in second active fin on the second area of the substrate, and described second FinFET does not include metal oxide layer, and including the second gate insulation layer, the bottom surface of second gate insulation layer and described the The bottom surface of one metal oxide layer is generally aligned in the same plane.

2. semiconductor devices according to claim 1, wherein the first area includes logic cells area, and institute State at least part that second area includes peripheral region.

3. semiconductor devices according to claim 2, wherein the first area includes logic cells area, Yi Jisuo A part of peripheral region is stated, and the 3rd FinFET with the electrical characteristics different from the 2nd FinFET is further formed In the peripheral region of the first area.

4. semiconductor devices according to claim 3, wherein the 3rd FinFET includes prolonging in this second direction The third grid structure stretched, and the third grid structure includes the second silicon oxide layer, metal oxide layer and third gate electrode, In, side wall and bottom of the metal oxide layer around the third gate electrode, and second silicon oxide layer is described It is contacted below third gate electrode with the metal oxide layer.

5. semiconductor devices according to claim 4, wherein the thickness of second silicon oxide layer is different from being formed described The thickness of first silicon oxide layer of the second gate insulation layer.

6. semiconductor devices according to claim 1, wherein first gate insulation layer is around the first gate electrode Side wall and bottom.

7. semiconductor devices according to claim 1, wherein second active fin extends in said first direction, And the 2nd FinFET is used as I/O device.

8. semiconductor devices according to claim 7, in which:

Each first gate insulation layer in each described first FinFET has first thickness,

2nd FinFET includes the second grid structure extended in this second direction, and second grid structure includes As the first silicon oxide layer and the second gate electrode of second gate insulation layer,

Wherein, for the 2nd FinFET, first silicon oxide layer is made only on the bottom surface of second gate electrode, And

Wherein, the second thickness of first silicon oxide layer is different from the first thickness.

9. semiconductor devices according to claim 8, wherein the first silicon oxide layer of the 2nd FinFET and each The first gate insulation layer in a first FinFET respectively contacts the top surface of corresponding fin, and corresponding in respective contact There is bottom surface coplanar relative to each other in place of fin.

10. semiconductor devices according to claim 7, wherein also being formed on the second area has and described the 3rd FinFET of two FinFET different electrical characteristics, wherein the 3rd FinFET includes third grid structure, the third grid Structure includes the second silicon oxide layer and third gate electrode, wherein the thickness of second silicon oxide layer is different from forming described the The thickness of first silicon oxide layer of two gate insulation layers.

11. a kind of semiconductor devices, comprising:

From the logic cells area of substrate multiple first active fins outstanding, each described first active fin is in a first direction Extend；

Multiple first fin formula field effect transistor FinFET in first active fin, wherein each described first FinFET includes the first grid structure upwardly extended in the second party vertical with the first direction, and first grid structure Including the first gate insulation layer and first gate electrode, first gate insulation layer includes metal oxide layer；

From the peripheral region of the substrate multiple second active fins outstanding, each described second active fin is in the first party It upwardly extends；And

The 2nd FinFET on the first fin in second active fin, wherein the 2nd FinFET is included in described second The second grid structure just upwardly extended, and second grid structure includes the first silicon oxide layer and the second gate electrode, described the One silica layer forms the second gate insulation layer and has the thickness different from the thickness of first gate insulation layer,

Wherein, the metal oxide layer of each first FinFET is adjacent to be formed with each first active fin respectively, and described First silicon oxide layer is adjacent to be formed with the first fin in second active fin.

12. semiconductor devices according to claim 11, wherein first gate insulation layer surrounds the first gate electrode Side wall and bottom.

13. semiconductor devices according to claim 11, wherein first silicon oxide layer is made only in the second gate On the bottom of electrode.

14. semiconductor devices according to claim 11, wherein the first FinFET is logic unit transistor, and And the 2nd FinFET is I/O transistor.

15. semiconductor devices according to claim 11 further includes the 3rd FinFET formed in the peripheral region, 3rd FinFET has the electrical characteristics different from the 2nd FinFET formed in the peripheral region.

16. semiconductor devices according to claim 15, wherein the 3rd FinFET includes grid structure, the grid knot Structure includes the second silicon oxide layer, metal oxide layer and third gate electrode, wherein the metal oxide layer surrounds the third The side wall of gate electrode and bottom, and the thickness of second silicon oxide layer is different from the thickness of first silicon oxide layer.

17. a kind of semiconductor devices, comprising:

From substrate multiple first active fins outstanding, each described first active fin extends in a first direction；

From the substrate multiple second active fins outstanding, each described second active fin extends in said first direction；

Multiple first fin formula field effect transistor FinFET in first active fin；

Multiple 2nd FinFET in second active fin；And

First grid structure upwardly extends in the second party vertical with the first direction and crosses over the multiple first FinFET With the multiple 2nd FinFET, wherein first grid structure include the first gate insulation layer and first gate electrode, described first Gate insulation layer include include metal oxide layer,

Wherein, the 2nd FinFET of the first FinFET and the 2nd FinFET in the first FinFET is direct It is adjacent, and

At the borderline region of one first FinFET and one 2nd FinFET direct neighbor, the metal oxidation Gap is formed in nitride layer.

18. semiconductor devices according to claim 17, wherein the first gate electrode is continuous conductive structure, institute It states continuous conductive structure and one first FinFET is connected to one 2nd FinFET.

19. semiconductor devices according to claim 18, wherein one first FinFET is N-shaped FinFET, and One 2nd FinFET is p-type FinFET, wherein the N-shaped FinFET and p-type FinFET includes the first grid Electrode is as the public first gate electrode extended in this second direction.

20. semiconductor devices according to claim 17, wherein one first FinFET is N-shaped FinFET, and One 2nd FinFET is p-type FinFET, wherein the N-shaped FinFET and p-type FinFET include physically that This separated corresponding first gate electrode and the second gate electrode.

21. on semiconductor devices according to claim 20, including corresponding first gate electrode and the second gate electrode Upper wiring, wherein it is described it is upper wiring corresponding first gate electrode and the second gate electrode are electrically connected to each other.

Technical field

Example embodiment is related to semiconductor devices and its manufacturing method.More specifically, example embodiment is related to including having Semiconductor devices and its manufacturing method including the transistor of various electrical characteristics.

Background technique

Semiconductor devices is formed on substrate, and semiconductor devices includes the transistor with various electrical characteristics.Each It is beneficial that transistor, which is formed by simple technique and has good characteristic,.For example, compared with some I/O devices, it is very thin Gate oxide high performance device can have the gate oxide film of different-thickness.However, because both devices are usually being processed Period is processed simultaneously, so the prior art for being used to form these devices may be complexity, this may generate reliability Adverse effect.

Summary of the invention

Example embodiment provides a kind of semiconductor devices including the transistor with various electrical characteristics.

According to one embodiment, a kind of semiconductor devices includes: from substrate multiple first active fins outstanding each first Active fin extends in a first direction；From substrate the second active fin outstanding；And first in active fin multiple corresponding One fin formula field effect transistor (FinFET).Each first FinFET includes upwardly extending in the second party vertical with first direction The first grid structure, and the first grid structure include the first gate insulation layer and first gate electrode.First FinFET is formed in substrate First area on, and have the first metal oxide layer as the first gate insulation layer, and the 2nd FinFET is in substrate It is formed on second area in the second active fin, and the 2nd FinFET does not include metal oxide layer, and it is exhausted including second gate Edge layer, the bottom surface of the second gate insulation layer and the bottom surface of the first metal oxide layer are generally aligned in the same plane.

According to one embodiment, a kind of semiconductor devices (be can be and semiconductor devices phase described in previous embodiment With semiconductor devices) include: logic cells area multiple first active fins outstanding from substrate, each first active fin exists First party upwardly extends；Multiple first fin formula field effect transistors (FinFET) in first active fin, wherein each first FinFET includes the first grid structure upwardly extended in the second party vertical with first direction, and the first grid structure includes first Gate insulation layer and first gate electrode, the first gate insulation layer include metal oxide layer；It is outstanding multiple from the peripheral region of substrate Second active fin, each second active fin extend in a first direction；And second on second the first fin in active fin FinFET, wherein the 2nd FinFET includes the second grid structure extended in a second direction, and the second grid structure includes first Silicon oxide layer and the second gate electrode, the first silicon oxide layer form the second gate insulation layer and have the thickness with the first gate insulation layer Different thickness.The metal oxide layer of each first FinFET is adjacent to be formed with each first active fin respectively, and the One silica layer is adjacent to be formed with the first fin in the second active fin.

According to one embodiment, a kind of semiconductor devices includes: from substrate multiple first active fins outstanding each first Active fin extends in a first direction；From substrate multiple second active fins outstanding, each second active fin is in a first direction Upper extension；Multiple first fin formula field effect transistors (FinFET) in first active fin；Multiple second in second active fin FinFET；And first grid structure, it is upwardly extended in the second party vertical with first direction and across the multiple first FinFET and the multiple 2nd FinFET, wherein the first grid structure includes the first gate insulation layer and first gate electrode, the first grid Insulating layer includes metal oxide layer.One second of the first FinFET and the 2nd FinFET in first FinFET FinFET direct neighbor, and at the borderline region of this first FinFET and this 2nd FinFET direct neighbor, Gap is formed in metal oxide layer.

Detailed description of the invention

Fig. 1, Fig. 2 and Fig. 3 are the plan view and cross-sectional view for showing semiconductor devices according to example embodiment；

Fig. 4 to Figure 20 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure；

Figure 21 and Figure 22 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment；

Figure 23 and Figure 24 is the cross-sectional view for showing semiconductor devices according to example embodiment；

Figure 25 and Figure 26 is the cross-sectional view for showing semiconductor devices according to example embodiment；

Figure 27 and Figure 28 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment；

Figure 29 to Figure 38 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure；

Figure 39 and Figure 40 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment；

Figure 41 to Figure 44 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure；

Figure 45 and Figure 46 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment；And

Figure 47 to Figure 50 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure.

Specific embodiment

According to the detailed description below in conjunction with attached drawing, exemplary embodiment will be more clearly understood.

Fig. 1, Fig. 2 and Fig. 3 are the plan view and cross-sectional view for showing semiconductor devices according to example embodiment.

Fig. 2 includes the cross-sectional view of the line A-A ' and line B-B ' interception in Fig. 1.Fig. 3 include line C-C ' in Fig. 1 and The cross-sectional view of line D-D ' interception.

In Fig. 1, some elements such as spacer (spacer) is omitted.Fig. 1 shows in plan view gate electrode and metal Oxide pattern.

Referring to figs. 1 to Fig. 3, substrate 100 may include first area R1 and second area R2.Including with high dielectric constant Metal oxide layer including the first transistor can be formed on the first area R1 of substrate 100.Second transistor can be with Without metal oxide layer, and can be formed on the second area R2 of substrate 100.

In the exemplary embodiment, first area R1 can be logic cells area, and second area R2 can be external zones Domain.For example, logic unit transistor with high performance can be formed on the R1 of first area, and can be in second area R2 It is upper to form the I/O transistor for being used as I/O (input/output) device.In the exemplary embodiment, the first transistor can have than The lower operating voltage of two-transistor and faster speed.For example, I/O transistor can be input buffer or I/O driver A part, and logic unit transistor can be the AND gate or "or" of the logic circuit such as core devices of logic chip A part of door.I/O transistor and logic unit transistor can be the semiconductor of such as logic chip or memory device etc A part of device.In the exemplary embodiment, each of the first transistor and second transistor may include fin field effect Answer transistor (FinFET).

The first transistor can be formed on the first active patterns 101a projected upwards from the upper surface of substrate 100.The One transistor may include the first grid structure 140a upwardly extended in the side intersected with the first active patterns 101a.First interval Object 110a can be formed on the side wall of the first grid structure 140a.

Second transistor can be formed on the second active patterns 101b projected upwards from the upper surface of substrate 100.The Two-transistor may include the second grid structure 140b upwardly extended in the side intersected with the second active patterns 101b.Second interval Object 110b can be formed on the side wall of the second grid structure 140b.

Substrate 100 may include the III- such as the semiconductor material such as silicon, germanium, silicon-germanium such as GaP, GaAs, GaSb V race semiconducting compound.In some embodiments, substrate 100 can be silicon-on-insulator (SOI) substrate or germanium on insulator (GOI) substrate.

First active patterns 101a can be upwardly extended in the first party substantially parallel with the upper surface of substrate 100.First Active patterns 101a can be arranged in the second direction intersected with first direction.Second active patterns 101b can be in first party It upwardly extends.Second active patterns 101b can be arranged in a second direction.But the present disclosure is not limited thereto.For example, second has Source pattern 101b can be upwardly extended in the side for being different from first direction.In the exemplary embodiment, first direction and second direction It can be substantially perpendicular to each other.The terms used herein example when being related to direction, layout, position, shape, size, amount or other measurements As " parallel ", " vertical ", " identical ", " equal ", " plane " or " coplanar " do not necessarily mean that identical direction, layout, position, Shape, size, amount or other measurements, and be intended in the acceptable variation that is included in and may for example occur due to manufacturing process Almost the same direction, layout, position, shape, size, amount or other measurement.Unless context or other statements separately have Bright, otherwise term " substantially " can be used for emphasizing the meaning herein.For example, being described as " substantially parallel ", " basic It is upper vertical ", " substantially the same ", " being essentially equal " or " substantially planar " item can be substantially parallel, be vertical, is identical, It is equal or plane, or can be parallel, vertical, phase in the acceptable variation that may for example occur due to manufacturing process It is same, equal or plane.

Separation layer 104 can fill the lower part of the groove between the first active patterns 101a.Separation layer 104 may include oxygen Compound, such as silica.The part that first active patterns 101a is not isolated the covering of layer 104 can be referred to as the first active fin 102a is used as active area.First active fin 102a can have the first width W1 in a second direction.First active fin 102a Between gap can have first distance D1 in a second direction.

Separation layer 104 can fill the lower part of the groove between the second active patterns 101b.Second active patterns 101b is not The part for being isolated the covering of layer 104 can be referred to as the second active fin 102b, be used as active area.Second active fin 102b can be with There is the second width W2 greater than the first width W1 in a second direction.Gap between second active fin 102b can be second There is the second distance D2 greater than first distance D1 on direction.

The first interlayer insulating film can be formed on the first active fin 102a and the second active fin 102b and separation layer 104 112.The upper surface of first interlayer insulating film 112 can be substantially flat.

First interlayer insulating film 112 may include silica.It the upper surface of first interlayer insulating film 112 can be with the first grid The upper surface of structure 140a and the second grid structure 140b are coplanar.

First opening can extend through the first interlayer insulating film 112.The side wall of first active fin 102a and upper surface with And separation layer 104 can be exposed by the first opening relative to the first interlayer insulating film 112.First opening can be in a second direction Extend.

First grid structure 140a can be formed in the first opening.In the exemplary embodiment, the first grid structure 140a can be with Extend in a second direction to intersect with multiple first active fin 102a.First grid structure 140a can have in a first direction Third width W3.

First grid structure 140a may include metal oxide pattern 126a, the first gate electrode 130a that sequence stacks and the One capping pattern 132a.

Metal oxide pattern 126a may include the dielectric constant high dielectric constant material higher than the dielectric constant of silica Material.According to embodiment, the dielectric constant of high dielectric constant material can be higher than the dielectric constant of silicon nitride.High dielectric constant material It may include such as hafnium oxide (HfO₂), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂) etc..Metal oxide pattern 126a can have There is first thickness.First thickness can be aboutTo aboutIt can threshold voltage according to the first transistor and work Voltage selects first thickness.

First gate electrode 130a may include metal or metal nitride.In the exemplary embodiment, first gate electrode 130a It may include such as Ti, TiN, Ta, TaN, TiAlC, TiAlCN, TiAlSiCN, Co or W.For example, first gate electrode 130a can To include the lower layer stacked and upper layer.Lower layer may include selected from the group being made of Ti, TiN, Ta, TaN and TiAlC, TiAlCN At least one of, and upper layer may include Co or W.Lower layer may be used as the layer for control threshold voltage.It can basis The threshold voltage of the first transistor selects lower layer.

Metal oxide pattern 126a can surround side wall and the bottom of first gate electrode 130a.

It in the exemplary embodiment, can be enterprising on the surface of the first active fin 102a below metal oxide pattern 126a One step forms pad oxide skin(coating) (not shown).Padding oxide skin(coating) may include thermal oxide layer.

First capping pattern 132a can be formed on first gate electrode 130a, and can fill the residue of the first opening Part.First capping pattern 132a may include such as silicon nitride, silicon oxynitride.

First spacer 110a can be formed on the side wall of the first grid structure 140a.In the exemplary embodiment, between first Parting 110a may include silicon nitride.

In the exemplary embodiment, impurity range (not shown) can be formed in adjacent with the side wall of the first grid structure 140a At one active fin 102a.Impurity range may be used as source/drain region.In some example embodiments, can with the first grid structure It is further formed extension pattern (not shown) between the first adjacent active fin 102a of the side wall of 140a, and extension can be passed through Pattern connects the first active fin 102a.Impurity range can be further formed in extension pattern.

Second opening can extend through the first interlayer insulating film 112.The side wall of second active fin 102b and upper surface with And separation layer 104 can be exposed by the second opening.Second opening can extend in a second direction.

Second grid structure 140b can be formed in the second opening.In the exemplary embodiment, the second grid structure 140b can be with Extend in a second direction to intersect with multiple second active fin 102b.Second grid structure 140b can have in a first direction Greater than the 4th width W4 of third width W3.

Second grid structure 140b may include the first silicon oxide layer 120, the second gate electrode 130b and second that sequence stacks Cover pattern 132b.

First silicon oxide layer 120 can have the second thickness of the first thickness greater than metal oxide pattern 126a.It can To select second thickness according to the threshold voltage of second transistor and operating voltage.From the above discussion, each first The metal oxide pattern 126a of FinFET can formation adjacent with each first active fin 102a respectively, and in some implementations Each first active fin 102a can be contacted respectively in example, and the first silicon oxide layer 120 can in the second active fin 102b The adjacent formation of the first fin, and the first fin in the second active fin 102b can be contacted in some embodiments.

Second gate electrode 130b may include metal or metal nitride.Second gate electrode 130b may include Ti, TiN, Ta, TaN, TiAlC, TiAlCN, TiAlSiCN, Co or W etc..Second gate electrode 130b may include and first gate electrode 130a Material essentially identical material or material composition.

First silicon oxide layer 120 can be formed in the bottom part down of the second gate electrode 130b, and in some embodiments, First silicon oxide layer 120 is not formed on the side wall of the second gate electrode 130b.In some embodiments, the first silicon oxide layer 120 Do not surround or contact the side wall of the second gate electrode 130b.First silicon oxide layer 120 can contact the bottom of the second gate electrode 130b. For example, as shown in Fig. 2, not forming metal oxide layer on the first silicon oxide layer 120.Therefore, the grid of second transistor are exhausted Edge layer can not have metal oxide layer.For contacting here depicted as " contacting " each other or the element of " being in contact " Intermediary element is not present at point or tie point.Therefore, " contact " is referred to being directly connected to or be touched.

Second capping pattern 132b can be formed on the second gate electrode 130b, and can fill the residue of the second opening Part.Second capping pattern 132b may include such as silicon nitride, silicon oxynitride.Second capping pattern 132b may include with The material of first capping pattern 132a essentially identical material or material composition.

Second spacer 110b can be formed on the side wall of the second grid structure 140b.In the exemplary embodiment, between second Parting 110b includes silicon nitride.

In the exemplary embodiment, impurity range (not shown) can be formed in adjacent with the side wall of the second grid structure 140b At two active fins.Impurity range may be used as source/drain region.

As described above, metal oxide layer can be formed on the R1 of first area, and metal oxide layer may be used as The gate insulation layer of the first transistor.Metal oxide layer can not be formed on second area R2.First silicon oxide layer can be with shape At on second area R2, and the first silicon oxide layer may be used as the gate insulation layer of second transistor.In this way, by The first gate insulation layer that one material (for example, metal oxide) is formed can be formed on the first area of semiconductor devices, and And the second gate insulation layer formed by the second material (for example, silica) can be with vertical level identical with the first gate insulation layer It is formed on the second area of semiconductor devices.First gate insulation layer (for example, 126a) can have than the second gate insulation layer (example Such as, 120) thin thickness (for example, vertical thickness).Identical semiconductor devices (such as formed on the tube core from chip Semiconductor chip) it can be at two different horizontal separation regions with the gate insulation layer of the two different-thickness.Therefore, may be used To reduce the leakage current and reliability failure of the second transistor generated by the metal oxide layer stayed on the first silicon oxide layer.

Fig. 4 to Figure 20 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure.

Fig. 7, Fig. 8, Figure 10, Figure 11, Figure 13, Figure 15, Figure 17, Figure 18 and Figure 20 are the edges in first area and second area The cross-sectional view of first direction interception.Fig. 5, Figure 12, Figure 14, Figure 16 and Figure 19 are in first area and second area along second The cross-sectional view of direction interception.

Referring to Fig. 4 and Fig. 5, the top of substrate 100 can be partly etched to form first groove at the R1 of first area And second groove is formed at second area R2.It, can be the when forming first groove at substrate 100 and when second groove Multiple first active patterns 101a are formed on one region R1, and multiple second active patterns can be formed on second area R2 101b.Each of first active patterns 101a and the second active patterns 101b can extend in a first direction.

Separation layer 104 can be formed to fill the lower part of first groove and second groove.

In the exemplary embodiment, the first active patterns 101a may be used as by the part that separation layer exposes in the R1 of first area First active fin 102a.First active fin 102a can have the first width W1 in a second direction.First active fin 102a it Between gap can have first distance D1 in a second direction.Gap between first active fin 102a can correspond to first Groove.

In the exemplary embodiment, the second active patterns 101b may be used as by the part that separation layer exposes in second area R2 Second active fin 102b.Second active fin 102b can have the second width W2 greater than the first width W1 in a second direction. Gap between second active fin 102b can have the second distance D2 greater than first distance D1 in a second direction.Second has Gap between the fin 102b of source can correspond to second groove.

Referring to figure 6 and figure 7, can be formed on the first active fin 102a and separation layer 104 includes the first of sequence stacking The first illusory grid structure 106 including illusory insulating pattern 106a, the illusory mask 106c of the first dummy gate electrode 106b and first. Can be formed on the second active fin 102b and separation layer 104 includes the second illusory insulating pattern 108a sequentially stacked, second The second illusory grid structure 108 including the illusory mask 108c of dummy gate electrode 108b and second.First illusory grid structure 106 and Two illusory grid structures 108 can be stacked by identical material layer and be formed by identical technique.

The first spacer 110a can be formed on the side wall of the first illusory grid structure 106.It can be in the second illusory grid knot The second spacer 110b is formed on the side wall of structure 108.In the exemplary embodiment, the first spacer 110a and the second spacer 110b It may include such as silicon nitride, silicon oxynitride.

In the exemplary embodiment, the first illusory grid structure 106 can extend in a second direction with it is multiple first active Fin 102a intersects.Multiple first illusory grid structures 106 can be separated from each other in a first direction.First illusory grid structure 106 There can be third width W3 in a first direction.

In the exemplary embodiment, the second illusory grid structure 108 can extend in a second direction with it is multiple second active Fin 102b intersects.Multiple second illusory grid structures 108 can be separated from each other in a first direction.Second illusory grid structure 108 There can be the 4th width W4 greater than third width W3 in a first direction.

Referring to Fig. 8, initial interlayer insulating film can be formed to fill the gap and second between the first illusory grid structure 106 Gap between illusory grid structure 108.Initial interlayer insulating film can cover the first illusory grid structure 106 and the second illusory grid knot Structure 108.The first initial interlayer insulating film can be planarized, until exposing the first dummy gate electrode 106b and the second dummy gate electrode The upper surface of 108b.That is, the first illusory illusory mask of mask 106c and second can be removed by flatening process 108c。

The top of initial interlayer insulating film can be removed partly to form the first interlayer insulating film 112.It can be first It is formed on interlayer insulating film 112 recessed.It can form that mask layer is recessed to fill, and the top of mask layer can be planarized, Upper surface until the first dummy gate electrode 106b and the second dummy gate electrode 108b can be exposed.Therefore, mask pattern 114 can To be formed on the first interlayer insulating film 112.

With reference to Fig. 9 and Figure 10, the first illusory grid structure 106 can be removed to form the first opening 116a.Can be removed Two illusory grid structures 108 are to form the second opening 116b.

First active fin 102a and separation layer 104 can be exposed by the first opening 116a (for example, multiple first can be formed Opening).Second active fin 102b and separation layer 104 (can be opened by the second opening 116b exposing for example, multiple second can be formed Mouthful).

1 and Figure 12 referring to Fig.1, can be in the first active fin 102a exposed by the first opening 116a and the second opening 116b With the first silicon oxide layer 120 is formed on the second active fin 102b.First silicon oxide layer 120 can be formed to have second thickness. First silicon oxide layer 120 may be used as the gate insulation layer of second transistor.

In the exemplary embodiment, the first silicon oxide layer 120 may include by active to the first active fin 102a and second The silicon of fin 102b is aoxidized and the thermal oxide that is formed.Therefore, the first silicon oxide layer 120 can be made only in the first active fin On the surface of 102a and the second active fin 102b.In the exemplary embodiment, the first silicon oxide layer 120 can pass through wet treatment process It is formed.

It in the side wall of the first opening 116a and the second opening 116b, the first silicon oxide layer 120, separation layer 104 and can cover Hard mask layer 122 is conformally formed on mould pattern 114.Hard mask layer 122 can protect the first silicon oxide layer 120.Therefore, it covers firmly Mold layer 122 can be formed to have the material for having high etch-selectivity relative to the first silicon oxide layer 120.In example embodiment In, hard mask layer 122 may include such as titanium oxide.

3 and Figure 14 referring to Fig.1 for example can form the first photoresist layer by spin coating proceeding on hard mask layer 122.It can To pattern the first photoresist layer by photoetching process, to form the first photoresist of the second area R2 of covering substrate 100 Pattern 124.

The hard mask layer that the first photoetching agent pattern 124 comes as etching mask on the R1 of sequential etch first area can be used 122 and first silicon oxide layer 120.Etch process may include wet etching process.

By executing etch process, the surface of the first active fin 102a is exposed by the first opening 116a.It is lost when executing wet process When carving technology, the hard mask layer 122 and the first silicon oxide layer 120 on the R1 of first area are removed, while reducing by the first active fin The damage on the surface of 102a.

5 and Figure 16 referring to Fig.1 can aoxidize the surface by the first opening 116a the first active fin 102a exposed to be formed Pad oxide skin(coating) (not shown).

Metal oxidation is conformally formed in the whole surface for the layer that can expose in first area R1 and second area R2 Nitride layer 126.For example, metal oxide layer 126 can be formed in the side wall of the first opening 116a, pad oxygen in the R1 of first area The upper surface (or if without using oxide skin(coating), the upper surface of the first active fin 102a is padded) of compound layer and mask pattern On 114 upper surface, and the side wall of the first opening 116a can be contacted, the upper surface of padding oxide skin(coating) (or if does not make With pad oxide skin(coating), the then upper surface of the first active fin 102a) and mask pattern 114 upper surface.In second area R2, gold Belonging to oxide skin(coating) 126 can be formed on hard mask layer 122 and contact hard mask layer 122.

Metal oxide layer 126 can be formed to have the first thickness of the second thickness less than the first silicon oxide layer 120, First silicon oxide layer 120 is used as the gate insulation layer of second transistor.For example, first thickness and second thickness can refer to for example in gold In place of the top surface of each fin of category each of oxide skin(coating) 126 and the first silicon oxide layer 120 contact in the vertical direction Thickness, and in place of the sidewall surfaces that each of metal oxide layer 126 and the first silicon oxide layer 120 contact each fin Thickness on the direction vertical with the side surface of each fin.In the top surface of each first active fin 102a and the second active fin 102b Place, metal oxide layer 126 and the first silicon oxide layer 120 can have the coplanar bottom being in contact to the top surface of each corresponding fin Surface, and extend certain height above each corresponding fin, wherein the height of the first silicon oxide layer 120 is greater than metal oxygen The height of compound layer 126.Metal oxide layer 126 may include such as hafnium oxide (HfO₂), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂) etc..Metal oxide layer 126 can be for example, by chemical vapor deposition (CVD) technique or atomic layer deposition (ALD) Technique is formed.Metal oxide layer 126 may be used as the gate insulation layer of the first transistor.

Referring to Fig.1 7, the second photoresist layer can be for example formed on metal oxide layer by spin coating proceeding.It can lead to Photoetching process is crossed to pattern the second photoresist layer, to form the second photoetching agent pattern of the first area R1 of covering substrate 100 128。

The second photoetching agent pattern 128 can be used as etching mask etch the metal oxide layer on second area R2 126.In the exemplary embodiment, etch process may include dry method etch technology.

With reference to Figure 18 and Figure 19, the second photoetching agent pattern 128 can be used as etching mask and carry out etch hard mask layer 122.In the exemplary embodiment, the etch process of hard mask layer 122 may include wet etching process.Although in wet etching work Metal oxide layer 126 is partially remaining on hard mask layer 122 before skill, but in the wet etching process of hard mask layer 122 Period can remove metal oxide layer 126 together.Therefore, metal oxide layer 126 can be removed from second area R2.

Therefore, metal oxide layer 126 can be formed in side wall and the bottom of the first opening 116a in the R1 of first area On, and the first silicon oxide layer 120 can be formed on the bottom of the second opening 116b in second area R2.

Then the second photoetching agent pattern 128 can be removed.

With reference to Figure 20, gate electrode layer can be formed to fill the opening of the first opening 116a and second 116b.Gate electrode layer can With coverage mask pattern 114.Upper surface of the gate electrode layer until exposing the first interlayer insulating film 112 can be planarized.Mask artwork Case 114 can also be removed by the flatening process.Therefore, the first initial gate electrode 129a can be formed in the first opening 116a In, and the second initial gate electrode 129b can be formed in the second opening 116b.

Gate electrode layer may include metal or metal nitride.In the exemplary embodiment, gate electrode layer may include for example Ti, TiN, Ta, TaN, TiAlC, TiAlCN, TiAlSiCN, Co or W etc..For example, gate electrode layer may include stack lower layer and Upper layer.Lower layer may include being selected from by least one of Ti, TiN, Ta, TaN and TiAlC, TiAlCN group formed, and on Layer may include Co or W.Lower layer can be selected according to the threshold voltage of the first transistor.

First initial gate electrode 129a can contact metal oxide layer 126.Second initial gate electrode 129b can be contacted First silicon oxide layer 120.

Referring again to Fig. 1 to Fig. 3, the top of the first initial initial gate electrode 129b of gate electrode 129a and second can be removed To be respectively formed first gate electrode 130a and the second gate electrode 130b.First gate electrode 130a can be formed in the first opening 116a In, and the second gate electrode 130b can be formed in the second opening 116b.The top of metal oxide layer 126 can also be removed To form metal oxide pattern 126a.

Capping layer can be formed on first gate electrode 130a, the second gate electrode 130b and the first interlayer insulating film 112, with The first opening 116a of filling and the second opening 116b.Capping layer can be planarized, until exposing the upper of the first interlayer insulating film 112 Surface is to form the capping of the first capping pattern 132a and second pattern 132b.First capping pattern 132a can be formed in the first grid It on electrode 130a, can also be formed on metal oxide pattern 126a, and the second capping pattern 132b can be formed in the On two gate electrode 130b.First capping pattern 132a and the second capping pattern 132b may include such as silicon nitride, silicon oxynitride.

Therefore, metal oxide pattern 126a, the first gate electrode 130a and the first capping pattern stacked including sequence The first grid structure 140a including 132a can be formed on the first area R1 of substrate 100.The first oxygen stacked including sequence The second grid structure 140b including SiClx layer 120, the capping of the second gate electrode 130b and second pattern 132b can be formed in substrate On 100 second area R2.

As described above, the second grid structure of second transistor can not include metal oxide on the first silicon oxide layer Layer.As a result, the 2nd FinFET is formed on the second active fin 102b on the second area R2 of substrate 100, the second of substrate 100 The first area R1 horizontal separation of region R2 and substrate 100, and the 2nd FinFET does not include metal oxide layer, and including grid Insulating layer (for example, first silicon oxide layer 120), the bottom surface of the gate insulation layer and the first metal oxide layer 126 are (for example, gold Belong to oxide pattern 126a) bottom surface be generally aligned in the same plane.It is thereby possible to reduce the leakage current and reliability of second transistor Failure.

Figure 21 and Figure 22 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment.

In Figure 21, some elements such as spacer is omitted.Figure 21 shows in plan view gate electrode and metal oxide Pattern.

In addition to be used as I/O device third transistor other than, semiconductor devices shown in Figure 21 can with referring to figs. 1 to figure Semiconductor devices shown in 3 is essentially identical.Third transistor can have operating voltage more higher than the first transistor and lower Speed.Third transistor can be FinFET.

The first transistor can with referring to figs. 1 to Fig. 3 shown in the first transistor it is essentially identical.Second transistor can be with Second transistor shown in referring to figs. 1 to Fig. 3 is essentially identical.

With reference to Figure 21 and Figure 22, third transistor can be formed in peripheral region.Third transistor can not have gold Belong to oxide skin(coating), therefore can have in no metal oxide and the gate insulation without being formed in the case where high dielectric constant Layer.Therefore, third transistor can be formed in second area R2.

Specifically, multiple third active fin 102c can be projected upwards from the upper surface of substrate 100, and can be first Side upwardly extends.Separation layer 104 can fill the gap between third active fin 102c.Third grid structure 140c can be formed in On third active fin 102c, and it can extend in a second direction.Third spacer 110c can be formed in third grid structure On the side wall of 140c.Although it should be understood that term " first ", " second ", " third " etc. can be used herein to describe various members Part, component, regions, layers, and/or portions, but these elements, component, regions, layers, and/or portions should not be limited by these terms System.Unless otherwise indicated by context, otherwise for example as naming convention, these terms are only used to by element, component, an area Domain, layer or part are distinguished with another element, component, region, layer or part.Therefore, below in a part of specification The first element of discussion, component, region, layer or part can be named as the in another part of claim or specification Two element, component, region, layer or part, without departing from the teachings of the present invention.In addition, in some cases, even if in specification In without usings " first ", " second " etc. carrying out Terminology, the term in the claims still can referred to as " first " or " second ", so that claimed different elements are distinguished from each other out.

First interlayer insulating film 112 can cover third active fin 102c and separation layer 104.Third opening can extend through The first interlayer insulating film 112 is crossed, to expose upper surface and side wall and the separation layer 104 of third active fin 102c.Third opening It can extend in a second direction.

Third grid structure 140c can be formed in third opening.In the exemplary embodiment, third grid structure 140c can be with The second silicon oxide layer 121, third gate electrode 130c and the third stacked including sequence covers pattern 132c.Second silicon oxide layer 121 thickness can be different from the thickness of the first silicon oxide layer 120.In the exemplary embodiment, the thickness of the second silicon oxide layer 121 It can be bigger than the thickness of the first silicon oxide layer 120.

As described above, the gate insulation layer for the second transistor and third transistor being formed in peripheral region can not include Metal oxide layer.For example, can include on gate insulation layer during the process of manufacture second transistor and third transistor Metal oxide layer, but metal oxide layer can be removed as a part of of technique so that the second transistor of completion and Third transistor does not include a part of metal oxide layer as gate insulation layer.

Third transistor can be formed together by forming the technique of the first transistor and second transistor.However, second Silicon oxide layer different terrain can become than the first silica thickness in the second opening in third opening.For example, above Referring to Fig.1 in the technique shown in 1 and 12, when the first silicon oxide layer 120 is formed to have second thickness, photoresist can be formed Pattern covers part corresponding with second transistor in first area R1 and second area R2, while exposing second area R2 In part corresponding with third transistor.It is then possible to exposed division corresponding with third transistor in second area R2 Divide and further aoxidized, to form the second silicon oxide layer 121.Later, photoetching agent pattern can be removed.Technique can institute as above It states and continues.

Figure 23 and Figure 24 is the cross-sectional view for showing semiconductor devices according to example embodiment.

Other than being used as the gate insulation layer structure of third transistor of I/O device, semiconductor shown in Figure 23 and Figure 24 Device can be essentially identical with the semiconductor devices referring to shown in Figure 21 and Figure 22.

The first transistor can with referring to figs. 1 to Fig. 3 shown in the first transistor it is essentially identical.Second transistor can be with Second transistor shown in referring to figs. 1 to Fig. 3 is essentially identical.

With reference to Figure 23 and Figure 24, third transistor can be formed in peripheral region.Third transistor may include having The upper metal oxide layer 127a of high dielectric constant.Therefore, the region for forming third transistor can correspond to first area R1. In this way, in some embodiments, a part of of first area R1 can be in peripheral region.

In the exemplary embodiment, the third grid structure 141c of third transistor includes the second silicon oxide layer that sequence stacks 121, upper metal oxide layer 127a, third gate electrode 130c and third cover pattern 132c.

Second silicon oxide layer 121 can be formed in below third gate electrode 130c.Second silicon oxide layer 121 can not surround The side wall of third gate electrode 130c.Upper metal oxide layer 127a can be formed in the side wall and the second silicon oxide layer of third opening On 121 upper surface.Upper metal oxide layer 127a can surround side wall and the bottom of third gate electrode 130c.

The thickness of second silicon oxide layer 121 can be different from the thickness of the first silicon oxide layer 120.In the exemplary embodiment, The thickness of second silicon oxide layer 121 is bigger than the thickness of the first silicon oxide layer 120.

Upper metal oxide layer 127a may include basic with the material of the metal oxide pattern 126a of the first transistor Identical material.The thickness of upper metal oxide layer 127a can be with the thickness of the metal oxide pattern 126a of the first transistor It is essentially identical.

For example, the second silicon oxide layer 121 can be such as the formation above by reference to as described in Figure 21 and Figure 22.In addition, above by reference to In technique shown in Figure 13 and 14, the first photoetching agent pattern 124 can be formed as not only covering second area R2, also cover first Part corresponding with third transistor in the R1 of region, allows to leave the second silicon oxide layer 121.It is then possible to from first The further etch hard mask layer 122 in part corresponding with third transistor in the R1 of region.Technique can continue as described above into Row.

Figure 25 and Figure 26 is the cross-sectional view for showing semiconductor devices according to example embodiment.

Other than the gate insulation layer structure of the gate insulation layer structure of second transistor and third transistor, Figure 25 and Figure 26 Shown in semiconductor devices can with it is essentially identical referring to figs. 1 to semiconductor devices shown in Fig. 3.The semiconductor devices can be with class Semiconductor devices shown in Figure 23 and 24 is similar to manufacture.

The first transistor can with it is essentially identical referring to figs. 1 to the first transistor shown in Fig. 3.Second transistor and third Transistor can be formed in peripheral region.

In the exemplary embodiment, the second grid structure 141b of second transistor may include the first silica that sequence stacks Layer 120, upper metal oxide layer 127b, the capping of the second gate electrode 130b and second pattern 132b.The gate insulation of second transistor Layer may include upper metal oxide layer 127b.Therefore, the region for forming second transistor can correspond to first area R1.With This mode, in some embodiments, a part of of first area R1 can be in peripheral region.

Upper metal oxide layer 127b can surround side wall and the bottom of the second gate electrode 130b.First silicon oxide layer 120 Can on the second gate electrode 130b lower contact metal oxide layer 127b.First silicon oxide layer 120 can not surround second The side wall of gate electrode 130b.Upper metal oxide layer 127b may include and the metal oxide pattern 126a in the R1 of first area The essentially identical material of material.The thickness of upper metal oxide layer 127b can be with the metal oxide figure in the R1 of first area The thickness of case 126a is essentially identical.

In the exemplary embodiment, the third grid structure 140c of third transistor may include the second silica that sequence stacks Layer 121, third gate electrode 130c and third cover pattern 132c.The thickness of second silicon oxide layer 121 can be with the first silica The thickness of layer 120 is different.In the exemplary embodiment, the thickness of the second silicon oxide layer 121 can be thicker than the first silicon oxide layer 120 Degree is big.The gate insulation layer of third transistor can not have metal oxide layer.

Figure 27 and Figure 28 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment.

Figure 27 and Figure 28 shows the high-performance transistor formed in logic cells area.I/O device in peripheral region The structure of part can be unrestricted, therefore I/O device is not shown in Figure 27 and Figure 28.In the exemplary embodiment, peripheral region In I/O device structure can with reference to I/O device shown in FIG. 1 structure it is essentially identical.In some example embodiments, The structure of I/O device in peripheral region can be essentially identical with the structure of the third transistor referring to shown in Figure 26.

Figure 27 shows in plan view gate electrode and metal oxide layer.Figure 28 includes that the line E-E ' in Figure 27 is intercepted Cross-sectional view.

With reference to Figure 27 and Figure 28, N-type transistor and P-type transistor can be formed in the logic cells area of substrate 100. N-type transistor can be formed in n-type region N, and P-type transistor can be formed in p-type area P.

In the plan view, n-type region N and p-type area P can be arranged in a second direction, and can be in contact with each other.Example Such as, p-type area P may be positioned such that horizontally adjacent with n-type region N.Boundary I between n-type region N and p-type area P can be One side upwardly extends.In the exemplary embodiment, n-type region N and p-type area P are alternately repeated arrangement in a second direction.

In n-type region N, multiple n-type transistors can be arranged in a second direction.In the exemplary embodiment, second The gate electrode structure of adjacent n-type transistor can be separated from each other on direction.The disconnection of gate electrode structure in n-type region N Part is properly termed as first grid cutting region C1.First grid cutting region C1 can extend in a first direction.

Similarly, in p-type area, multiple p-type transistors can be arranged in a second direction.In the exemplary embodiment, The gate electrode structure of adjacent p-type transistor can be separated from each other in a second direction.Gate electrode structure in p-type area P Breaking part be properly termed as second grid cutting region C2.Second grid cutting region C2 can extend in a first direction.

Can be formed on substrate 100 the multiple first active fin 202a and 202b extended in a first direction and with The gate electrode structure that the vertical second party of first direction is upwardly extended to intersect with the first active fin 202a and 202b.It can be in grid The first spacer (not shown) is formed on the side wall of electrode structure 232.

First active fin 202a and 202b can be formed in each of p-type area and n-type region, and can wrap Include the first n active fin 202a and the first p active fin 202b.First n active fin 202a can be in n-type region N, and can use Make the active area of n-type transistor.First p active fin 202b can be in p-type area P, and may be used as having for p-type transistor Source region.Separation layer 104 can fill the gap between the first active fin 202a and 202b.

The first interlayer insulating film (not shown) can be formed on the first active fin 202a and 202b and separation layer 104. First opening can pass through the first interlayer insulating film and be formed, and extend in a second direction.First opening is in a second direction Marginal portion can be located at first grid cutting region C1 and second grid cutting region C2.

It can be formed on separation layer 104 corresponding with first grid cutting region C1 and second grid cutting region C2 exhausted Edge pattern 210.Insulating pattern 210 can extend in a first direction.

First metal oxide layer 214a can be formed in by first opening expose the first n active fin 202a surface, Separation layer 104 between first n active fin 202a and on the first side wall of insulating pattern 210.Second metal oxide layer 214b can be formed in the isolation between the surface of the first p active fin 202b exposed by the first opening, the first p active fin 202b In the second sidewall of layer 104 and insulating pattern 210.First metal oxide layer 214a may include and the second metal oxide The essentially identical material of the material of layer 214b.

In the first opening, the first metal oxide layer 214a and the second metal oxide layer 214b can be not formed in n On boundary I between type region and p-type area.For example, the part in second direction between n-type transistor and p-type transistor can For use as the metal oxide layer absent region R3 for not forming metal oxide layer.It the upper surface of separation layer 104 can be in gold Belong to and exposing at the R3 of oxide skin(coating) absent region.

Gate electrode structure 232 can be formed in the first opening, and can cover the first metal oxide layer 214a, Separation layer between two metal oxide layer 214b and the first metal oxide layer 214a and the second metal oxide layer 214b 104.Gate electrode structure 232 can extend in a second direction to intersect with n-type region and p-type area.Gate electrode structure 232 can For use as the public grid of n-type transistor and p-type transistor.That is, the grid of n-type transistor and p-type transistor can be with It is electrically connected to each other (for example, directly electrical connection).

In the exemplary embodiment, the gate electrode structure 232 in n-type region may include the threshold for controlling n-type transistor Threshold voltage, the first metal layer 226a directly contacted with the first metal oxide layer 214a.Gate electrode structure in p-type area 232 may include the second gold medal for controlling the threshold voltage of p-type transistor, directly contacting with the second metal oxide layer 214b Belong to layer 226b.In the exemplary embodiment, the gate electrode structure in n-type region and p-type area can include upper conductive pattern jointly 228 and capping pattern 230.Therefore, as shown, the first FinFET in first group of FinFET in n-type region can be with p-type The 2nd FinFET direct neighbor in second group of FinFET in region, and in the first FinFET and the 2nd direct phase of FinFET At adjacent borderline region, gap is formed in metal oxide layer (for example, forming the metal oxide layer 214a of two separation And 214b).

The first metal layer 226a may include metal of the work function for the threshold voltage of n-type transistor.Second metal layer 226b may include metal of the work function for the threshold voltage of p-type transistor.The first metal layer 226a may include for example TiAlC, TiAlCN, TiAlSiCN etc..Second metal layer 226b may include such as Ti, TiN, Ta, TaN.

First impurity range (not shown), which can be formed in the first n adjacent with the side wall of gate electrode structure in n-type region, to be had At the fin of source.First impurity range may be used as the source/drain region of n-type transistor.Second impurity range (not shown) can be formed in p-type area In domain at the first p active fin adjacent with the side wall of gate electrode structure.Second impurity range may be used as the source/drain of p-type transistor Area.

As described above, the grid of n-type transistor and p-type transistor can be (for example, be connected by directly electrical connection and physics Connect) it is electrically connected to each other.However, the first metal oxide layer 214a of n-type transistor and the second metal oxide of p-type transistor Layer 214b can be physically separated from each other.Therefore, it is possible to reduce the N-shaped generated due to the connection with metal oxide layer is brilliant Body pipe and p-type transistor may not have failure as target threshold voltage.

Figure 29 to Figure 38 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure.

Figure 30, Figure 32, Figure 33, Figure 35, Figure 36 and Figure 38 be along E-E ' interception cross-sectional view.Hereinafter, it only retouches State the device formed in logic cells area.In the peripheral region of the semiconductor devices including the logic cells area The structure of the I/O device of formation is not limited to any specific structure, and may include the I/O device formed in peripheral region One of above-described embodiment or other structures.

Referring to Figure 29 and Figure 30, the logic cells area of substrate 100 may include being used to form the n-type area of n-type transistor The domain N and p-type area P for being used to form p-type transistor.Boundary I between n-type region and p-type area can be in a first direction Upper extension.

The top of substrate 100 can be etched anisotropically through to form first groove at n-type region and p-type area.Every Absciss layer 104 can fill the lower part of first groove.Therefore, can be formed from the first active fin 202a outstanding of substrate 100 and 202b.The first active fin in n-type region can be referred to as the first n active fin 202a, and the first active fin in p-type area The first p active fin 202b can be referred to as.

The first initial illusory grid including stacking can be formed on the first active fin 202a and 202b and separation layer 104 The first initial illusory grid structure including insulating layer 206a, the first initial dummy gate electrode 206b and the first initial mask 206c 206.The first spacer (not shown) can be formed on the side wall of the first initial illusory grid structure 206.

First initial illusory grid structure 206 can extend in a second direction with multiple first active fin 202a and 202b Intersect.First initial illusory grid structure 206 can be formed as intersecting with n-type region N and p-type area P.

Referring to Figure 31 and Figure 32, it can etch and be formed at first grid cutting region C1 and second grid cutting region C2 The first initial illusory grid structure 206, to form the multiple first illusory grid structures 208.First initial illusory grid structure 206 is cut Cutting part can have the groove shape extended in a first direction.First illusory grid structure 208 may include first stacked Illusory gate insulation layer 208a, the first dummy gate electrode 208b and the first mask 208c.

Initial first interlayer insulating film can be sufficient filling with the groove and in a first direction the first illusory grid structure 208 Between gap.The upper surface that initial first interlayer insulating film can be planarized, until exposing the upper of the first illusory grid structure 208 Surface is to form the first interlayer insulating film (not shown) and insulating pattern 210.First interlayer insulating film can be formed in the first void If between grid structure 208.Insulating pattern 210 can be formed in the groove.

Insulating pattern 210 can be formed in the separation layer in first grid cutting region C1 and second grid cutting region C2 On 104.Insulating pattern 210 can extend in a first direction.

With reference to Figure 33, the first illusory grid structure 208 can be etched to form the first opening 212.First p active fin 202b, First n active fin 202a and separation layer 104 can be exposed by the first opening 212.

By first opening 212 expose the first p active fin 202b and the first n active fin 202a surface can be oxidized with Form pad oxide skin(coating) (not shown).In the first interlayer insulating film, insulating pattern 210 and conformal landform on oxide skin(coating) can be padded At the metal oxide layer 214 with high dielectric constant.Metal oxide layer 214 can be formed in the whole surface of the layer of exposing On.

Referring to Figure 34 and Figure 35, the first sacrificial layer 216 can be formed on metal oxide layer 214, to be sufficient filling with the One opening 212.First sacrificial layer 216 can cover the upper surface of insulating pattern 210 and the first interlayer insulating film.Implement in example In example, the first sacrificial layer 216 may include bottom antireflective coating (BARC).

In some example embodiments, before forming the first sacrificial layer 216, can on metal oxide layer 214 shape At the metal layer for control threshold voltage.

Hard mask 218 can be formed on the first sacrificial layer 216.Hard mask 218 can expose the first sacrificial layer 216 in n The part formed on boundary I between type region and p-type area.The exposed portion of hard mask 218 can prolong in a first direction It stretches.

Hard mask 218 can be used as etching mask and come the first sacrificial layer of sequential etch 216 and metal oxide layer 214, to form groove 220.Metal can be separated by removing a part of metal oxide layer 214 during etch process Oxide skin(coating) 214, to form the first metal oxide layer 214a in n-type region and form in p-type area the second metal Oxide skin(coating) 214b.Metal oxide layer is formed between the first metal oxide layer 214a and the second metal oxide layer 214b Absent region R3.First metal oxide layer 214a can be formed in insulating pattern 210, the first n active fin 202a surface with And on the first separation layer 104 between n active fin 202a.Second metal oxide layer 214b can be formed in insulating pattern 210, On separation layer 104 between the surface and the first p active fin 202b of first p active fin 202b.

The groove 220 can be formed along boundary I.Metal oxide layer 214 can be removed by etch process, so that isolation Layer 104 can be exposed by the groove 220.Therefore, metal oxide layer absent region R3 can be formed.

In the exemplary embodiment, when formation is used for control threshold voltage on metal oxide layer 214 in the prior art Metal layer when, the metal layer and metal oxide layer for control threshold voltage can be etched together in the etch process 214.In this case, it can be cut at the I of boundary for the metal layer of control threshold voltage.

With reference to Figure 36, hard mask 218 is removed.Remove the first sacrificial layer 216.Therefore, the first metal oxide can be exposed The upper surface of layer 214a and the second metal oxide layer 214b.

The first metal oxide layer 214a, the second metal oxide layer 214b and the first metal oxide layer 214a with Be conformally formed on separation layer 104 between second metal oxide layer 214b for control threshold voltage metal layer 222a and 222b.In this case, it can be connected at the I of boundary for the metal layer 222a and 222b of control threshold voltage.For example, with It can be formed on the first metal oxide layer 214a in the metal layer 222a of the threshold voltage of control n-type transistor.For controlling The metal layer 222b of the threshold voltage of p-type transistor processed can be formed on the second metal oxide layer 214b.

With reference to Figure 37 and Figure 38, can be formed on the metal layer 222a and 222b for control threshold voltage metal layer with The first opening of filling.The smoothization metal layer can be done, the upper table until the first interlayer insulating film and insulating pattern 210 can be exposed Face to form initial conduction pattern 224 in the first opening.

Referring again to Figure 27 and Figure 28, initial conduction pattern 224 can be partly etched to form upper conductive pattern 228.

Capping layer can be formed on upper conductive pattern 228, the first interlayer insulating film and insulating pattern 210 to fill first Opening.Capping layer can be planarized up to the upper surface of the first interlayer insulating film and insulating pattern 210, in upper conductive pattern Capping pattern 230 is formed on 228.

Therefore, gate electrode structure 232 can be formed in the first metal oxide layer 214a, the second metal oxide layer 214b And on the first separation layer 104 between metal oxide layer 214a and the second metal oxide layer 214b.Gate electrode structure 232 The first opening can be filled.In n-type region N, gate electrode structure 232 may include the threshold value electricity for controlling n-type transistor Metal layer 226a, upper conductive pattern 228 and the capping pattern 230 of pressure.In the P of p type island region domain, gate electrode structure 232 may include For controlling the metal layer 226b, upper conductive pattern 228 and capping pattern 230 of the threshold voltage of p-type transistor.

Figure 39 and Figure 40 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment.

Other than the shape of the first metal oxide layer and the second metal oxide layer, which can be with ginseng It is essentially identical according to semiconductor devices shown in Figure 27 and Figure 28.For example, the n-type region and p-type area of substrate, the first active fin, Insulating pattern and gate electrode structure can respectively with it is essentially identical those of referring to shown in Figure 27 and Figure 28.

With reference to Figure 39 and Figure 40, the first opening can extend through the first interlayer insulating film.First opening can be second Side upwardly extends.Insulating pattern 210 can be formed in first grid cutting region C1 and second grid cutting region C2 every On absciss layer 104.

First metal oxide layer 214a can be formed in the first n active fin 202a and first exposed by the first opening On separation layer 104 between n active fin 202a.

Second metal oxide layer 214b can be formed in the first p active fin 202b and first exposed by the first opening On separation layer 104 between p active fin 202b.First metal oxide layer 214a can have and the second metal oxide layer The identical material of the material of 214b.

In the embodiment of Figure 39 to Figure 40, the first metal oxide layer 214a and the second metal oxide layer 214b do not have It is formed on the side wall of insulating pattern 210.

The grid of n-type transistor and p-type transistor can be electrically connected to each other.However, the first metal of n-type transistor aoxidizes Nitride layer 214a and the second metal oxide layer 214b of p-type transistor can be physically separated from each other.

Figure 41 to Figure 44 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure.

It is possible, firstly, to execute the technique with reference to shown in Figure 29 and Figure 30, with the first active fin 202a and 202b and every The first initial illusory grid structure 206 is formed on absciss layer 104.Can be formed on the side wall of the first initial illusory grid structure 206 One spacer (not shown).

The first interlayer insulating film (not shown) can be formed between the first initial illusory grid structure 206.

In the exemplary embodiment, in this step, it does not execute in first grid cutting region C1 and second grid cutting area The first initial illusory grid structure 206 is cut at the C2 of domain to form groove and the in the trench operation of formation insulating pattern.

The first initial illusory grid structure 206 can be removed to form the first opening.First p active fin 202b, the first n are active Fin 202a and separation layer 104 can be exposed by the first opening.

Referring to Figure 41 and Figure 42, the table for the first p active fin and the first n active fin exposed by the first opening can be aoxidized Oxide skin(coating) (not shown) is padded to be formed in face.

The metal oxide layer with high dielectric constant can be formed on the first interlayer insulating film and pad oxide skin(coating).Gold In the whole surface for belonging to the layer that oxide skin(coating) can be formed in exposing.

The first sacrificial layer 240 can be formed on metal oxide layer to be sufficient filling with the first opening.First sacrificial layer 240 The upper surface of the first interlayer insulating film can be covered.In the exemplary embodiment, the first sacrificial layer 240 may include BARC.

It in some example embodiments, can be on metal oxide layer conformally before forming the first sacrificial layer 240 Form the metal layer for being used for control threshold voltage.

Hard mask 242 can be formed on the first sacrificial layer 240.Hard mask 242 can expose the first sacrificial layer 240 in n The part formed on boundary I between type region and p-type area.The exposed portion of hard mask 242 can prolong in a first direction It stretches.

Hard mask 242 can be used as etching mask and come the first sacrificial layer of sequential etch 240 and metal oxide layer, with Form groove 244.It can be by etch process separating metal oxide layer, to form the first metal oxide in n-type region Layer and forms the second metal oxide layer 214b at 214a in p-type area.First metal oxide layer 214a can be formed in On separation layer 104 between the surface and the first n active fin 202a of first n active fin 202a.Second metal oxide layer 214b can be formed on the separation layer 104 between the surface and the first p active fin 202b of the first p active fin 202b.

With reference to Figure 43 and Figure 44, hard mask 242 can be removed.The first sacrificial layer 240 can be removed.Therefore, can expose The upper surface of first metal oxide layer 214a and the second metal oxide layer 214b.

It can be in the first metal oxide layer 214a, the second metal oxide layer 214b and the first metal oxide layer The metal layer for control threshold voltage is conformally formed on separation layer 104 between 214a and the second metal oxide layer 214b 244a and 244b.In this case, it can be connected in boundary for the metal layer 244a of control threshold voltage with 244b.Example Such as, the first metal oxide layer 214a can be formed in for controlling the metal layer 244a of the threshold voltage of n-type transistor.With It can be formed on the second metal oxide layer 214b in the metal layer 244b of the threshold voltage of control p-type transistor.

Metal layer can be formed on the metal layer 244a and 244b for control threshold voltage to fill the first opening.It can To planarize the metal layer, until the upper surface of the first interlayer insulating film can be exposed to form initial conduction in the first opening Pattern 246.

Referring again to Figure 39 and Figure 40, the top of initial conduction pattern 246 can be partly etched to form upper conductive pattern Case 246a.Capping pattern 250 can be formed on upper conductive pattern 246a.

Can be etched at first grid cutting region and second grid cutting region formed capping pattern 250, on lead Electrical pattern 246a and the first interlayer insulating film are to form gate electrode structure.In the etch process, it can remove and be cut in first grid Cut the first metal oxide layer 214a and the second metal oxide layer formed at region C1 and second grid cutting region C2 214b。

Insulating layer can be formed to fill the groove formed by etch process.The insulating layer, Zhi Daoke can be planarized To expose the upper surface of capping pattern 250 to form insulating pattern 210.

As set forth above, it is possible to be formed after forming the first metal oxide layer 214a and the second metal oxide layer 214b Insulating pattern 210.Therefore, the first metal oxide layer 214a and the second metal oxide layer 214b can be not formed in insulation figure On the side wall of case 210.

Figure 45 and Figure 46 is the plan view and cross-sectional view for showing semiconductor devices according to example embodiment.

Other than grid structure and wiring, semiconductor devices shown in Figure 45 and Figure 46 can with referring to Figure 27 and Figure 28 institute The semiconductor devices shown is essentially identical.For example, the n-type region and p-type area and the first active fin of substrate can respectively with ginseng It those of examines shown in Figure 27 and Figure 28 essentially identical.

With reference to Figure 45 and Figure 46, the first opening and the second opening can extend through the first interlayer insulating film.It can be The grid structure of n-type transistor is formed in one opening.The grid structure of p-type transistor can be formed in the second opening.It can be The second insulating pattern 210b is formed on two directions between the first opening and the second opening.

First insulating pattern 210a can be formed on first grid cutting region C1 and second grid cutting region C2.

First metal oxide layer 214a can be formed in by first opening expose the first n active fin 202a surface with And on the first separation layer 104 between n active fin 202a.First metal oxide layer 214a can be not formed in the first insulation figure On case 210a and the second insulating pattern 210b (for example, on the side wall of the first insulating pattern 210a and the second insulating pattern 210b).

Second metal oxide layer 214b can be formed in by second opening expose the first p active fin 202b surface with And on the first separation layer 104 between p active fin 202b.Second metal oxide layer 214b can be not formed in the first insulation figure On case 210a and the second insulating pattern 210b (for example, on the side wall of the first insulating pattern 210a and the second insulating pattern 210b).

First gate electrode structure 251a can be formed in the first opening to cover the first metal oxide layer 214a.Second Gate electrode structure 251b can be formed in the second opening to cover the second metal oxide layer 214b.

First gate electrode structure 251a can be formed in n-type region, and the second gate electrode structure 251b can be formed In p-type area.First gate electrode structure 251a and the second gate electrode structure 251b can be separated from each other.Therefore, the first grid Electrode structure 251a and the second gate electrode structure 251b can be physically separated from each other.

Upper interlayer insulating film 252 can be formed in first gate electrode structure 251a, the second gate electrode structure 251b, first absolutely On edge pattern 210a and the second insulating pattern 210b and the first interlayer insulating film.

Upper wiring 254 can be formed through interlayer insulating film 254, so that first gate electrode structure 251a and second gate The top of electrode structure 251b is electrically connected to each other by upper wiring 254.

Figure 47 to Figure 50 is plan view and the cross section for the method for showing manufacturing semiconductor devices according to example embodiment Figure.

Referring to Figure 47 and Figure 48, it is possible, firstly, to the technique with reference to shown in Figure 41 and Figure 42 be executed, in the first layer insulation The metal oxide layer 214 with high dielectric constant is formed on layer and pad oxide skin(coating).Metal is aoxidized it is then possible to not execute The etching of nitride layer 214.

The metal layer 244a and 244b for control threshold voltage can be formed on metal oxide layer 214.It can be Upper conductive pattern 246 is formed in first opening.Capping pattern 250 can be formed on upper conductive pattern 246.

With reference to Figure 49 and Figure 50, can etch positioned at first grid cutting region C1, second grid cutting region C2 and side Capping pattern 250, upper conductive pattern 246 at boundary I, metal layer 244a and 244b for control threshold voltage, metal oxidation Nitride layer 214 and the first interlayer insulating film, to form first gate electrode structure 251a in n-type region and in p-type area Form the second gate electrode structure 251b.In addition, the first metal oxide layer 214a can be formed in n-type region, and second Metal oxide layer 214b can be formed in p-type area.

Insulating pattern can be formed to fill the groove formed by etch process.For example, the first insulating pattern 210a can To be formed in the groove at first grid cutting region C1 and second grid cutting region C2.Second insulating pattern 210b can be with It is formed in the groove at the I of boundary.

Referring again to Figure 45 and Figure 46, can first gate electrode structure 251a, the second gate electrode structure 251b, first absolutely Upper interlayer insulating film 252 is formed on edge pattern 210a and the second insulating pattern 210b and the first interlayer insulating film.

Upper wiring 254 can be formed through interlayer insulating film 252, so that first gate electrode structure 251a and second gate Electrode structure 251b is electrically connected to each other by upper wiring 254.

Foregoing teachings are the explanations to example embodiment, and are not necessarily to be construed as limitation ot it.Although it have been described that Some example embodiments, but the person skilled in the art will easily understand in the novel religion for not being detached from present inventive concept substantially In the case where justice and advantage, a variety of modifications can be carried out in the exemplary embodiment.Therefore, all this modifications are intended to be included in In the scope of the present invention being defined by the claims.In the claims, device adds function clause to be intended to comprising described herein The structure of the function is executed, and further includes not only equivalent structure including equivalent structures.It will be understood, therefore, that foregoing teachings It is the explanation to various example embodiments, and should not be construed as limited to disclosed specific example embodiment, and to institute The modification of disclosed example embodiment and other example embodiments are intended to be included in scope of the appended claims.