阅读说明：本技术 一种半导体器件及其制造方法 (A kind of semiconductor devices and its manufacturing method ) 是由 乔明 孟培培 张波 于 2019-09-06 设计创作，主要内容包括：本发明提供一种半导体器件及其制造方法,属于功率半导体技术领域。所述的半导体器件由多个结构相同的元胞以叉指方式连接形成,所述的元胞结构包括第二导电类型轻掺杂衬底、第一导电类型轻掺杂外延层、扩散第二导电类型阱区、具有第一导电类型的第一、第三重掺杂区、具有第二导电类型的第二重掺杂区、耗尽型沟道区、氧化介质层、金属阴极、金属阳极以及背面金属电极。本发明通过金属场板及注入第二导电类型掺杂区的形式,对器件正向耐压及恒流特性进行优化设计；采用的第二导电类型轻掺杂衬底起到辅助耗尽第一导电类型轻掺杂外延层及导电沟道的作用,既提高器件耐压又减小了夹断电压,实现更好的恒流能力与更高的击穿电压。最终设计得到器件耐压达到460V,夹断电压在4V以下。(The present invention provides a kind of semiconductor devices and its manufacturing method, belongs to power semiconductor technologies field.The semiconductor devices is connected with interdigited fashion by the identical cellular of multiple structures and is formed, and the structure cell includes that substrate, the first conduction type lightly doped epitaxial layer, the second conduction type well region of diffusion, first with the first conduction type, third heavily doped region, the second heavily doped region with the second conduction type, deplection type channel area, oxide isolation floor, metallic cathode, metal anode and back metal electrode is lightly doped in the second conduction type.The present invention optimizes the positive pressure resistance of device and constant-current characteristics by way of the second conduction type doped region of Metal field plate and injection；The second conduction type used is lightly doped substrate and plays the role of assisted depletion the first conduction type lightly doped epitaxial layer and conducting channel, had not only improved device pressure resistance but also had reduced pinch-off voltage, and had realized better constant current ability and higher breakdown voltage.Final design obtains device pressure resistance and reaches 460V, and pinch-off voltage is in 4V or less.)

1. a kind of semiconductor devices, is connected with interdigited fashion by the identical cellular of multiple structures and formed, the structure cell includes Substrate (1), the first conduction type lightly doped epitaxial layer (2), oxide isolation layer (10), metallic cathode is lightly doped in second conduction type (11), metal anode (12) and back metal electrode (13)；There is diffusion second in first conduction type lightly doped epitaxial layer (2) Conduction type well region (3), the first conduction type deplection type channel area (8), the first heavily doped region (5), the second heavily doped region (6) and Third heavily doped region (7), the first heavily doped region (5) and third heavily doped region (7) are the first conduction type, the second heavily doped region It (6) is the second conduction type；

The first conduction type lightly doped epitaxial layer (2) is located at the second conduction type and is lightly doped above substrate (1), diffusion second Conduction type well region (3) is arranged in the first conduction type lightly doped epitaxial layer (2), the first conduction type deplection type channel area (8) it is located at the upper layer of the first conduction type lightly doped epitaxial layer (2), the first heavily doped region (5) and the second heavily doped region (6) are side by side Positioned at the section top of the second conduction type well region (3) of diffusion；Third heavily doped region (7) is located at first conduction type and gently mixes The upper layer side of miscellaneous epitaxial layer (2)；

Oxide isolation floor (10) is located at the first part and part the first conduction type deplection type channel area of the first heavily doped region (5) (8) on；Metallic cathode (11) is located at the second part of the first heavily doped region (5), the first part of the second heavily doped region (6) and oxygen Change on dielectric layer (10)；Metal anode (12) is located in the first part of third heavily doped region (7)；First heavily doped region (5) it is shorted with the second heavily doped region (6), and forms Ohmic contact, the third heavily doped region (7) and gold with metallic cathode (11) Belong to anode (12) and forms Ohmic contact；

Oxide isolation layer (10) is also located at the first part of the second heavily doped region (6) and the first part of third heavily doped region (7) Between the first conduction type lightly doped epitaxial layer (2) on；Back metal electrode (13) is located at the second conduction type and lining is lightly doped The lower section at bottom (1).

2. a kind of semiconductor devices according to claim 1, which is characterized in that metallic cathode (11) and metal anode (12) Field plate structure is extended to form along the surface of oxide isolation layer (10).

3. a kind of semiconductor devices according to claim 2, which is characterized in that further include the second conduction type doped region (4), the second conduction type doped region (4) is located between the second conduction type well region (3) of third heavily doped region (7) and diffusion, and Positioned at the surface layer of the first conduction type lightly doped epitaxial layer (2), the both ends of the second conduction type doped region (4) are located at metallic cathode (11) and the lower section of metal anode (12).

4. a kind of semiconductor devices according to claim 2, which is characterized in that further include the second conduction type doped region (4), the second conduction type doped region (4) is located between the second conduction type well region (3) of third heavily doped region (7) and diffusion, and In the first conduction type lightly doped epitaxial layer (2), the both ends of the second conduction type doped region (4) are located at metallic cathode (11) With the lower section of metal anode (12).

5. a kind of semiconductor devices according to claim 3, which is characterized in that further include buries oxide layer (14), bury oxidation Layer (14) is located at the second conduction type and is lightly doped between substrate (1) and the first conduction type lightly doped epitaxial layer (2), and will be described The doping type of third heavily doped region (7) replaces with the second conduction type, forms the 4th heavily doped region (9).

6. a kind of semiconductor devices according to claim 1, which is characterized in that material used by the semiconductor devices For silicon or silicon carbide.

7. a kind of semiconductor devices according to claim 1, which is characterized in that first conduction type is N-type, described Second conduction type is p-type；Or first conduction type is p-type, second conduction type is N-type.

8. a kind of manufacturing method of semiconductor devices, which comprises the following steps:

Select the second conduction type lightly doped silicon wafer that substrate (1) is lightly doped as the second conduction type, using epitaxy technique, in institute It states and forms the first conduction type lightly doped epitaxial layer (2) on substrate；

The second conduction type well region (3) is spread in the formation being spaced in the first conduction type lightly doped epitaxial layer (2)；

The second conduction type doped region (4) is formed in the two sides for diffusion the second conduction type well region (3) that interval is formed；

Using ion implantation technology, ion implanting is carried out on entire first conduction type lightly doped epitaxial layer (2) surface, forms the One conduction type deplection type channel area (8)；

On the upper layer two for the section top and the first conduction type lightly doped epitaxial layer (2) for spreading the second conduction type well region (3) End is respectively formed the first heavily doped region (5) and third heavily doped region (7)；

The second heavy doping is formed in the upper layer for spreading the second conduction type well region (3), and in the side of the first heavily doped region (5) Area (6)；

Oxide isolation layer (10) are formed in the first conduction type lightly doped epitaxial layer (2)；Photoetching simultaneously etches the oxide isolation Layer (10) forms ohm hole, deposits aluminum metal and anti-carves, forms metallic cathode (11) and metal anode (12)；

Passivation layer is deposited on oxide isolation layer (10), metallic cathode (11) and metal anode (12), etches the hole PAD；

Back note metal, forms back metal electrode (13) below substrate.

9. the manufacturing method of semiconductor devices according to claim 8, which is characterized in that formed by multiple ion implanting Spread the second conduction type well region (3), wherein the energy and dosage of rear primary ions injection are lower than the energy of preceding primary ions injection Amount and dosage.

10. the manufacturing method of semiconductor devices according to claim 8, which is characterized in that conductive forming diffusion second Before type well region (3), progress field oxygen oxidation processes on the active area are further comprised the steps of:, field oxygen is formed.

Technical field

The invention belongs to power semiconductor device technology fields, and in particular to a kind of semiconductor devices and its manufacturing method.

Background technique

Constant-current source is a kind of common electronic equipment and device, using fairly common in electronic circuit.Constant-current source is usual For protecting entire circuit, even if occurring spread of voltage in circuit or the case where load resistor value changes greatly, remain to protect Demonstrate,prove the stabilization of entire circuit supply current.Current regulator diode (CRD, Constant Regulating Diode) is a kind of common Semiconductor constant current device replaces common by multiple electronics such as transistor, voltage-stabiliser tube and resistance using diode as constant-current source The constant-current source of element composition realizes that circuit structure is simplified and minimized.Common current regulator diode output electric current is in several millis at present Pacify between tens milliamperes, can be used for directly driving load, due to having the characteristics that device volume is small, device reliability is high, make It has great advantage compared to conventional constant current source.In addition the peripheral circuit of current regulator diode is simple, easy to use, has been widely used In fields such as automatic control, instrument and meter and protection circuits.But the forward break down voltage of current current regulator diode is generally located at 30 In the section~100V, therefore there is a problem of that breakdown voltage is lower, while the constant current value that can be provided is also relatively low.

Summary of the invention

The technical problem to be solved by the present invention is in view of the problems of the existing technology, provide a kind of semiconductor devices and Its manufacturing method.

In order to solve the above technical problems, the embodiment of the present invention provides a kind of semiconductor devices, by the identical member of multiple structures Born of the same parents connect to be formed with interdigited fashion, and the structure cell includes that substrate is lightly doped in the second conduction type, the first conduction type is gently mixed Miscellaneous epitaxial layer, oxide isolation layer, metallic cathode, metal anode and back metal electrode；First conduction type lightly doped epitaxial layer In have diffusion the second conduction type well region, the first conduction type deplection type channel area, the first heavily doped region, the second heavily doped region With third heavily doped region, the first heavily doped region and third heavily doped region are the first conduction type, and the second heavily doped region is led for second Electric type；

The first conduction type lightly doped epitaxial layer is located at the second conduction type and is lightly doped above substrate, and diffusion second is led Electric type well region is arranged in the first conduction type lightly doped epitaxial layer, and the first conduction type deplection type channel area is located at first and leads The upper layer of electric type lightly doped epitaxial layer, the first heavily doped region and the second heavily doped region are located side by side at the second conductive type of trap of diffusion The section top in area；Third heavily doped region is located at the upper layer side of the first conduction type lightly doped epitaxial layer；

Oxide isolation floor is located in the first part and part the first conduction type deplection type channel area of the first heavily doped region； Metallic cathode is located in the first part and oxide isolation layer of the second part of the first heavily doped region, the second heavily doped region；Metal Anode is located in the first part of third heavily doped region；First heavily doped region and the second heavily doped region are shorted, and and metal Cathode forms Ohmic contact, and the third heavily doped region and metal anode form Ohmic contact；

Oxide isolation layer is also located between the first part of the second heavily doped region and the first part of third heavily doped region In first conduction type lightly doped epitaxial layer；Back metal electrode is located at the lower section that substrate is lightly doped in the second conduction type.

The beneficial effects of the present invention are: semiconductor devices of the invention injects knot in the epitaxial layer forms well region, in trap Deplection type channel and JFET conducting channel are respectively formed among area surface and two well regions, the form of double channel improves device constant current Effect and motional impedance value, and the substrate opposite with channel dopant type is used, assisted depletion is served to channel, is accelerated JFET conducting channel exhausts, and pinch-off voltage control is in 4V hereinafter, to obtain more excellent constant-current characteristics and higher pressure resistance.

Based on the above technical solution, the present invention can also be improved as follows.

Further, metallic cathode and metal anode extend to form field plate structure along the surface of oxide isolation layer.

Beneficial effect using above-mentioned further scheme is: making that device reaches better constant-current characteristics and higher forward direction is resistance to Pressure value.

It further, further include the second conduction type doped region, the second conduction type doped region is located at third heavily doped region Between the second conduction type well region of diffusion, and it is located at the surface layer of the first conduction type lightly doped epitaxial layer, the second conduction type The both ends of doped region are located at the lower section of metallic cathode and metal anode.

Beneficial effect using above-mentioned further scheme is: that accelerates the first conduction type lightly doped epitaxial layer exhausts speed Degree, realizes better constant current ability and higher breakdown voltage.

It further, further include the second conduction type doped region, the second conduction type doped region is located at third heavily doped region Between the second conduction type well region of diffusion, and it is located in the first conduction type lightly doped epitaxial layer, the doping of the second conduction type The both ends in area are located at the lower section of metallic cathode and metal anode.

Beneficial effect using above-mentioned further scheme is: that accelerates the first conduction type lightly doped epitaxial layer exhausts speed Degree, realizes better constant current ability and higher breakdown voltage.

It further, further include buries oxide layer, buries oxide layer is located at the second conduction type and substrate and the first conduction is lightly doped Between type lightly doped epitaxial layer, and the doping type of the third heavily doped region is replaced with into the second conduction type, forms the Four heavily doped regions.

Using the beneficial effect of above-mentioned further scheme is: for semiconductor devices of the invention for bipolar device, electric current is close It spends big compared with monopole type device；Since there are two types of carriers to participate in conduction, not only current density is high under identical anode voltage, and It is easier to be rapidly achieved saturation state, there is lesser pinch-off voltage；Metal anode and cathode extend to form field plate knot to two sides Structure is alleviated and is formed by the 4th heavily doped region, the first conduction type lightly doped epitaxial layer and the second conduction type well region of diffusion Parasitic-PNP transistor lateral punchthrough issues, in turn ensure the preferable constant-current characteristics of device；In view of longitudinal parasitism PNP is brilliant The punchthrough issues of body pipe, using soi wafer structure, outside substrate is lightly doped in the second conduction type and the first conduction type is lightly doped Prolong and be provided with buries oxide layer between layer, has prevented longitudinal phost line electrical leakage problems completely.

Further, material used by the semiconductor devices is silicon or silicon carbide.

Further, first conduction type is N-type, and second conduction type is p-type；Or first conduction Type is p-type, and second conduction type is N-type.

In order to solve the above technical problems, the embodiment of the present invention also provides a kind of manufacturing method of semiconductor devices, including with Lower step:

The second conduction type lightly doped silicon wafer is selected as the second conduction type, substrate is lightly doped, using epitaxy technique, In The first conduction type lightly doped epitaxial layer is formed on the substrate；

The second conduction type well region is spread in the formation being spaced in the first conduction type lightly doped epitaxial layer；

The second conduction type doped region is formed in the two sides for diffusion the second conduction type well region that interval is formed；

Using ion implantation technology, ion implanting is carried out on entire first conduction type lightly doped epitaxial layer surface, is formed First conduction type deplection type channel area；

At the upper layer both ends for the section top and the first conduction type lightly doped epitaxial layer for spreading the second conduction type well region It is respectively formed the first heavily doped region and third heavily doped region；

The second heavy doping is formed in the upper layer for spreading the second conduction type well region, and in the side of the first heavily doped region Area；

Oxide isolation layer is formed in the first conduction type lightly doped epitaxial layer；Photoetching simultaneously etches the oxide isolation layer shape At ohm hole, deposits aluminum metal and anti-carve, form metallic cathode and metal anode；

Passivation layer is deposited on oxide isolation layer, metallic cathode and metal anode, etches the hole PAD；

Back note metal, forms back metal electrode below substrate.

The beneficial effects of the present invention are: semiconductor devices of the invention injects knot in the epitaxial layer forms well region, in trap Deplection type channel and JFET conducting channel are respectively formed among area surface and two well regions, the form of double channel improves device constant current Effect and motional impedance value, and the substrate opposite with channel dopant type is used, assisted depletion is served to channel, is accelerated JFET conducting channel exhausts, and pinch-off voltage control is in 4V hereinafter, to obtain more excellent constant-current characteristics and higher pressure resistance.

Based on the above technical solution, the present invention can also be improved as follows.

Further, the second conduction type well region of diffusion is formed by multiple ion implanting, wherein rear primary ions injection Energy and dosage be lower than preceding primary ions injection energy and dosage.

Beneficial effect using above-mentioned further scheme is: weakening surface channel and diffusion well region impurity compensation degree, drop Low surface depletion channel and JFET conducting channel transitional region width are easy to surface channel pinch off, reduce pinch-off voltage, lifter Part constant-current characteristics.

Further, before forming the second conduction type well region of diffusion, progress field oxygen on the active area is further comprised the steps of: Oxidation processes form field oxygen.

Beneficial effect using above-mentioned further scheme is: by by the second conduction type well region be made in an oxygen process it Afterwards, well region can be made to be subjected to shorter thermal process, reduce impurity lateral diffusion length.

Detailed description of the invention

Fig. 1 (a)-Fig. 1 (e) is a kind of cross-section structure signal of semiconductor devices of the first to the 5th embodiment of the invention Figure；

Fig. 2 is a kind of structure cell schematic diagram of semiconductor devices of third embodiment of the invention；

Fig. 3 is a kind of cellular process simulation schematic diagram of semiconductor devices of third embodiment of the invention；

Fig. 4 is a kind of current -voltage curve figure of semiconductor devices of third embodiment of the invention；

Fig. 5 (a)-Fig. 5 (f) is that a kind of process flow of the manufacturing method of semiconductor devices of sixth embodiment of the invention is shown It is intended to；

Fig. 6 (a)-Fig. 6 (f) is that a kind of corresponding technique of manufacturing process of semiconductor devices of sixth embodiment of the invention is imitative True figure.

In attached drawing, parts list represented by the reference numerals are as follows:

C (1), c (2) ... c (i) are structure cell, and i is positive integer, indicate cellular number, and the 1, second conduction type is lightly doped Substrate, the 2, first conduction type lightly doped epitaxial layer, 3, the second conduction type well region of diffusion, the 4, second conduction type doped region, 5, the first heavily doped region, the 6, second heavily doped region, 7, third heavily doped region, the 8, first conduction type deplection type channel area, 9, Four heavily doped regions, 10, oxide isolation layer, 11, metallic cathode, 12, metal anode, 13, back metal electrode, 14, buries oxide layer.

Specific embodiment

The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and It is non-to be used to limit the scope of the invention.

As shown in Fig. 1 (a), a kind of semiconductor devices that first embodiment of the invention provides, by the identical member of multiple structures Born of the same parents connect to be formed with interdigited fashion, and the structure cell includes that substrate 1 is lightly doped in the second conduction type, the first conduction type is gently mixed Miscellaneous epitaxial layer 2, oxide isolation layer 10, metallic cathode 11, metal anode 12 and back metal electrode 13；First conduction type is gently mixed In miscellaneous epitaxial layer 2 have diffusion the second conduction type well region 3, the first conduction type deplection type channel area 8, the first heavily doped region 5, Second heavily doped region 6 and third heavily doped region 7, the first heavily doped region 5 and third heavily doped region 7 be the first conduction type, second Heavily doped region 6 is the second conduction type；

The first conduction type lightly doped epitaxial layer 2 is located at the second conduction type and 1 top of substrate, diffusion second is lightly doped Conduction type well region 3 is arranged in the first conduction type lightly doped epitaxial layer 2, and the first conduction type deplection type channel area 8 is located at The upper layer of first conduction type lightly doped epitaxial layer 2, the first heavily doped region 5 and the second heavily doped region 6 are located side by side at diffusion second The section top of conduction type well region 3；Third heavily doped region 7 is located at the upper layer of the first conduction type lightly doped epitaxial layer 2 Side；

Oxide isolation floor 10 is located at the first part and part the first conduction type deplection type channel area of the first heavily doped region 5 On 8；Metallic cathode 11 is located at the second part of the first heavily doped region 5, the first part of the second heavily doped region 6 and oxide isolation layer On 10；Metal anode 12 is located in the first part of third heavily doped region 7；First heavily doped region 5 and the second heavily doped region 6 It is shorted, and forms Ohmic contact with metallic cathode 11, the third heavily doped region 7 forms Ohmic contact with metal anode 12；

Oxide isolation layer 10 be also located at the second heavily doped region 6 first part and third heavily doped region 7 first part it Between the first conduction type lightly doped epitaxial layer 2 on；Back metal electrode 13 is located at the second conduction type and is lightly doped under substrate 1 Side.

In above-described embodiment, semiconductor devices of the invention injects knot in the epitaxial layer and forms well region, on well region surface Be respectively formed deplection type channel and JFET conducting channel among two well regions, the form of double channel improve device constant current effect and Motional impedance value, and the substrate opposite with channel dopant type is used, assisted depletion is served to channel, it is conductive to accelerate JFET Channel exhausts, and pinch-off voltage control is in 4V hereinafter, to obtain more excellent constant-current characteristics and higher pressure resistance.

The number i of the cellular can be adjusted according to the demand of specific constant current value.Spread the second conductive type of trap 3 junction depth of area, mutual distance and implantation dosage can be adjusted according to the requirement of device constant current value and pinch-off voltage, make The flexibility for obtaining device design is greatly improved, in addition, device is adjusted by the implantation dosage and energy for controlling deplection type channel 8 The current capacity of part.

Below using the first conduction type as N-type, the second conduction type is p-type to introduce the working principle of the invention, at this point, The second conduction type well region 3 is spread for diffusion P type trap zone, and the first conduction type deplection type channel area 8 is N-type deplection type channel Area, the first heavily doped region 5 with the first conduction type are the first N-type heavily doped region, the second weight with the second conduction type Doped region 6 is the second p-type heavily doped region, and the third heavily doped region 7 with the first conduction type is third N-type heavily doped region, the One conduction type lightly doped epitaxial layer 2 is N-type lightly doped epitaxial layer.Working principle of the present invention is as follows:

The semiconductor devices is to be connected by c (1), the identical cellular of c (2) ... c (i) with interdigited fashion, cellular Number i can be adjusted according to specific current capacity demand.The present invention passes through in diffusion P type trap zone surface tune ditch injection Phosphonium ion makes surface compensate to form N-type deplection type channel area, then is implanted sequentially and to form the first N-type heavily doped region and third N-type weight Doped region and the second p-type heavily doped region.Before carrying out the injection of surface tune ditch, by injecting P in the top of N-type lightly doped epitaxial layer Type doped region, preferably to promote device constant-current characteristics and breakdown voltage.Adjust ditch injection phosphonium ion dosage and diffusion p-type Well region distance can make channel region realize lesser pinch-off voltage；Deplection type channel area is after pinch off, with the increasing of anode voltage Add, channel carriers speed reaches saturation, when reaching pinch-off point, is depleted area's strong electrical field and is swept into the first N-type heavily doped region 5 Among, hereafter electric current no longer increases with anode voltage and is increased, and realizes preferable constant current ability；In addition, adjustment diffusion P type trap zone Implantation Energy and knot time make vertical-channel and surface depletion channel region realize pinch off simultaneously, can further promote device perseverance Properties of flow；Current value size can be by adjusting tune ditch injection phosphonium ion dosage, deplection type channel section length and diffusion P type trap zone Dosage is adjusted；Metallic cathode 11 and metal anode 12 can extend to form field plate structure to two sides, and Metal field plate length can It adjusts, in conjunction with P-doped zone and common assisted depletion epitaxial layer, realizes the higher forward break down voltage of device.

The metal anode 12 of semiconductor devices of the invention connects high potential, and metallic cathode 11 connects low potential, spreads p-type Depletion layer is formed between well region and N-type lightly doped epitaxial layer, two cellulars spread non-depleted region between P type trap zone and form vertical furrow Road, as anode voltage increases, depletion layer is constantly extended to centre, and the broadening of depletion layer causes conduction channel region to narrow.Ditch Before non-pinch off, characteristic is equivalent to a semiconductor resistor in road, and electric current increases with the increase of voltage, at this time device state Work in linear zone；When the depletion layer that anode voltage continues to increase to two sides contacts with each other, channel region is by pinch off, at this time Anode voltage is known as pinch-off voltage, after channel pinch off, continues growing anode voltage, pinch-off point changes slow with the increase of anode voltage Slowly, device current, which is pushed the speed, slows down, and device work at this time is in transitional region；Then it is further added by anode voltage, pinch-off point and electricity Flow valuve all no longer changes substantially, and device works in constant current area.In the process, positioned at the depletion type ditch on diffusion P type trap zone surface The both ends in road area also have similar pinch off process since there is also pressure drops, by reasonably adjust diffusion P type trap zone between Away from, implantation dosage and knot time etc., it can be achieved that pinch off while surface depletion channel and vertical-channel, electric current is not with voltage Variation and change, greatly promote the constant-current characteristics of device.

As shown in Fig. 1 (b), a kind of semiconductor devices that second embodiment of the invention provides is implemented in the present invention first On the basis of example, metallic cathode 11 and metal anode 12 is made to extend to form field plate structure along the surface of oxide isolation layer 10.It should In structure, field plate length is adjustable, can effectively shield high electric field peak value at media slot bottom corners, electric field point in optimised devices body Cloth, and the thickness of the first conduction type lightly doped epitaxial layer 2 and concentration are also adjusted, and so that device is reached better constant current special Property with higher positive pressure voltage.

As shown in Fig. 1 (c) and Fig. 2, a kind of semiconductor devices that third embodiment of the invention provides is in the present invention second It further include the second conduction type doped region 4 on the basis of embodiment, the second conduction type doped region 4 is located at third heavily doped region 7 Between the second conduction type well region 3 of diffusion, and it is located at the surface layer of the first conduction type lightly doped epitaxial layer 2, the second conductive-type The both ends of type doped region 4 are located at the lower section of metallic cathode 11 and metal anode 12.

What above-described embodiment can accelerate the first conduction type lightly doped epitaxial layer 2 exhausts speed, realizes better constant current energy Power and higher breakdown voltage.

Wherein metallic cathode 11, the length of metal anode 12 and the second conduction type doped region 4 and relative position It adjusts, to realize the good constant current ability of device and different pressure voltages.

As shown in Fig. 1 (d), a kind of semiconductor devices that fourth embodiment of the invention provides is implemented in the present invention second It further include the second conduction type doped region 4 on the basis of example, the second conduction type doped region 4 is located at third heavily doped region 7 and expands It dissipates between the second conduction type well region 3, and is located in the first conduction type lightly doped epitaxial layer 2, the second conduction type doped region 4 Both ends be located at the lower section of metallic cathode 11 and metal anode 12.

In above-described embodiment, that accelerates the first conduction type lightly doped epitaxial layer 2 exhausts speed, realizes better constant current energy Power and higher breakdown voltage.

As shown in Fig. 1 (e), a kind of semiconductor devices that fifth embodiment of the invention provides is implemented in third of the present invention It further include buries oxide layer 14, buries oxide layer 14 is located at the second conduction type and substrate 1 and the first conductive-type is lightly doped on the basis of example Between type lightly doped epitaxial layer 2, and the doping type of the third heavily doped region 7 is replaced with into the second conduction type, forms the Four heavily doped regions 9.

Semiconductor devices in the structure is bipolar device, and current density is big compared with monopole type device；Since there are two types of loads Stream participates in conductive, and not only current density is high under identical anode voltage, and is easier to be rapidly achieved saturation state, have compared with Small pinch-off voltage；Metal anode and cathode extend to form field plate structure to two sides, alleviate by the 4th heavily doped region 9, first The lateral break-through that conduction type lightly doped epitaxial layer 2 and the second conduction type well region 3 of diffusion are formed by parasitic-PNP transistor is asked Topic, in turn ensures the preferable constant-current characteristics of device；In view of the punchthrough issues of longitudinal parasitic-PNP transistor, using soi wafer knot Structure is lightly doped between substrate 1 and the first conduction type lightly doped epitaxial layer 2 in the second conduction type and is provided with buries oxide layer 14, Longitudinal phost line electrical leakage problems are prevented completely.

The semiconductor devices is formed by the interdigital connection of multiple identical cellulars, wherein adjacent third heavily doped region 7 or The 4th heavily doped region 9 of person shares, and adjacent 3 spacing of the second conduction type of diffusion well region can be according to constant current value and pinch-off voltage Demand is adjusted.

Optionally, material used by the semiconductor devices is silicon or silicon carbide.

Optionally, first conduction type is N-type, and second conduction type is p-type；Or first conductive-type Type is p-type, and second conduction type is N-type.

By means of TSUPREM4 with MEDICI simulation software to the cellular knot of the semiconductor devices of third embodiment of the invention Structure carries out device simulation, as shown in figure 3, the second conduction type is p-type using the first conduction type as N-type, positive pressure resistance is 460V illustrates simulation parameter for the semiconductor devices that electric current is about 2.6E-5A/ μm: initial silicon wafer thickness is about 250 μm, p-type The concentration that substrate is lightly doped is 3.6E14cm^-3, the concentration of N-type lightly doped epitaxial layer is 2.5E15cm^-3, thickness is about 10.8 μm, It spreads P type trap zone and injects boron, implantation dosage 2.5E13cm^-2, Implantation Energy 80keV, the knot time is 500 minutes, wide About 9.0 μm or so of degree, the distance of two adjacent diffusion P type trap zones is 4.0 μm；P-doped zone is also injected into boron, Implantation Energy For 1150keV, implantation dosage 1.75E12cm^-2；The first N-type heavily doped region and third N-type heavily doped region as Ohmic contact Inject phosphorus, implantation dosage 4.0E15cm^-2, Implantation Energy 60keV is equally used for the second p-type heavily doped region of Ohmic contact Inject boron, implantation dosage 4.0E15cm^-2, Implantation Energy 60keV；The length in deplection type channel area is at 3.5 μm or so；Diffusion P type trap zone is 35 μm at a distance from third N-type heavily doped region；Metallic cathode 11 and metal anode 12 with a thickness of 2.5 μm, institute's shape At field plate length can adjust accordingly；The first N-type of cathode portion heavily doped region, deplection type channel area and JFET overlying regions Oxidated layer thickness is 0.8um.

As shown in figure 4, be computed it can be concluded that device pinch-off voltage in 4V hereinafter, pinch-off voltage can by adjust spread The implantation dosage of P type trap zone, two adjacent diffusion P type trap zone spacing, N-type lightly doped epitaxial layer concentration and tune ditch implantation dosage etc. It is controlled；From this figure it can be seen that device current is held essentially constant value after reaching constant current area, have good Constant-current characteristics.

As shown in Fig. 5 (a) -5 (f) and Fig. 6 (a) -6 (f), a kind of semiconductor device of sixth embodiment of the present invention offer The manufacturing method of part, comprising the following steps:

The second conduction type lightly doped silicon wafer is selected as the second conduction type, substrate 1 is lightly doped, using epitaxy technique, In The first conduction type lightly doped epitaxial layer 2 is formed on the substrate；

The second conduction type well region 3 is spread in the formation being spaced in the first conduction type lightly doped epitaxial layer 2；

The second conduction type doped region 4 is formed in the two sides for the second conduction type of diffusion well region 3 that interval is formed；

Using ion implantation technology, ion implanting is carried out on entire first conduction type lightly doped epitaxial layer, 2 surface, is formed First conduction type deplection type channel area 8；

On the upper layer two for the section top and the first conduction type lightly doped epitaxial layer 2 for spreading the second conduction type well region 3 End is respectively formed the first heavily doped region 5 and third heavily doped region 7；

The second heavy doping is formed in the upper layer for spreading the second conduction type well region 3, and in the side of the first heavily doped region 5 Area 6；

Oxide isolation layer 10 is formed in the first conduction type lightly doped epitaxial layer 2；Photoetching simultaneously etches the oxide isolation Layer 10 forms ohm hole, deposits aluminum metal and anti-carves, forms metallic cathode 11 and metal anode 12；

Passivation layer is deposited on oxide isolation layer 10, metallic cathode 11 and metal anode 12, etches the hole PAD；

Back note metal, forms back metal electrode 13 below substrate.

In above-described embodiment, semiconductor devices of the invention injects knot in the epitaxial layer and forms well region, on well region surface Be respectively formed deplection type channel and JFET conducting channel among two well regions, the form of double channel improve device constant current effect and Motional impedance value, and the substrate opposite with channel dopant type is used, assisted depletion is served to channel, it is conductive to accelerate JFET Channel exhausts, and pinch-off voltage control is in 4V hereinafter, to obtain more excellent constant-current characteristics and higher pressure resistance.

Wherein, before being diffused the injection of the second conduction type well region 3, pre-impregnated with hydrogen peroxide is carried out, then use photoetching process, and The second conduction type well region 3 of diffusion is formed by ion implanting and high temperature knot processing, etching removes extra oxide layer later, Extra oxide layer is the oxide layer generated by pre-impregnated with hydrogen peroxide and during the high temperature knot is handled, in device table It looks unfamiliar longer oxide layer.At this point, ion implantation energy is 80keV, the high temperature knot time is about 500 minutes；

Before carrying out the first heavily doped region 5 and being injected with third heavily doped region 7, pre-impregnated with hydrogen peroxide is carried out, photoetching work is then used Skill, then the first conductive type impurity is injected by ion implantation technology, to form the first heavily doped region 5 and third heavily doped region 7, the second conductive type impurity is injected using photoetching process, then by ion implantation technology, so that the second heavily doped region 6 is formed, Then etching removes extra oxide layer, and extra oxide layer is the oxide layer generated by pre-impregnated with hydrogen peroxide；

Second conduction type doped region 4 is formed using ion implantation technology, then carries out rapid thermal anneal process, when continuing Between about 20 seconds；

Formed the second conduction type well region 3 of diffusion, the first conduction type deplection type channel area 8, the first heavily doped region 5 with Before third heavily doped region 7, pre-impregnated with hydrogen peroxide is carried out to device, prevents subsequent impurity injection bring damage.The oxide isolation Layer 10 is dense oxide.

In addition, the second conduction type doped region 4 and the injection sequence in deplection type channel area 8 are interchangeable.First heavily doped region 5 It is interchangeable with the second heavily doped region 6 injection sequence.

Optionally, the second conduction type well region 3 of diffusion is formed by multiple ion implanting, wherein rear primary ions injection Energy and dosage be lower than preceding primary ions injection energy and dosage.

Above-described embodiment weakens surface channel and diffusion well region impurity compensation degree, reduces surface depletion channel and leads with JFET Electric channel transitional region width is easy to surface channel pinch off, reduces pinch-off voltage, promotes device constant-current characteristics.Wherein, subsequent can It is formed by the pushing away trap process of short period.

Wherein, Implantation Energy, implantation dosage and the well region spacing for spreading the second conduction type well region 3 can be adjusted suitably It is whole, to obtain suitable the distance between junction depth and two the second conduction type well regions 3 of diffusion, so that vertical-channel and surface depletion Channel region 8 while pinch off, improve the constant-current characteristics of semiconductor devices.

Optionally, before forming the second conduction type well region 3 of diffusion, progress field oxygen on the active area is further comprised the steps of: Oxidation processes form field oxygen.

After above-described embodiment is by doing oxygen process on the scene for the second conduction type well region 3, well region can be made to be subjected to shorter Thermal process reduces impurity lateral diffusion length.

The step of formation field oxygen specifically: carry out silicon wafer initial oxidation and deposit Si3N4, pass through lithography and etching work Skill etches active area, carries out the oxidation of field oxygen, then etching removal Si3N4 and extra oxide layer；

In addition, can wouldn't carry out pushing away trap after diffusion P type trap zone 3 is injected, is realized and pushed away together using subsequent fields oxidation technology Knot and field oxide growth step.

Substrate is lightly doped using the second conduction type in semiconductor devices proposed by the invention, can play assisted depletion two Cellular spreads the effect of the region JFET and its lower zone between the second conduction type well region, accelerates JFET conducting channel and exhausts, Realize lower pinch-off voltage；Using higher energy injection the second conduction type well region of diffusion in manufacturing process, shorten simultaneously The high temperature knot time weakens the second conduction type well region impurity compensation degree of surface depletion channel and diffusion, reduces surface depletion Channel and JFET conducting channel transitional region width are easy to surface channel pinch off, promote device constant current ability；Positioned at the first conduction The second conduction type doped region and substrate, the common assisted depletion epitaxial layer of Metal field plate above type lightly doped epitaxial layer, prolong Better constant current ability and higher breakdown voltage are realized in long electrical wave path.

The length of semiconductor device metal field plate of the present invention, two cellulars spread the second conductive type of trap section away from, second lead The depth and dopant dose and field plate of electric type doped region can be adjusted with the second conduction type doped region relative position Section increases the flexible of device design to realize lower pinch-off voltage, better constant current effect and the specific pressure-resistant demand of satisfaction Property.

In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside", " up time The orientation or positional relationship of the instructions such as needle ", " counterclockwise ", " axial direction ", " radial direction ", " circumferential direction " be orientation based on the figure or Positional relationship is merely for convenience of description of the present invention and simplification of the description, rather than the device or element of indication or suggestion meaning must There must be specific orientation, be constructed and operated in a specific orientation, therefore be not considered as limiting the invention.

In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three It is a etc., unless otherwise specifically defined.

In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc. Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.

In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below " One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.

In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples It closes and combines.

The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.