阅读说明：本技术 功率分配单元电路及用于集成收发机系统的功率分配结构 (Power distributing unit circuit and Distributed Power Architecture for integrating transceiver system ) 是由 马建国 杨圣辉 于 2019-09-24 设计创作，主要内容包括：一种功率分配单元电路及用于集成收发机系统的功率分配结构,包括有N个功率分配单元电路,每一个功率分配单元电路均有一个输入端两个输出端,第一个功率分配单元电路的输入端连接外部输入信号IN,每个功率分配单元电路的两个输出端都分别连接一个功率分配单元电路的输入端,共同构成具有2<Sup>N</Sup>个相同输出的用于集成收发机系统的功率分配结构。本发明的功率分配单元电路及用于集成收发机系统的功率分配结构,可在占用较小芯片面积的情况下实现对信号功率的多通道均等分配。(A kind of power distributing unit circuit and the Distributed Power Architecture for integrating transceiver system, it include N number of power distributing unit circuit, each power distributing unit circuit has two output ends of an input terminal, the input terminal of first power distributing unit circuit connects external input signal IN, two output ends of each power distributing unit circuit are respectively coupled the input terminal of a power distributing unit circuit, collectively form with 2 N The Distributed Power Architecture for being used to integrate transceiver system of a identical output.Power distributing unit circuit of the invention and the Distributed Power Architecture for integrating transceiver system can realize the multichannel equalization distribution to signal power in the case where occupying smaller chip area.)

1. a kind of power distributing unit circuit, which is characterized in that include identical first NMOS transistor (M1) of structure, second NMOS transistor (M2) and third NMOS transistor (M3), first NMOS transistor (M1), the second NMOS transistor (M2) Drain electrode with third NMOS transistor (M3) passes through drain electrode resistive load structure (R_D) power supply is connect, it is resistive that source electrode passes through source electrode Support structures (R_S) ground connection, the input terminal connection of the grid composition power distributing unit circuit of first NMOS transistor (M1) Externally input signal IN, the grid of drain electrode connection the second NMOS transistor (M2), source electrode connect third NMOS transistor (M3) Grid, the drain electrode of second NMOS transistor (M2) passes through the first balance resistance (R1) and is grounded, and source electrode constitutes power distribution One output end OUT1 of element circuit, the source electrode also pass through first resistor (R2) ground connection, the third NMOS transistor (M3) Source electrode by the second balance resistance (R4) be grounded, drain electrode constitute power distributing unit circuit another output OUT2, should Drain electrode is also grounded by second resistance (R3).

2. according to claim 1 a kind of for integrating the extensive Distributed Power Architecture of transceiver system, feature exists In the resistance value of first balance resistance (R1) and the second balance resistance (R4) is 50 ohm.

3. according to claim 1 a kind of for integrating the extensive Distributed Power Architecture of transceiver system, feature exists In the output gain signal Av of the output end OUT1 and output end OUT2 of the power distributing unit circuit₁And Av₂Such as following formula:

Wherein, g_mFor the mutual conductance of each NMOS transistor, R is resistive for each NMOS transistor drain or the concatenated drain electrode of source level The resistance value of support structures or source electrode resistive load structure.

4. a kind of power distribution for being used to integrate transceiver system being made of power distributing unit circuit described in claim 1 Structure, which is characterized in that include N number of power distributing unit circuit (A), each power distributing unit circuit (A) has one The input terminal of two output ends of a input terminal, first power distributing unit circuit (A) connects external input signal IN, Mei Gegong Two output ends of rate allocation unit circuit (A) are respectively coupled the input terminal of a power distributing unit circuit (A), common structure At with 2^NThe Distributed Power Architecture for being used to integrate transceiver system of a identical output.

Technical field

The present invention relates to a kind of Distributed Power Architectures.It is received more particularly to a kind of power distributing unit circuit and for integrated The Distributed Power Architecture of hair machine system.

Background technique

With the development of wireless communication technique, frequency resource day is becoming tight, and communication system starts to extend to higher frequency section, milli Meter wave frequency band possesses abundant frequency resource, while the promotion of frequency is also able to achieve higher transmission rate.However frequency increases Decaying of the electromagnetic wave in propagation medium also increases, so generally requiring through multiple-input and multiple-output (Multiple-Input Multiple-Output, MIMO) antenna array scheme promotes the output power of communication system.

In mimo systems, being assigned to signal power equalization in multiple channels is needed, realizes this power at present The common structure of distribution is Wilkinson power distribution structure, and the major defect of this structure includes caused by being divided equally by power The inherent loss of every level-one power distribution 3dB and it is difficult to the large chip area compressed, so this structure is very uneconomical.Except this with Outside, the structure that Wilkinson structure is combined with power amplifier has also been used in some systems, this structure can be in certain journey It is reduced on degree and is lost and reduces area, but is not significant to the compression effectiveness of area.It thus needs a kind of compact and low-loss Power allocation scheme will be helpful to that system cost can be greatly reduced, and be conducive to the large scale array application of integrated transceiver system.

Summary of the invention

It can be realized in the case where occupying smaller chip area pair the technical problem to be solved by the invention is to provide one kind The power distributing unit circuit that the multichannel equalization of signal power is distributed and the Distributed Power Architecture for integrating transceiver system.

The technical scheme adopted by the invention is that: a kind of power distributing unit circuit includes structure identical first NMOS transistor, the second NMOS transistor and third NMOS transistor, first NMOS transistor, the second NMOS transistor and The drain electrode of third NMOS transistor passes through drain electrode resistive load structure and connects power supply, and source electrode passes through source electrode resistive load structure and connects Ground, the input terminal that the grid of first NMOS transistor constitutes power distributing unit circuit connect externally input signal IN, The grid of drain electrode the second NMOS transistor of connection, source electrode connect the grid of third NMOS transistor, second NMOS transistor Drain electrode by the first balance resistance be grounded, source electrode constitute power distributing unit circuit an output end OUT1, the source electrode is also It is grounded by first resistor, the source electrode of the third NMOS transistor is grounded by the second balance resistance, and drain electrode constitutes power point Another output OUT2 with element circuit, the drain electrode are also grounded by second resistance.

The resistance value of first balance resistance and the second balance resistance (R4) is 50 ohm.

The output gain signal Av of the output end OUT1 and output end OUT2 of the power distributing unit circuit₁And Av₂It is as follows Formula:

Wherein, g_mFor the mutual conductance of each NMOS transistor, R is each NMOS transistor drain or the concatenated drain electrode of source level The resistance value of resistive load structure or source electrode resistive load structure.

A kind of Distributed Power Architecture for being used to integrate transceiver system being made of power distributing unit circuit, includes N A power distributing unit circuit, each power distributing unit circuit have two output ends of an input terminal, first power The input terminal of allocation unit circuit connects external input signal IN, and two output ends of each power distributing unit circuit are distinguished The input terminal for connecting a power distributing unit circuit, collectively forms with 2^NA identical output is used to integrate transceiver system Distributed Power Architecture.

Power distributing unit circuit of the invention and the Distributed Power Architecture for integrating transceiver system, can occupy compared with It is realized in the case where small chip area and the multichannel equalization of signal power is distributed.Beneficial effects of the present invention are as follows:

(1) power distribution is realized using active structure, avoids every grade of 3dB caused by dividing equally as power and inherently damages Consumption, amplifier operation mode consisting of transistors not only can electrode compensation, while also bringing along certain gain.

(2) Distributed Power Architecture based on active structure alleviates core brought by large area passive device significantly Piece area for cutting, reduces chip cost.

(3) it is stringent that the element circuit structure being made of three NMOS transistors theoretically realizes two output end power Equal in magnitude, phase it is consistent, power distribution error is smaller.

(4) the power distributing unit circuit proposed is easy to multi-stage cascade, can realize unit by simple coupled modes The multistage connection of circuit, to realize large-scale multi-channel power distribution.

Detailed description of the invention

Fig. 1 is the composition schematic diagram of power distributing unit circuit of the invention

Fig. 2 is that the circuit of the Distributed Power Architecture for integrating transceiver system of the invention constitutes block diagram.

Specific embodiment

Below with reference to embodiment and attached drawing to power distributing unit circuit of the invention and for integrating transceiver system Distributed Power Architecture is described in detail.

Power distributing unit circuit of the invention, under CMOS technology, by three identical NMOS (N-Metal- Oxide-Semiconductor) transistor composition basic element circuit structure, one of transistor using source level output and Drain output mode and source level output mode is respectively adopted in the dual output mode of drain output, other two transistors.

As shown in Figure 1, power distributing unit circuit of the invention, include the identical first NMOS transistor M1 of structure, Second NMOS transistor M2 and third NMOS transistor M3, the first NMOS transistor M1, the second NMOS transistor M2 and The drain electrode of three NMOS transistor M3 passes through drain electrode resistive load structure R_DPower supply is connect, source electrode passes through source electrode resistive load structure R_SGround connection, the input terminal that the grid of the first NMOS transistor M1 constitutes power distributing unit circuit connect externally input letter Number, the grid of the second NMOS transistor M2 of drain electrode connection, source electrode connects the grid of third NMOS transistor M3, the 2nd NMOS The drain electrode of transistor M2 is grounded by the first balance resistance R1, and source electrode constitutes an output end of power distributing unit circuit OUT1, the source electrode also pass through first resistor R2 and are grounded, and the source electrode of the third NMOS transistor M3 passes through the second balance resistance R4 Ground connection, drain electrode constitute the another output OUT2 of power distributing unit circuit, which also passes through second resistance R3 and be grounded.

The resistance value of the first balance resistance R1 and the second balance resistance R4 are 50 ohm.

The output gain signal Av of the output end OUT1 and output end OUT2 of power distributing unit circuit of the present invention₁With Av₂Such as following formula:

Wherein, g_mFor the mutual conductance of each NMOS transistor, R is each NMOS transistor drain or the concatenated drain electrode of source level The resistance value of resistive load structure or source electrode resistive load structure.

Power distributing unit circuit of the invention provides two output ports, it can be achieved that the power etc. of input signal all the way Point, the signal of final two ports output is within a certain error range watt level is equal, phase is consistent.

As shown in Fig. 2, the power for integrating transceiver system point of the invention being made of power distributing unit circuit Distribution structure, includes N number of power distributing unit circuit A, each power distributing unit circuit A has input terminal two defeated The input terminal of outlet, first power distributing unit circuit A connects external input signal, each power distributing unit circuit A's Two output ends are respectively coupled the input terminal of a power distributing unit circuit A, collectively form with 2^NA identical output For integrating the Distributed Power Architecture of transceiver system.

Power distributing unit circuit through the invention is only attached by simple coupled modes, can be used to receive Extensive power distribution is carried out in hair machine system.The power dividing function that 1:2 can be achieved, continues to cascade on this basis, can be according to It is secondary realize 1:4,1:8 ..., the Distributed Power Architecture of 1:N, since main body is made of active device in the Distributed Power Architecture, Comprising minute quantity passive device, thus big N value can be achieved under lesser chip area.