阅读说明：本技术 一种主从mcu内外多重监视定时器协同复位的系统及方法 (System and method for cooperatively resetting internal and external multiple monitoring timers of master-slave MCU (microprogrammed control Unit) ) 是由 高连鹏 王诗涵 于 2019-09-05 设计创作，主要内容包括：本发明提供一种主从MCU内外多重监视定时器协同复位的系统,包括：主MCU芯片、从MCU芯片、监视定时器复位电路和电源电路。主MCU芯片采用Cortex-M4架构的STM32F407ZGT6芯片；Cortex-M4架构的STM32F407ZGT6芯片通用GPIO口线与从MCU的通用GPIO口线1连接,向从MCU发送固定频率的脉冲信号；芯片的nRST引脚为低电平复位引脚,与从MCU的通用GPIO口线2连接,接收从MCU的复位控制信号并与从MCU通过SPI接口进行通信。本发明在主从MCU协同工作的系统下,主从内外4重监视定时器协同工作,分别对主从MCU进行监视,在MCU工作异常时及时进行复位。其中由从MCU对主MCU进行外部复位控制,可灵活调整监视定时器溢出时间,有效解决了执行复杂任务的主MCU从上电到可以启动内置监视定时器期间发生工作异常导致系统无法复位的问题。(The invention provides a system for cooperatively resetting multiple internal and external monitoring timers of a master MCU (microprogrammed control Unit) and a slave MCU (microprogrammed control Unit), which comprises the following components: the device comprises a master MCU chip, a slave MCU chip, a monitoring timer reset circuit and a power supply circuit. The main MCU chip adopts an STM32F407ZGT6 chip with a Cortex-M4 framework; the general GPIO port line of the STM32F407ZGT6 chip of the Cortex-M4 architecture is connected with the general GPIO port line 1 of the slave MCU, and sends a pulse signal with fixed frequency to the slave MCU; and the nRST pin of the chip is a low-level reset pin, is connected with the general GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI (serial peripheral interface). In the invention, under a system with cooperative work of a master MCU and a slave MCU, 4-time monitoring timers inside and outside the master MCU and the slave MCU are cooperatively worked to respectively monitor the master MCU and the slave MCU and reset in time when the MCU works abnormally. The slave MCU is used for carrying out external reset control on the master MCU, the overflow time of the monitoring timer can be flexibly adjusted, and the problem that the system cannot be reset due to abnormal work during the period from power-on to starting of the built-in monitoring timer of the master MCU which executes complex tasks is effectively solved.)

1. A system for the cooperative reset of multiple internal and external monitoring timers of a master MCU and a slave MCU is characterized by comprising: the monitoring system comprises a master MCU chip, a slave MCU chip, a monitoring timer reset circuit and a power supply circuit;

The main MCU chip adopts an STM32F407ZGT6 chip with a Cortex-M4 framework; the STM32F407ZGT6 chip general purpose GPIO port line of the Cortex-M4 architecture is connected with the general purpose GPIO port line 1 of the slave MCU, and a pulse signal with fixed frequency is sent to the slave MCU; and the nRST pin of the chip is a low-level reset pin, is connected with the general GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI (serial peripheral interface).

2. the system according to claim 1, wherein said master-slave MCU is further characterized by:

The slave MCU chip adopts an STM32F103RCT6 chip of a Cortex-M3 framework; the general GPIO port 3 of the STM32F103RCT6 chip of the Cortex-M3 architecture is connected with a WDI pin of the monitoring timer reset circuit and used for sending a pulse signal with fixed frequency to the monitoring timer reset circuit, and the nRST pin is a low-level reset pin and connected with a pin of the monitoring timer reset circuit and used for receiving a reset control signal of the monitoring timer reset circuit.

3. A system for cooperative reset of multiple watchdog timers within and outside a master-slave MCU according to claim 1 or 2, further characterized by:

The monitoring timer reset circuit adopts a TPS3828 monitoring timer reset chip to provide timing monitoring and reset control with the overflow time of 1.6s for the slave MCU.

4. The system according to claim 1, wherein said master-slave MCU is further characterized by:

The power supply circuit comprises 2 SPX5205 linear voltage stabilizing chips, and 5.0V voltage is converted into 3.3V voltage to provide working power supply for the master/slave MCU chip and the monitoring timer reset circuit.

5. A method for using a master-slave MCU internal-external multi-watchdog timer in a system according to any of claims 1-4, comprising the steps of:

S1: setting a quadruple monitoring timer, and monitoring the master/slave MCU chip and the monitoring timer reset circuit in real time;

S2: judging whether the master/slave MCU chip needs to be reset or not through the quadruple monitoring timer;

S3: and resetting the master/slave MCU chip.

6. The method of claim 1, wherein the master-slave MCU is configured to perform a cooperative reset of internal and external multi-watchdog timers, further comprising:

the quadruple watchdog timer comprises: the MCU chip comprises a master MCU chip built-in monitoring timer, a slave MCU chip monitoring timer for the master MCU chip, a slave MCU chip built-in monitoring timer and an external monitoring timer reset circuit monitoring timer for the slave MCU.

7. The method of claim 6, wherein the master-slave MCU is further characterized by a cooperative reset of internal and external multi-watchdog timers: the main MCU chip is internally provided with a monitoring timer: when the main MCU chip works normally, clearing a built-in monitoring timer in a working cycle, if the duration of the built-in monitoring timer exceeds 13S, overflowing the built-in monitoring timer, judging that the main MCU chip is in an abnormal working state, and executing the step S3.

8. The method of claim 6, wherein the master-slave MCU is further characterized by a cooperative reset of internal and external multi-watchdog timers: the slave MCU chip monitors the master MCU chip for a timer: when the master MCU chip works normally, continuously transmitting a pulse signal with the frequency of 10Hz to the slave MCU chip; if the slave MCU chip does not detect the pulse signal after exceeding 3S, the master MCU is judged to be in an abnormal working state, reset is carried out by pulling down the reset pin of the master MCU, the overflow time is prolonged to 30S, the step S3 is executed, and the time is shortened to 3S after the master MCU enters a normal working state.

9. The method of claim 6, wherein the master-slave MCU is further characterized by a cooperative reset of internal and external multi-watchdog timers: the slave MCU is internally provided with a monitoring timer: if the slave MCU is operating normally, the built-in watchdog timer is cleared within the operation cycle thereof, and if this operation is not performed for more than 13 seconds, the built-in watchdog timer overflows, and it is determined that the slave MCU is in an abnormal operation state, and the above-described step S3 is executed.

10. the method of claim 6, wherein the master-slave MCU is further characterized by a cooperative reset of internal and external multi-watchdog timers: the external monitoring timer reset circuit is used for monitoring the timer of the slave MCU: when the slave MCU works normally, a pulse signal with the frequency of 100Hz is continuously sent to the reset circuit of the monitoring timer, if the pulse signal is not detected when the reset circuit of the monitoring timer exceeds 1.6s, the slave MCU is judged to be in an abnormal working state, and the reset pin of the slave MCU is pulled down to reset the slave MCU.

Technical Field

The invention relates to the technical field of cooperative resetting of multiple monitoring timers, in particular to a system and a method for cooperative resetting of the multiple monitoring timers inside and outside a master MCU and a slave MCU.

background

The internal reset process for the microprocessor in the current technology generally comprises: when the microprocessor works normally, the built-in monitoring timer is cleared according to the set time interval, and if the monitoring timer is not cleared within the overflow time, the microprocessor automatically resets. However, the disadvantages of this approach are: the time required by the microprocessor for executing complex tasks from power-on to the time required by starting the built-in monitoring timer and outputting a signal for clearing the monitoring timer is longer, and if abnormal working conditions such as program running and the like occur in the period, the microprocessor cannot be timely reset, so that system paralysis is caused.

meanwhile, in the current technology, the external reset process of the microprocessor generally comprises the following steps: when the microprocessor works normally, a clear monitoring timer signal with fixed frequency is sent to an external monitoring timer reset circuit, and if the external monitoring timer reset circuit does not receive the clear monitoring timer signal within the overflow time, the microprocessor is judged to work abnormally, and reset control is carried out on the microprocessor. The disadvantages of this approach are: the overflow time of the monitoring timer is not adjustable, the flexibility is low, and the system with a plurality of microprocessors working cooperatively needs the same number of monitoring timer reset circuits, occupies the area resources of a printed circuit board, and increases the wiring difficulty and the system cost.

Disclosure of Invention

In light of the above-mentioned technical problems, a system and method for cooperatively resetting multiple internal and external watchdog timers of a master MCU and a slave MCU are provided. The invention mainly utilizes a system for cooperatively resetting a master-slave MCU internal and external multiple monitoring timer, which is characterized by comprising: the device comprises a master MCU chip, a slave MCU chip, a monitoring timer reset circuit and a power supply circuit.

Further, the main MCU chip adopts an STM32F407ZGT6 chip of a Cortex-M4 architecture; the STM32F407ZGT6 chip general purpose GPIO port line of the Cortex-M4 architecture is connected with the general purpose GPIO port line 1 of the slave MCU, and a pulse signal with fixed frequency is sent to the slave MCU; and the nRST pin of the chip is a low-level reset pin, is connected with the general GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI (serial peripheral interface).

Furthermore, the slave MCU chip adopts an STM32F103RCT6 chip of Cortex-M3 architecture; the general GPIO port 3 of the STM32F103RCT6 chip of the Cortex-M3 architecture is connected with a WDI pin of the monitoring timer reset circuit and used for sending a pulse signal with fixed frequency to the monitoring timer reset circuit, and the nRST pin is a low-level reset pin and connected with a pin of the monitoring timer reset circuit and used for receiving a reset control signal of the monitoring timer reset circuit.

Further, the monitoring timer reset circuit adopts a TPS3828 monitoring timer reset chip to provide timing monitoring and reset control with the overflow time of 1.6s for the slave MCU.

Furthermore, the power supply circuit comprises 2 SPX5205 linear voltage stabilizing chips, and 5.0V voltage is converted into 3.3V voltage to provide working power supply for the master/slave MCU chip and the monitoring timer reset circuit.

The invention also comprises a method for cooperatively resetting the internal and external multiple monitoring timers of the master MCU and the slave MCU, which is characterized by comprising the following steps of:

Step S1: setting a quadruple monitoring timer, and monitoring the master/slave MCU chip and the monitoring timer reset circuit in real time;

Step S2: judging whether the master/slave MCU chip needs to be reset or not through the quadruple monitoring timer;

step S3: and resetting the master/slave MCU chip.

Further, the quadruple watchdog timer comprises: the MCU chip comprises a master MCU chip built-in monitoring timer, a slave MCU chip monitoring timer for the master MCU chip, a slave MCU chip built-in monitoring timer and an external monitoring timer reset circuit monitoring timer for the slave MCU.

Further, the master MCU chip has built-in monitoring timer: when the main MCU chip works normally, clearing a built-in monitoring timer in a working cycle, if the duration of the built-in monitoring timer exceeds 13S, overflowing the built-in monitoring timer, judging that the main MCU chip is in an abnormal working state, and executing the step S3.

Further, the slave MCU chip monitors the master MCU chip for: when the master MCU chip works normally, continuously transmitting a pulse signal with the frequency of 10Hz to the slave MCU chip; if the slave MCU chip does not detect the pulse signal after exceeding 3S, the master MCU is judged to be in an abnormal working state, reset is carried out by pulling down the reset pin of the master MCU, the overflow time is prolonged to 30S, the step S3 is executed, and the time is shortened to 3S after the master MCU enters a normal working state.

Further, the slave MCU has built-in monitoring timer: if the slave MCU is operating normally, the built-in watchdog timer is cleared within the operation cycle thereof, and if this operation is not performed for more than 13 seconds, the built-in watchdog timer overflows, and it is determined that the slave MCU is in an abnormal operation state, and the above-described step S3 is executed.

Further, the external watchdog reset circuit resets the watchdog timer of the slave MCU: when the slave MCU works normally, a pulse signal with the frequency of 100Hz is continuously sent to the reset circuit of the monitoring timer, if the pulse signal is not detected when the reset circuit of the monitoring timer exceeds 1.6s, the slave MCU is judged to be in an abnormal working state, and the reset pin of the slave MCU is pulled down to reset the slave MCU.

Compared with the prior art, the invention has the following advantages:

In the invention, under a system with cooperative work of a master MCU and a slave MCU, 4-time monitoring timers inside and outside the master MCU and the slave MCU are cooperatively worked to respectively monitor the master MCU and the slave MCU and reset in time when the MCU works abnormally. The slave MCU is used for carrying out external reset control on the master MCU, the overflow time of the monitoring timer can be flexibly adjusted, the problem that the system cannot be reset due to abnormal work during the period from power-on to starting of the built-in monitoring timer of the master MCU which executes complex tasks is effectively solved, and the reliability of the system is improved.

Meanwhile, only 1 external monitoring timer reset chip is used, so that the occupation of the area resources of the printed circuit board is effectively reduced, and the wiring difficulty and the system cost are reduced.

Drawings

in order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a circuit module according to the present invention;

Fig. 2 is a block diagram of the cooperative operation of multiple watchdog timers in accordance with the present invention.

Detailed Description

in order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As shown in fig. 1-2, the present invention provides a system for cooperatively resetting multiple internal and external watchdog timers of a master MCU and a slave MCU, comprising: the device comprises a master MCU chip, a slave MCU chip, a monitoring timer reset circuit and a power supply circuit. It is understood that in other embodiments, the synchronous reset system described herein may further include a feedback circuit or a recording circuit, as long as it is sufficient to implement multiple monitoring and resetting.

In a preferred embodiment, the main MCU chip adopts an STM32F407ZGT6 chip of a Cortex-M4 architecture; the STM32F407ZGT6 chip general purpose GPIO port line of the Cortex-M4 architecture is connected with the general purpose GPIO port line 1 of the slave MCU, and a pulse signal with fixed frequency is sent to the slave MCU; and the nRST pin of the chip is a low-level reset pin, is connected with the general GPIO port line 2 of the slave MCU, receives a reset control signal of the slave MCU and communicates with the slave MCU through an SPI (serial peripheral interface).

in a preferred embodiment, the slave MCU chip adopts an STM32F103RCT6 chip of Cortex-M3 architecture; the general GPIO port 3 of the STM32F103RCT6 chip of the Cortex-M3 architecture is connected with a WDI pin of the monitoring timer reset circuit and used for sending a pulse signal with fixed frequency to the monitoring timer reset circuit, and the nRST pin is a low-level reset pin and connected with a pin of the monitoring timer reset circuit and used for receiving a reset control signal of the monitoring timer reset circuit.

In the application, the monitoring timer reset circuit adopts a TPS3828 monitoring timer reset chip to provide timing monitoring and reset control with the overflow time of 1.6s for the slave MCU. The power supply circuit comprises 2 SPX5205 linear voltage stabilizing chips, and 5.0V voltage is converted into 3.3V voltage to provide working power supply for the master/slave MCU chip and the monitoring timer reset circuit.

meanwhile, as a preferred implementation mode, the invention also comprises a method for cooperatively resetting the internal and external multiple monitoring timers of the master-slave MCU, which comprises the following steps:

Step S1: setting a quadruple monitoring timer, and monitoring the master/slave MCU chip and the monitoring timer reset circuit in real time;

Step S2: judging whether the master/slave MCU chip needs to be reset or not through the quadruple monitoring timer;

step S3: and resetting the master/slave MCU chip.

as a preferred embodiment, the quadruple watchdog timer comprises: the MCU chip comprises a master MCU chip built-in monitoring timer, a slave MCU chip monitoring timer for the master MCU chip, a slave MCU chip built-in monitoring timer and an external monitoring timer reset circuit monitoring timer for the slave MCU.

In this embodiment, the main MCU chip incorporates a monitoring timer: when the main MCU chip works normally, clearing a built-in monitoring timer in a working cycle, if the duration of the built-in monitoring timer exceeds 13S, overflowing the built-in monitoring timer, judging that the main MCU chip is in an abnormal working state, and executing the step S3.

as a preferred embodiment, the slave MCU chip monitors the master MCU chip for: when the master MCU chip works normally, continuously transmitting a pulse signal with the frequency of 10Hz to the slave MCU chip; if the slave MCU chip does not detect the pulse signal after exceeding 3S, the master MCU is judged to be in an abnormal working state, reset is carried out by pulling down the reset pin of the master MCU, the overflow time is prolonged to 30S, the step S3 is executed, and the time is shortened to 3S after the master MCU enters a normal working state.

in this application, the slave MCU has built therein a watchdog timer: if the slave MCU is operating normally, the built-in watchdog timer is cleared within the operation cycle thereof, and if this operation is not performed for more than 13 seconds, the built-in watchdog timer overflows, and it is determined that the slave MCU is in an abnormal operation state, and the above-described step S3 is executed.

As a preferred embodiment, the external watchdog reset circuit resets the watchdog timer of the slave MCU: when the slave MCU works normally, a pulse signal with the frequency of 100Hz is continuously sent to the reset circuit of the monitoring timer, if the pulse signal is not detected when the reset circuit of the monitoring timer exceeds 1.6s, the slave MCU is judged to be in an abnormal working state, and the reset pin of the slave MCU is pulled down to reset the slave MCU.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

in the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

in the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.