阅读说明：本技术 一种关于内存adddc功能的测试方法、系统及设备 (test method, system and equipment for memory ADDDC function ) 是由 刘学艳 于 2019-07-26 设计创作，主要内容包括：本发明提出的一种关于内存ADDDC功能的测试方法、系统及设备,主要用于服务器内存ADDDC功能测试,通过模拟内存故障情形,验证ADDDC功能是否正常。即可提高测试效率,提高测试质量也同时节约测试时间和成本。(the invention provides a method, a system and equipment for testing a memory ADDDC function, which are mainly used for testing the memory ADDDC function of a server, and verifying whether the memory ADDDC function is normal or not by simulating the memory fault condition. The testing efficiency can be improved, the testing quality is improved, and the testing time and the testing cost are saved.)

1. A method for testing a function of a memory ADDDC, comprising:

Entering a Set up of a machine to be tested, configuring test environment parameters and restarting a system;

appointing the memory device register address of the tested machine, injecting repairable errors into the memory device register address and checking error record logs in a system log and a BMC log;

If the system is not abnormal due to the memory failure and the injected repairable error is recorded in the error log in the BMC log, the test is successful.

2. The method of claim 1, wherein configuring test environment parameters at Set up into the machine under test comprises:

setting ADDDC spacing and SDDC plus one as Enable;

Setting a correct Error Threshold to be 1;

setting System Errors as Enable;

Setting WHEA Support as Enable;

WHEA Error Injection is set to Enable.

3. The method of claim 1, wherein specifying and injecting a repairable error into a memory device register address of a machine under test and viewing error log records in a system log and a BMC log comprises:

Appointing a first address of a register of the memory device and injecting a repairable error into a first Bank of the memory, wherein the repairable error reaches a threshold value to trigger a Bank virtual lockstep;

and checking the abnormal memory fault records in the system log, and checking the ADC Bank VLS log recorded in the system log and the BMC log.

4. The method of claim 3, wherein the specifying and injecting the memory device register address of the machine under test into the error log and checking the error log in the system log and the BMC log further comprises:

Appointing a second address of a register of the memory device and injecting a repairable error into a second Bank of the memory, wherein the repairable error reaches a threshold value to trigger a Rank virtual lockstep;

and checking the abnormal record of the memory fault in the system log, and checking the ADC Rank VLS log recorded in the system log and the BMC log.

5. the method of claim 4, wherein specifying and injecting repairable errors into memory device register addresses of the machine under test and viewing error log records in the system log and the BMC log further comprises:

Appointing a third address of a register of the memory device and injecting a repairable error into a third Bank of the memory, wherein the repairable error reaches a threshold value to trigger SDDC sparing;

and checking the memory fault restart record in the system log, and checking the SDDC +1 log recorded in the system log and the BMC log.

6. the method of claim 5, wherein the first address, the second address, and the third address are different; the first Bank, the second Bank and the third Bank are different from each other.

7. a system for testing a function of a memory ADDDC, comprising:

The parameter configuration module is used for configuring test environment parameters under the Set up of the tested machine;

The data injection module is used for appointing the memory equipment register address of the tested machine and injecting repairable errors into the memory equipment register address;

And the information viewing module is used for viewing error record logs in the system log and the BMC log.

8. A test apparatus for memory ADDDC functionality, comprising:

A memory for storing a computer program;

A processor for implementing the steps of the method for testing the function of the ADDDC according to any one of claims 1 to 6 when executing the computer program.

Technical Field

The invention relates to the technical field of computer networks, in particular to a method, a system and equipment for testing an ADDDC function of a memory.

background

ADDDC is an adaptive dual DRAM device correction technique to manage errors that DDR4DRAM DIMMs may induce during the product lifetime, and ADDDC (mr) can correct two consecutive DRAM failures. If a second device of the zone fails, repairable error detection and correction is still supported and the system is allowed to continue to operate.

With the advent of ADDDC, memory subsystems are typically configured to operate in a performance mode. When the correction amount of the DRAM device reaches the target threshold, the identified defective DRAM regions will be adaptively placed in lockstep mode with the help of UEFI runtime code to mark the defective regions of the DRAM device from the ECC. SDDC ECC coverage continues to be provided on DIMMs, thereby extending the life of DIMMs. This operation is typically performed during the refinement of the DRAM Bank and/or Rank to minimize the impact on overall system performance.

therefore, in order to ensure stable execution of the ADDDC, a testing method of the ADDDC function is urgently needed for verifying the ADDDC function when the server is shipped.

disclosure of Invention

in view of the above problems, an object of the present invention is to provide a method, system and device for testing ADDDC function of a memory, which can verify whether the ADDDC function is normal by simulating a memory failure condition.

in order to achieve the purpose, the invention is realized by the following technical scheme: a method of testing for memory ADDDC functionality, comprising:

entering a Set up of a machine to be tested, configuring test environment parameters and restarting a system;

appointing the memory device register address of the tested machine, injecting repairable errors into the memory device register address and checking error record logs in a system log and a BMC log;

If the system is not abnormal due to the memory failure and the injected repairable error is recorded in the error log in the BMC log, the test is successful.

further, configuring the testing environment parameters under the Set up entering the tested machine includes:

Setting ADDDC spacing and SDDC plus one as Enable;

setting a correct Error Threshold to be 1;

Setting System Errors as Enable;

setting WHEA Support as Enable;

WHEA Error Injection is set to Enable.

Further, the specifying the memory device register address of the tested machine and injecting the repairable error into the memory device register address and checking the error log in the system log and the BMC log includes:

Appointing a first address of a register of the memory device and injecting a repairable error into a first Bank of the memory, wherein the repairable error reaches a threshold value to trigger a Bank virtual lockstep;

And checking the abnormal memory fault records in the system log, and checking the ADC Bank VLS log recorded in the system log and the BMC log.

Further, the specifying the memory device register address of the tested machine and injecting the repairable error into the memory device register address and checking the error log in the system log and the BMC log further includes:

appointing a second address of a register of the memory device and injecting a repairable error into a second Bank of the memory, wherein the repairable error reaches a threshold value to trigger a Rank virtual lockstep;

and checking the abnormal record of the memory fault in the system log, and checking the ADC Rank VLS log recorded in the system log and the BMC log.

further, the specifying the memory device register address of the tested machine and injecting the repairable error into the memory device register address and checking the error log in the system log and the BMC log further includes:

Appointing a third address of a register of the memory device and injecting a repairable error into a third Bank of the memory, wherein the repairable error reaches a threshold value to trigger SDDC sparing;

And checking the memory fault restart record in the system log, and checking the SDDC +1 log recorded in the system log and the BMC log.

Further, the first address, the second address and the third address are different; the first Bank, the second Bank and the third Bank are different from each other.

Correspondingly, the invention also discloses a test system for the function of the memory ADDDC, which comprises:

The parameter configuration module is used for configuring test environment parameters under the Set up of the tested machine;

the data injection module is used for appointing the memory equipment register address of the tested machine and injecting repairable errors into the memory equipment register address;

And the information viewing module is used for viewing error record logs in the system log and the BMC log.

Correspondingly, the invention also discloses a test device related to the function of the memory ADDDC, which comprises:

a memory for storing a computer program;

A processor for implementing the steps of the method for testing the function of the ADDDC according to any of the above embodiments when the computer program is executed.

Compared with the prior art, the invention has the beneficial effects that: the invention provides a method, a system and equipment for testing an ADDDC function of a memory, which are mainly used for testing the ADDDC function of a server memory and verifying whether the ADDDC function is normal or not by simulating the fault condition of the memory. The testing efficiency can be improved, the testing quality is improved, and the testing time and the testing cost are saved.

therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.

drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a flow chart of the method of the present invention.

fig. 2 is a system block diagram of the present invention.

Detailed Description

the following description of the embodiments of the present invention will be made with reference to the accompanying drawings.

the method for deriving the MAC address of a multi-node machine shown in fig. 1 includes the following steps:

step 1: and (5) entering the Set up of the tested machine, configuring the testing environment parameters and restarting the system.

Configuring test environment parameters includes:

Setting ADDDC spacing and SDDC plus one as Enable;

Setting a correct Error Threshold to be 1;

setting System Errors as Enable;

setting WHEA Support as Enable;

WHEA Error Injection is set to Enable.

step 2: and appointing a first address of a register of the memory device and injecting a repairable error into a first Bank of the memory, wherein the repairable error reaches a threshold value to trigger a Bank virtual lockstep.

and step 3: and checking the abnormal memory fault records in the system log, and checking the ADC Bank VLS log recorded in the system log and the BMC log.

and 4, step 4: and appointing a second address of the register of the memory device and injecting a repairable error into a second Bank of the memory, wherein the repairable error reaches a threshold value to trigger a Rank virtual lockstep.

and 5: and checking the abnormal record of the memory fault in the system log, and checking the ADC Rank VLS log recorded in the system log and the BMC log.

Step 6: appointing a third address of a register of the memory device and injecting a repairable error into a third Bank of the memory, wherein the repairable error reaches a threshold value to trigger SDDC sparing;

And 7: and checking the memory fault restart record in the system log, and checking the SDDC +1 log recorded in the system log and the BMC log.

Wherein the first address, the second address and the third address are different from each other; the first Bank, the second Bank and the third Bank are different from each other.

And 8: if the system is not abnormal due to the memory fault and the injected repairable errors are recorded in an ADC Rank VLS log, an ADC Rank VLS log and an SDDC +1 log in the BMC log respectively, the test is successful.

Correspondingly, as shown in fig. 2, the present invention also discloses a system for testing the function of the memory ADDDC, which includes:

the parameter configuration module is used for configuring test environment parameters under the Set up of the tested machine;

The data injection module is used for appointing the memory equipment register address of the tested machine and injecting repairable errors into the memory equipment register address;

And the information viewing module is used for viewing error record logs in the system log and the BMC log.

Correspondingly, the invention also discloses a test device related to the memory ADDDC function, which comprises:

a memory for storing a computer program;

a processor for implementing the steps of the method for testing the function of the ADDDC according to any of the above embodiments when the computer program is executed.

those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented as software plus a required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention. The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant points can be referred to the description in the method embodiment.

in the embodiments provided by the present invention, it should be understood that the disclosed system, system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit.

the invention is further described with reference to the accompanying drawings and specific embodiments. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and these equivalents also fall within the scope of the present application.