阅读说明：本技术 一种高速大面阵红外成像电路 (High-speed large-area-array infrared imaging circuit ) 是由 苗壮 李宁珍 龚瑞 关智聪 刘菁菁 龚文 张丰收 许羽 于 2021-06-25 设计创作，主要内容包括：本发明公开了一种高速大面阵红外成像电路,包括滤波电路、一级运放电路、二级运放电路、多通道高速AD转换电路、处理器FPGA；其中,处理器FPGA完成探测器及多通道高速AD转换电路的配置,使探测器正常输出图像信号,多通道高速AD能够开始采集信号；滤波电路将原始图像信号低通滤波后发送至一级运放电路；一级运放电路将滤波后的信号进行跟随及偏置；二级运放电路将一级运放处理的信号进行比例缩放及差分变换；多通道高速AD转换电路采集差分信号并数字化送至处理器FPGA；处理器FPGA采集多通道高速AD转换电路的数据,打包后送至下一级系统。本发明减少图像采集噪声,提高图像采集速度,提高产品的灵敏域。(The invention discloses a high-speed large-area-array infrared imaging circuit which comprises a filter circuit, a primary operational amplifier circuit, a secondary operational amplifier circuit, a multi-channel high-speed AD conversion circuit and a processor FPGA; the FPGA completes the configuration of the detector and the multi-channel high-speed AD conversion circuit, so that the detector normally outputs image signals, and the multi-channel high-speed AD can start to acquire the signals; the filtering circuit low-pass filters the original image signal and then sends the filtered image signal to the first-stage operational amplifier circuit; the first-stage operational amplifier circuit follows and biases the filtered signal; the second-stage operational amplifier circuit performs scaling and differential conversion on the signals processed by the first-stage operational amplifier; the multi-channel high-speed AD conversion circuit collects differential signals and digitalizes the signals to be sent to the FPGA; and the FPGA acquires data of the multi-channel high-speed AD conversion circuit, packages the data and sends the data to a next-stage system. The invention reduces the image acquisition noise, improves the image acquisition speed and improves the sensitive domain of the product.)

1. A high-speed large-area array infrared imaging circuit is characterized by comprising: the device comprises a filter circuit, a primary operational amplifier circuit, a secondary operational amplifier circuit, a multi-channel high-speed AD conversion circuit and a processor FPGA; wherein the content of the first and second substances,

the filter circuit filters the output signal of the detector to obtain a filtered signal and sends the filtered signal to the first-stage operational amplifier circuit; the first-stage operational amplifier circuit carries out direct current bias and isolation on the filtered signal to obtain a biased signal, and the biased signal is sent to the second-stage operational amplifier circuit; the second-stage operational amplifier circuit performs scaling and differential conversion on the biased signals to obtain differential signals, and the differential signals are sent to the multi-channel high-speed AD conversion circuit; and the multi-channel high-speed AD conversion circuit performs analog-to-digital conversion on the differential signal and then sends the differential signal to the FPGA.

2. The high-speed large-area-array infrared imaging circuit according to claim 1, characterized in that: the filter circuit comprises a capacitor C100, a resistor R1, a capacitor C101, a resistor R4, a capacitor C102, a resistor R11, a capacitor C103 and a resistor R14; wherein the content of the first and second substances,

the anode of the capacitor C100 and the anode of the resistor R1 are both connected with the pin 3 of the N1A of the primary operational amplifier circuit, and the cathode of the capacitor C100 and the cathode of the resistor R1 are both connected with GND _ TCQ;

the anode of the capacitor C101 and the anode of the resistor R4 are both connected with the pin 10 of the N1C of the primary operational amplifier circuit, and the cathode of the capacitor C101 and the cathode of the resistor R4 are both connected with GND _ TCQ;

the anode of the capacitor C102 and the anode of the resistor R11 are both connected with the pin 3 of the N2A of the primary operational amplifier circuit, and the cathode of the capacitor C102 and the cathode of the resistor R11 are both connected with GND _ TCQ;

the anode of the capacitor C103 and the anode of the resistor R14 are both connected with the pin 3 of the N1A of the primary operational amplifier circuit, and the cathode of the capacitor C103 and the cathode of the resistor R14 are both connected with GND _ TCQ.

3. The high-speed large-area-array infrared imaging circuit according to claim 1, characterized in that: the primary operational amplifier circuit comprises an operational amplifier N1A, an operational amplifier N1B, a resistor R7, a resistor R8, a capacitor C1, a capacitor C7, an operational amplifier N1C, an operational amplifier N1D, a resistor R9, a resistor R10, a capacitor C8, an operational amplifier N2A, an operational amplifier N2B, a resistor R17, a resistor R18, a capacitor C4, a capacitor C9, an operational amplifier N2C, an operational amplifier N2D, a resistor R19, a resistor R20 and a capacitor C10; wherein the content of the first and second substances,

a pin 2 of the operational amplifier N1A is connected with the cathode of a resistor R7, a pin 4 of the operational amplifier N1A is respectively connected with the power supply VC and the anode of a capacitor C1, a pin 1 of the operational amplifier N1A is respectively connected with the anode of a resistor R7 and the anode of a resistor R29, and a pin 11 of the operational amplifier N1A is respectively connected with GND _ TCQ and the cathode of a capacitor C7; the negative electrode of the capacitor C1 is connected with GND _ TCQ; the positive electrode of the capacitor C7 is respectively connected with a direct current bias VF and a pin 5 of an operational amplifier N1B; the 6 pins of the operational amplifier N1B are connected with the cathode of the resistor R8, and the 7 pins of the operational amplifier N1B are respectively connected with the anode of the resistor R8 and the anode of the resistor R30;

a pin 9 of the operational amplifier N1C is connected with a cathode of a resistor R9, a pin 8 of the operational amplifier N1C is respectively connected with an anode of the resistor R9 and an anode of the resistor R31, an anode of a capacitor C8 is respectively connected with a direct current bias VF and a pin 12 of the operational amplifier N1D, a cathode of the capacitor C8 is connected with GND _ TCQ, a pin 13 of the operational amplifier N1D is connected with a cathode of a resistor R10, and a pin 14 of the operational amplifier N1D is respectively connected with an anode of the resistor R10 and an anode of the resistor R32;

a pin 2 of the operational amplifier N2A is connected with the cathode of a resistor R17, a pin 4 of the operational amplifier N2A is respectively connected with the power supply VC and the anode of a capacitor C4, a pin 1 of the operational amplifier N2A is respectively connected with the anode of a resistor R17 and the anode of a resistor R33, and a pin 11 of the operational amplifier N2A is respectively connected with GND _ TCQ and the cathode of a capacitor C9; the negative electrode of the capacitor C4 is connected with GND _ TCQ; the positive electrode of the capacitor C9 is connected with a direct current bias VF and a pin 5 of an operational amplifier N2B; the pin 6 of the operational amplifier N2B is connected with the cathode of the resistor R18, and the pin 7 of the operational amplifier N2B is respectively connected with the anode of the resistor R18 and the anode of the resistor R34;

the pin 9 of the operational amplifier N2C is connected with the cathode of the resistor R19, the pin 8 of the operational amplifier N2C is connected with the anode of the resistor R19 and the anode of the resistor R35 respectively, the anode of the capacitor C10 is connected with the direct current bias VF and the pin 12 of the operational amplifier N2D respectively, the cathode of the capacitor C10 is connected with GND _ TCQ, the pin 13 of the operational amplifier N1D is connected with the cathode of the resistor R20, and the pin 14 of the operational amplifier N1D is connected with the anode of the resistor R20 and the anode of the resistor R36 respectively.

4. The high-speed large-area-array infrared imaging circuit according to claim 1, characterized in that: the secondary operational amplifier circuit comprises a differential operational amplifier circuit N3, a resistor R21, a resistor R22, a resistor R29, a resistor R30, a capacitor C11, a capacitor C2, a differential operational amplifier circuit N4, a resistor R23, a resistor R24, a resistor R31, a resistor R32, a capacitor C12, a capacitor C3, a differential operational amplifier circuit N5, a resistor R25, a resistor R26, a resistor R33, a resistor R34, a capacitor C13, a capacitor C5, a differential operational amplifier circuit N6, a resistor R27, a resistor R28, a resistor R35, a resistor R36, a capacitor C14 and a capacitor C6; wherein the content of the first and second substances,

a pin 1 of the differential operational amplifier circuit N3 is respectively connected with a cathode of a resistor R30 and an anode of a resistor R22, a pin 2 of the differential operational amplifier circuit N3 is respectively connected with an anode of a capacitor C11 and an anode of a resistor R45, a pin 3 of the differential operational amplifier circuit N3 is respectively connected with a power supply VC and an anode of a capacitor C2, a pin 4 of the differential operational amplifier circuit N3 is respectively connected with a cathode of a resistor R22 and an anode of a resistor R61, a pin 5 of the differential operational amplifier circuit N3 is respectively connected with a cathode of a resistor R21 and an anode of a resistor R60, a pin 6 of the differential operational amplifier circuit N3 is connected with GND _ TCQ, a pin 7 of the differential operational amplifier circuit N3 is suspended, and a pin 8 of the differential operational amplifier circuit N3 is respectively connected with a cathode of a resistor R29 and an anode of a resistor R21; the negative electrode of the capacitor C13 and the negative electrode of the capacitor C5 are both connected with GND _ TCQ;

a pin 1 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R32 and an anode of a resistor R24, a pin 2 of the differential operational amplifier circuit N4 is respectively connected with an anode of a capacitor C12 and an anode of a resistor R45, a pin 3 of the differential operational amplifier circuit N4 is respectively connected with a power supply VC and an anode of a capacitor C3, a pin 4 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R22 and an anode of a resistor R62, a pin 5 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R23 and an anode of a resistor R63, a pin 6 of the differential operational amplifier circuit N4 is connected with GND _ TCQ, a pin 7 of the differential operational amplifier circuit N4 is suspended, and a pin 8 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R31 and an anode of a resistor R23; the negative electrode of the capacitor C12 and the negative electrode of the capacitor C3 are both connected with GND _ TCQ;

a pin 1 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R34 and an anode of a resistor R26, a pin 2 of the differential operational amplifier circuit N5 is respectively connected with an anode of a capacitor C13 and an anode of a resistor R45, a pin 3 of the differential operational amplifier circuit N5 is respectively connected with a power supply VC and an anode of a capacitor C5, a pin 4 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R22 and an anode of a resistor R65, a pin 5 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R25 and an anode of a resistor R64, a pin 6 of the differential operational amplifier circuit N5 is connected with GND _ TCQ, a pin 7 of the differential operational amplifier circuit N5 is suspended, and a pin 8 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R33 and an anode of a resistor R25; the negative electrode of the capacitor C13 and the negative electrode of the capacitor C5 are both connected with GND _ TCQ;

a pin 1 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R35 and an anode of a resistor R27, a pin 2 of the differential operational amplifier circuit N6 is respectively connected with an anode of a capacitor C14 and an anode of a resistor R45, a pin 3 of the differential operational amplifier circuit N6 is respectively connected with a power supply VC and an anode of a capacitor C6, a pin 4 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R28 and an anode of a resistor R66, a pin 5 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R27 and an anode of a resistor R67, a pin 6 of the differential operational amplifier circuit N6 is connected with GND _ TCQ, a pin 7 of the differential operational amplifier circuit N6 is suspended, and a pin 8 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R35 and an anode of a resistor R27; the negative electrode of the capacitor C14 and the negative electrode of the capacitor C6 are both connected with GND _ TCQ.

5. The high-speed large-area-array infrared imaging circuit according to claim 1, characterized in that: the multi-channel high-speed AD conversion circuit comprises an AD sampling chip N10, a resistor R45, a resistor R60, a resistor R60, a resistor R61, a resistor R62, a resistor R63, a resistor R64, a resistor R65, a resistor R66, a resistor R67, a resistor R68, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C76, a capacitor C77, a capacitor C78, a capacitor C19, a capacitor C84, a capacitor C84, a capacitor C30, a capacitor C31 and a capacitor C32; wherein the content of the first and second substances,

a pin 0 of an AD sampling chip N10 is connected with AGND, a pin 1 of an AD sampling chip N10 is respectively connected with the cathode of a resistor R66 and the cathode of a capacitor C79, a pin 2 of an AD sampling chip N10 is respectively connected with the anode of a resistor C79 and the cathode of a resistor R67, a pin 3, a pin 4, a pin 7, a pin 34, a pin 39, a pin 45 and a pin 4 of the AD sampling chip N67 are respectively connected with 1.8VA, a pin 8 and a pin 29 of the AD sampling chip N67 are respectively connected with 1.8VAD, a pin 5 of the AD sampling chip N67 is connected with the cathode of the capacitor C67, a pin 6 of the AD sampling chip N67 is connected with the cathode of the capacitor C67, a pin 27 of the AD sampling chip N67 is respectively connected with the anode of the resistor R67, a pin P67 of the FPGA chip N7 AD 67, a pin 28 of the sampling chip N67 is respectively connected with the anode of the resistor R67, the pin R67 of the FPGA chip N67, the anode of the FPGA sampling chip N67, the FPGA sampling chip N67 and the cathode of the FPGA sampling chip N67 are respectively connected with the anode of the resistor R67, and the anode of the FPGA sampling chip N67, and the FPGA sampling chip N67, The L pin of the FPGA chip N7, the 23 pins of the AD sampling chip N are respectively connected with the anode of a resistor R, the L pin of the FPGA chip N7, the 22 pins of the AD sampling chip N are respectively connected with the cathode of the resistor R, the K pin of the FPGA chip N7, the 21 pins of the AD sampling chip N are respectively connected with the anode of the resistor R, the K pin of the FPGA chip N7, the 20 pins of the AD sampling chip N are respectively connected with the cathode of the resistor R, the J pin of the FPGA chip N7, the 19 pins of the AD sampling chip N are respectively connected with the anode of the resistor R, the J pin of the FPGA chip N7, the 16 pins of the AD sampling chip N are respectively connected with the cathode of the resistor R, the J pin of the FPGA chip N7, the 15 pins of the AD sampling chip N are respectively connected with the anode of the resistor R, the J pin of the FPGA chip N7, the 14 pins of the AD sampling chip N are respectively connected with the cathode of the resistor R, the H pin of the FPGA chip N7, the 13 pins of the AD sampling chip N are respectively connected with the anode of the FPGA chip R, the H pin of the FPGA chip N7, the H pin, the cathode of the FPGA chip N12 pins of the AD sampling chip N, the anode of the AD sampling chip R, The pin C16 of the FPGA chip N7F, the pin 11 of the AD sampling chip N10 are respectively connected with the anode of a resistor R55, the pin C15 of the FPGA chip N7E, the pin 10 of the AD sampling chip N10 is respectively connected with the cathode of a resistor R56 and the pin D16 of the FPGA chip N7F, the pin 9 of the AD sampling chip N10 is respectively connected with the anode of a resistor R56 and the pin D15 of the FPGA chip N7F, the pin 18 of the AD sampling chip N10 is respectively connected with the cathode of a resistor R49 and the pin P16 of the FPGA chip N7E, the pin 17 of the AD sampling chip N10 is respectively connected with the anode of a resistor R49 and the pin R16 of the FPGA chip N7E, the pin 30 of the AD sampling chip N16 is connected with the pin R16 of the FPGA chip N7 16, the pin 31 of the sampling chip N16 is respectively connected with the pin T16 of the resistor N7 of the FPGA chip N16, the pin AD sampling chip N16 and the pin N16 of the anode of the FPGA chip AD sampling chip N16, and the pin AD sampling chip N16 are respectively connected with the anode of the pin T16 and the pin R16 of the sampling chip AD sampling chip N16, and the pin R16 of the anode of the FPGA chip AD sampling chip N16, and the pin AD sampling chip N16, The negative electrode of a capacitor C78, the pin 48 of an AD sampling chip N10 is respectively connected with the positive electrode of a resistor C78 and the negative electrode of a resistor R65, the pin 37 of the AD sampling chip N10 is respectively connected with the negative electrode of a resistor R62 and the negative electrode of a capacitor C77, the pin 38 of the AD sampling chip N10 is respectively connected with the positive electrode of a resistor C77 and the negative electrode of a resistor R63, the pin 35 of the AD sampling chip N10 is respectively connected with the negative electrode of a resistor R60 and the negative electrode of a capacitor C76, the pin 36 of the AD sampling chip N10 is respectively connected with the positive electrode of a resistor C76 and the negative electrode of a resistor R61, and the pin 41 of the AD sampling chip N10 is connected with AGND; the positive electrode of the capacitor C15, the positive electrode of the capacitor C16, the positive electrode of the capacitor C17, the positive electrode of the capacitor C18, the positive electrode of the capacitor C19, the positive electrode of the capacitor C20, the positive electrode of the capacitor C22, the positive electrode of the capacitor C23, the positive electrode of the capacitor C24, the positive electrode of the capacitor C25, the positive electrode of the capacitor C26, the positive electrode of the capacitor C27 and the positive electrode of the capacitor C28 are all connected to 1.8 VA; the negative electrode of the capacitor C15, the negative electrode of the capacitor C16, the negative electrode of the capacitor C17, the negative electrode of the capacitor C18, the negative electrode of the capacitor C19, the negative electrode of the capacitor C20, the negative electrode of the capacitor C21, the negative electrode of the capacitor C22, the negative electrode of the capacitor C23, the negative electrode of the capacitor C24, the negative electrode of the capacitor C25, the negative electrode of the capacitor C26, the negative electrode of the capacitor C27, the negative electrode of the capacitor C28, the negative electrode of the capacitor C29 and the negative electrode of the capacitor C30 are all connected to AGND.

6. The high-speed large-area-array infrared imaging circuit according to claim 1, characterized in that: the processor FPGA comprises an FPGA chip N7, a crystal oscillator N, a flash memory N, a resistor R, a capacitor C and a capacitor C; wherein the content of the first and second substances,

the pin C of the FPGA chip N7 is connected with the pin 5 of the flash memory N, the pin D of the FPGA chip N7 is connected with the pin 1 of the flash memory N, the pin H of the FPGA chip N7 is connected with the pin 2 of the flash memory N, the pin R of the FPGA chip N7 is connected with the pin 3 of the crystal oscillator N, the pin H of the FPGA chip N7 is connected with the negative electrode of the resistor R, the pin J of the FPGA chip N7 is connected with the pin 1 of the programming connector JTAG, the pin H of the FPGA chip N7 is connected with the negative electrode of the resistor R, the pin H and the pin H of the FPGA chip N7 are connected with 2.5VD, the pin G and the pin J of the FPGA chip N7 are connected with ND, the pin H of the FPGA chip N7 is connected with the pin 6 of the flash memory N, the pin H of the FPGA chip N7 is connected with the negative electrode of the resistor R, the pin F of the FPGA chip N7 is connected with the pin F of the resistor R, the pin E, the pin G, the pin A, the pin C, the pin A, the pin C pin, the pin A pin, the pin C pin, the pin C pin 3, the pin C pin, the pin 3, the pin 3 pin, the pin M3, the pin of the pin 3, the pin of the FPGA chip N7, the pin M3, the pin of the pin M3, the FPGA chip, the pin of the pin M of the pin, the pin of the FPGA chip, the pin M of the FPGA chip, the pin of the pin, the pin of the pin, the FPGA chip, the pin of the pin, the pin of the FPGA chip, the pin M of the pin, the pin of the pin, the pin of the pin, the FPGA chip, the pin of the FPGA chip, the pin of the socket of the FPGA chip, the pin of the FPGA chip, the socket of the pin, the socket of the, The P pin, the T pin, the K pin, the M pin, the E pin, the G pin, the L pin, the F pin and the L pin are all connected with 2.5VD, the P pin and the T pin of the FPGA chip N7 are all connected with 1.8VD, the F pin, the G pin, the H pin, the J pin, the K pin, the N pin, the D pin and the N pin of the FPGA chip N7 are all connected with 1.2VD, the H pin, the J pin, the F pin, the J pin, the K pin, the B pin, the C pin, the D pin, the E pin, the G pin, the K pin, the M pin, the N pin, the P pin, the R pin, the M pin, the E pin, the ND pin and the DGE pin are all connected with 2.5 VD; a pin 1 of the crystal oscillator N9 is suspended, a pin 2 of the crystal oscillator N9 is respectively connected with the negative electrode and the DGND of the capacitor C80, and a pin 4 of the crystal oscillator N9 is connected with 2.5 VD; 3 pins of a flash memory N8 are connected with 3.3VD, 4 pins of a flash memory N8 are connected with DGND, 7 pins and 8 pins of a flash memory N8 are connected with 3.3VD, and the positive electrode of a capacitor C81; the negative electrode of the capacitor C81 is connected with DGND, the positive electrodes of the resistor R37 and the resistor R39 are both connected with 3.3VD, the negative electrode of the resistor R38 is connected with DGND, the resistor R40 is connected with 2.5VD, and the resistor R41 and the resistor R42 are both connected with 3.3 VD; the negative electrodes of the capacitor C44, the capacitor C45, the capacitor C46, the capacitor C47, the capacitor C48, the capacitor C49, the capacitor C50, the capacitor C51, the capacitor C52, the capacitor C53, the capacitor C54, the capacitor C55, the capacitor C56, the capacitor C57, the capacitor C58, the capacitor C59, the capacitor C60, the capacitor C61, the capacitor C62, the capacitor C63, the capacitor C64, the capacitor C65, the capacitor C66, the capacitor C67, the capacitor C68, the capacitor C69, the capacitor C70, the capacitor C71, the capacitor C72, the capacitor C73, the capacitor C74, the capacitor C75 and the capacitor C80 are connected to DGND;

the positive electrodes of the capacitor C44, the capacitor C45, the capacitor C46, the capacitor C47, the capacitor C48, the capacitor C49, the capacitor C50, the capacitor C51, the capacitor C52, the capacitor C53, the capacitor C54 and the capacitor C55 are connected with 1.2 VD; the capacitor C56, the capacitor C57, the capacitor C58, the capacitor C59, the capacitor C60, the capacitor C61, the capacitor C62, the capacitor C63 and the capacitor C64 are connected with 2.5 VD; the capacitor C65, the capacitor C66 and the capacitor C67 are connected with 1.8 VD; the positive electrodes of the capacitor C68, the capacitor C69, the capacitor C70, the capacitor C71, the capacitor C72, the capacitor C73, the capacitor C74 and the capacitor C75 are connected with 3.3 VD.

The pins L5, F12, F5 and L12 of the FPGA chip N7M are connected with 2.5 VD; pins N4, D13, D4 and N13 are connected with 1.2 VD; the pins M5, E12, E5 and M12 are connected with DGND.

7. The high-speed large-area-array infrared imaging circuit according to claim 2, characterized in that: the models of the operational amplifier N1A, the operational amplifier N1B, the operational amplifier N1C, the operational amplifier N1D, the operational amplifier N2A, the operational amplifier N2B, the operational amplifier N2C and the operational amplifier N2D are OPA 4354.

8. The high-speed large-area-array infrared imaging circuit according to claim 3, characterized in that: the models of the differential operational amplifier circuit N3, the differential operational amplifier circuit N4, the differential operational amplifier circuit N5 and the differential operational amplifier circuit N6 are LT 1994.

9. The high-speed large-area-array infrared imaging circuit according to claim 6, characterized in that: the FPGA chips N7A, N7I, N7J, N7K, N7L and N7M are EP3C16U256I 7.

10. The high-speed large-area-array infrared imaging circuit according to claim 6, characterized in that: flash N8 is model EPCQ4ASI 8N.

Technical Field

The invention belongs to the technical field of microelectronics and photoelectronics, and particularly relates to a high-speed large-area-array infrared imaging circuit.

Background

Infrared imaging technology has become a hot spot of research in the world today in the military field. The advent of the third generation infrared detector has enabled the infrared imaging technology to rise one step in military applications. High frame frequency, large area array detectors have also been developed. The application of the high-frame-frequency large-area-array infrared detector in a seeker system greatly improves the performance of the seeker. The multi-array can improve the sensitivity threshold of the product, so that the product can detect farther targets; the high frame frequency can quickly update the target information of the product, so that the pre-push track of the missile is more accurate, the bandwidth is increased, the target loss is reduced, and the accurate guidance is realized.

At present, most infrared imaging circuits only realize the acquisition of a small-area array infrared detector. The design of the acquisition circuit of the detector with high frame frequency and large area array is to be verified.

Disclosure of Invention

The technical problem solved by the invention is as follows: the high-speed large-area array infrared imaging circuit is provided, high-frequency filtering of signals of a detector is completed through a filter circuit, a first-stage operational amplifier circuit follows and biases the filtered signals to improve the loading capacity of the detector, and a second-stage operational amplifier circuit scales and differentially converts the signals processed by the first-stage operational amplifier circuit to reduce common-mode interference on the circuit and match the input of a high-speed acquisition module; the multi-channel high-speed AD conversion circuit performs analog-to-digital conversion on the differential signal and then sends the differential signal to the FPGA; the FPGA acquires data of the multi-channel high-speed AD conversion circuit, and high-speed acquisition of signals is realized.

The purpose of the invention is realized by the following technical scheme: a high-speed large-area array infrared imaging circuit comprises: the device comprises a filter circuit, a primary operational amplifier circuit, a secondary operational amplifier circuit, a multi-channel high-speed AD conversion circuit and a processor FPGA; the filter circuit filters a signal output by the detector to obtain a filtered signal, and the filtered signal is sent to the first-stage operational amplifier circuit; the first-stage operational amplifier circuit carries out direct current bias and isolation on the filtered signal to obtain a biased signal, and the biased signal is sent to the second-stage operational amplifier circuit; the second-stage operational amplifier circuit performs scaling and differential conversion on the biased signals to obtain differential signals, and the differential signals are sent to the multi-channel high-speed AD conversion circuit; and the multi-channel high-speed AD conversion circuit performs analog-to-digital conversion on the differential signal and then sends the differential signal to the FPGA.

In the above high-speed large-area-array infrared imaging circuit, the filter circuit includes a capacitor C100, a resistor R1, a capacitor C101, a resistor R4, a capacitor C102, a resistor R11, a capacitor C103, and a resistor R14; the anode of the capacitor C100 and the anode of the resistor R1 are both connected with the pin 3 of the N1A of the primary operational amplifier circuit, and the cathode of the capacitor C100 and the cathode of the resistor R1 are both connected with GND _ TCQ; the anode of the capacitor C101 and the anode of the resistor R4 are both connected with the pin 10 of the N1C of the primary operational amplifier circuit, and the cathode of the capacitor C101 and the cathode of the resistor R4 are both connected with GND _ TCQ; the anode of the capacitor C102 and the anode of the resistor R11 are both connected with the pin 3 of the N2A of the primary operational amplifier circuit, and the cathode of the capacitor C102 and the cathode of the resistor R11 are both connected with GND _ TCQ; the anode of the capacitor C103 and the anode of the resistor R14 are both connected with the pin 3 of the N1A of the primary operational amplifier circuit, and the cathode of the capacitor C103 and the cathode of the resistor R14 are both connected with GND _ TCQ.

In the high-speed large-area-array infrared imaging circuit, the primary operational amplifier circuit comprises an operational amplifier N1A, an operational amplifier N1B, a resistor R7, a resistor R8, a capacitor C1, a capacitor C7, an operational amplifier N1C, an operational amplifier N1D, a resistor R9, a resistor R10, a capacitor C8, an operational amplifier N2A, an operational amplifier N2B, a resistor R17, a resistor R18, a capacitor C4, a capacitor C9, an operational amplifier N2C, an operational amplifier N2D, a resistor R19, a resistor R20 and a capacitor C10; wherein, 2 feet of the operational amplifier N1A are connected with the cathode of the resistor R7, 4 feet of the operational amplifier N1A are respectively connected with the power supply VC and the anode of the capacitor C1, 1 foot of the operational amplifier N1A is respectively connected with the anode of the resistor R7 and the anode of the resistor R29, and 11 feet of the operational amplifier N1A are respectively connected with GND _ TCQ and the cathode of the capacitor C7; the negative electrode of the capacitor C1 is connected with GND _ TCQ; the positive electrode of the capacitor C7 is respectively connected with a direct current bias VF and a pin 5 of an operational amplifier N1B; the 6 pins of the operational amplifier N1B are connected with the cathode of the resistor R8, and the 7 pins of the operational amplifier N1B are respectively connected with the anode of the resistor R8 and the anode of the resistor R30; a pin 9 of the operational amplifier N1C is connected with a cathode of a resistor R9, a pin 8 of the operational amplifier N1C is respectively connected with an anode of the resistor R9 and an anode of the resistor R31, an anode of a capacitor C8 is respectively connected with a direct current bias VF and a pin 12 of the operational amplifier N1D, a cathode of the capacitor C8 is connected with GND _ TCQ, a pin 13 of the operational amplifier N1D is connected with a cathode of a resistor R10, and a pin 14 of the operational amplifier N1D is respectively connected with an anode of the resistor R10 and an anode of the resistor R32; a pin 2 of the operational amplifier N2A is connected with the cathode of a resistor R17, a pin 4 of the operational amplifier N2A is respectively connected with the power supply VC and the anode of a capacitor C4, a pin 1 of the operational amplifier N2A is respectively connected with the anode of a resistor R17 and the anode of a resistor R33, and a pin 11 of the operational amplifier N2A is respectively connected with GND _ TCQ and the cathode of a capacitor C9; the negative electrode of the capacitor C4 is connected with GND _ TCQ; the positive electrode of the capacitor C9 is connected with a direct current bias VF and a pin 5 of an operational amplifier N2B; the pin 6 of the operational amplifier N2B is connected with the cathode of the resistor R18, and the pin 7 of the operational amplifier N2B is respectively connected with the anode of the resistor R18 and the anode of the resistor R34; the pin 9 of the operational amplifier N2C is connected with the cathode of the resistor R19, the pin 8 of the operational amplifier N2C is connected with the anode of the resistor R19 and the anode of the resistor R35 respectively, the anode of the capacitor C10 is connected with the direct current bias VF and the pin 12 of the operational amplifier N2D respectively, the cathode of the capacitor C10 is connected with GND _ TCQ, the pin 13 of the operational amplifier N1D is connected with the cathode of the resistor R20, and the pin 14 of the operational amplifier N1D is connected with the anode of the resistor R20 and the anode of the resistor R36 respectively.

In the high-speed large-area-array infrared imaging circuit, the secondary operational amplifier circuit comprises a differential operational amplifier circuit N3, a resistor R21, a resistor R22, a resistor R29, a resistor R30, a capacitor C11, a capacitor C2, a differential operational amplifier circuit N4, a resistor R23, a resistor R24, a resistor R31, a resistor R32, a capacitor C12, a capacitor C3, a differential operational amplifier circuit N5, a resistor R25, a resistor R26, a resistor R33, a resistor R34, a capacitor C13, a capacitor C5, a differential operational amplifier circuit N6, a resistor R27, a resistor R28, a resistor R35, a resistor R36, a capacitor C14 and a capacitor C6; wherein, pin 1 of the differential operational amplifier circuit N3 is connected to the cathode of the resistor R30 and the anode of the resistor R22, pin 2 of the differential operational amplifier circuit N3 is connected to the anode of the capacitor C11 and the anode of the resistor R45, pin 3 of the differential operational amplifier circuit N3 is connected to the anode of the power supply VC and the capacitor C2, pin 4 of the differential operational amplifier circuit N3 is connected to the cathode of the resistor R22 and the anode of the resistor R61, pin 5 of the differential operational amplifier circuit N3 is connected to the cathode of the resistor R21 and the anode of the resistor R60, pin 6 of the differential operational amplifier circuit N3 is connected to GND _ TCQ, pin 7 of the differential operational amplifier circuit N3 is suspended, and pin 8 of the differential operational amplifier circuit N3 is connected to the cathode of the resistor R29 and the anode of the resistor R21; the negative electrode of the capacitor C13 and the negative electrode of the capacitor C5 are both connected with GND _ TCQ; a pin 1 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R32 and an anode of a resistor R24, a pin 2 of the differential operational amplifier circuit N4 is respectively connected with an anode of a capacitor C12 and an anode of a resistor R45, a pin 3 of the differential operational amplifier circuit N4 is respectively connected with a power supply VC and an anode of a capacitor C3, a pin 4 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R22 and an anode of a resistor R62, a pin 5 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R23 and an anode of a resistor R63, a pin 6 of the differential operational amplifier circuit N4 is connected with GND _ TCQ, a pin 7 of the differential operational amplifier circuit N4 is suspended, and a pin 8 of the differential operational amplifier circuit N4 is respectively connected with a cathode of a resistor R31 and an anode of a resistor R23; the negative electrode of the capacitor C12 and the negative electrode of the capacitor C3 are both connected with GND _ TCQ; a pin 1 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R34 and an anode of a resistor R26, a pin 2 of the differential operational amplifier circuit N5 is respectively connected with an anode of a capacitor C13 and an anode of a resistor R45, a pin 3 of the differential operational amplifier circuit N5 is respectively connected with a power supply VC and an anode of a capacitor C5, a pin 4 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R22 and an anode of a resistor R65, a pin 5 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R25 and an anode of a resistor R64, a pin 6 of the differential operational amplifier circuit N5 is connected with GND _ TCQ, a pin 7 of the differential operational amplifier circuit N5 is suspended, and a pin 8 of the differential operational amplifier circuit N5 is respectively connected with a cathode of a resistor R33 and an anode of a resistor R25; the negative electrode of the capacitor C13 and the negative electrode of the capacitor C5 are both connected with GND _ TCQ; a pin 1 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R35 and an anode of a resistor R27, a pin 2 of the differential operational amplifier circuit N6 is respectively connected with an anode of a capacitor C14 and an anode of a resistor R45, a pin 3 of the differential operational amplifier circuit N6 is respectively connected with a power supply VC and an anode of a capacitor C6, a pin 4 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R28 and an anode of a resistor R66, a pin 5 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R27 and an anode of a resistor R67, a pin 6 of the differential operational amplifier circuit N6 is connected with GND _ TCQ, a pin 7 of the differential operational amplifier circuit N6 is suspended, and a pin 8 of the differential operational amplifier circuit N6 is respectively connected with a cathode of a resistor R35 and an anode of a resistor R27; the negative electrode of the capacitor C14 and the negative electrode of the capacitor C6 are both connected with GND _ TCQ.

In the high-speed large-area-array infrared imaging circuit, the multichannel high-speed AD conversion circuit comprises an AD sampling chip N10, a resistor R45, a resistor R60, a resistor R60, a resistor R61, a resistor R62, a resistor R63, a resistor R64, a resistor R65, a resistor R66, a resistor R67, a resistor R68, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C76, a capacitor C77, a capacitor C78, a capacitor C19, a capacitor C84, a capacitor C84, a capacitor C30, a capacitor C31, and a capacitor C32; wherein, pin 0 of AD sampling chip N10 is connected with AGND, pin 1 of AD sampling chip N10 is respectively connected with the cathode of resistor R66 and the cathode of capacitor C79, pin 2 of AD sampling chip N10 is respectively connected with the anode of resistor C79 and the cathode of resistor R67, pin 3, pin 4, pin 7, pin 34, pin 39, pin 45 and pin 4 of AD sampling chip N10 are respectively connected with 1.8VA, pin 8 and pin 29 of AD sampling chip N10 are respectively connected with 1.8VAD, pin 5 of AD sampling chip N10 is connected with the cathode of capacitor C31, pin 6 of AD sampling chip N10 is connected with the cathode of capacitor C32, pin 27 of AD sampling chip N32 is respectively connected with the cathode of resistor R32, pin P32 of FPGA chip N7 32, pin 28 of AD sampling chip N32 is respectively connected with the anode of resistor R32, pin R32 of FPGA chip N32, pin P32 of FPGA sampling chip N32 and pin 32 are respectively connected with the anode of FPGA sampling chip N32 and pin 32 of FPGA sampling chip N32, the 24 pin of the AD sampling chip N10 is respectively connected with the negative electrode of a resistor R51, the L13 pin of an FPGA chip N7E, the 23 pin of the AD sampling chip N10 is respectively connected with the positive electrode of a resistor R51, the L16 pin of an FPGA chip N7E, the 22 pin of the AD sampling chip N10 is respectively connected with the negative electrode of a resistor R52, the K16 pin of an FPGA chip N7E, the 21 pin of the AD sampling chip N10 is respectively connected with the positive electrode of a resistor R52, the K15 pin of an FPGA chip N7E, the 20 pin of the AD sampling chip N10 is respectively connected with the negative electrode of a resistor R58, the J14 pin of an FPGA chip N7E, the 19 pin of the AD sampling chip N10 is respectively connected with the positive electrode of a resistor R58, the J12 pin of an FPGA chip N7E, the 16 pin of the sampling chip N12 is respectively connected with the negative electrode of a resistor R12, the J12 pin of an FPGA chip N12, the positive electrode of the FPGA chip N12, the sampling chip N12 is respectively connected with the positive electrode of an FPGA sampling chip AD sampling chip N12, and the sampling chip N12 pin of the sampling chip N12, and the sampling chip N12 are respectively connected with the positive electrode of the anode of the FPGA sampling chip N12, H15 of FPGA chip N7F, 12 of AD sampling chip N10 are respectively connected with the negative pole of resistor R55, C16 of FPGA chip N7F, 11 of AD sampling chip N10 is respectively connected with the positive pole of resistor R55, C15 of FPGA chip N7E, 10 of AD sampling chip N10 is respectively connected with the negative pole of resistor R56, D16 of FPGA chip N7F, 9 of AD sampling chip N10 is respectively connected with the positive pole of resistor R56, D15 of FPGA chip N7F, 18 of AD sampling chip N10 is respectively connected with the negative pole of resistor R49, P49 of FPGA chip N7 49, 17 of AD sampling chip N49 is respectively connected with the positive pole of resistor R49, R49 of FPGA chip N7 49, R49 of FPGA chip N49, 30 of sampling chip N49 is connected with the R49 of FPGA chip N7, N49 is respectively connected with the negative pole of FPGA sampling chip AD sampling chip N49, and N49 is respectively connected with the sampling chip AD sampling chip N49, and N49 of FPGA sampling chip AD sampling chip N49 is respectively connected with the negative pole of FPGA sampling chip N49, and the sampling chip N49, The positive pole of the capacitor C30, the pin 47 of the AD sampling chip N10 is respectively connected with the negative pole of the resistor R64 and the negative pole of the capacitor C78, the pin 48 of the AD sampling chip N10 is respectively connected with the positive pole of the resistor C78 and the negative pole of the resistor R65, the pin 37 of the AD sampling chip N10 is respectively connected with the negative pole of the resistor R62 and the negative pole of the capacitor C77, the pin 38 of the AD sampling chip N10 is respectively connected with the positive pole of the resistor C77 and the negative pole of the resistor R63, the pin 35 of the AD sampling chip N10 is respectively connected with the negative pole of the resistor R60 and the negative pole of the capacitor C76, the pin 36 of the AD sampling chip N10 is respectively connected with the positive pole of the resistor C76 and the negative pole of the resistor R61, and the pin 41 of the AD sampling chip N10 is connected with AGND; the positive electrode of the capacitor C15, the positive electrode of the capacitor C16, the positive electrode of the capacitor C17, the positive electrode of the capacitor C18, the positive electrode of the capacitor C19, the positive electrode of the capacitor C20, the positive electrode of the capacitor C22, the positive electrode of the capacitor C23, the positive electrode of the capacitor C24, the positive electrode of the capacitor C25, the positive electrode of the capacitor C26, the positive electrode of the capacitor C27 and the positive electrode of the capacitor C28 are all connected to 1.8 VA; the negative electrode of the capacitor C15, the negative electrode of the capacitor C16, the negative electrode of the capacitor C17, the negative electrode of the capacitor C18, the negative electrode of the capacitor C19, the negative electrode of the capacitor C20, the negative electrode of the capacitor C21, the negative electrode of the capacitor C22, the negative electrode of the capacitor C23, the negative electrode of the capacitor C24, the negative electrode of the capacitor C25, the negative electrode of the capacitor C26, the negative electrode of the capacitor C27, the negative electrode of the capacitor C28, the negative electrode of the capacitor C29 and the negative electrode of the capacitor C30 are all connected to AGND.

In the high-speed large-area-array infrared imaging circuit, the processor FPGA comprises an FPGA chip N7A, an FPGA chip N7I, an FPGA chip N7J, an FPGA chip N7D, an FPGA chip N7K, an FPGA chip N7L, an FPGA chip N7M, a crystal oscillator N9, a flash memory N8, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, a resistor R49, a resistor R50, a resistor R51, a resistor R52, a resistor R53, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R5, a capacitor C44, a capacitor C45, a capacitor C46 and a capacitor C47, a capacitor C48, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C57, a capacitor C58, a capacitor C59, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64, a capacitor C65, a capacitor C66, a capacitor C67, a capacitor C68, a capacitor C69, a capacitor C70, a capacitor C71, a capacitor C72, a capacitor C73, a capacitor C74, a capacitor C75, and a capacitor C80; wherein, the pin C of the FPGA chip N7 is connected with the pin 5 of the flash memory N, the pin D of the FPGA chip N7 is connected with the pin 1 of the flash memory N, the pin H of the FPGA chip N7 is connected with the pin 2 of the flash memory N, the pin R of the FPGA chip N7 is connected with the pin 3 of the crystal oscillator N, the pin H of the FPGA chip N7 is connected with the negative electrode of the resistor R, the pin J of the FPGA chip N7 is connected with the pin 1 of the programming connector JTAG, the pin H of the FPGA chip N7 is connected with the negative electrode of the resistor R, the pin H and the pin H of the FPGA chip N7 are connected with the pin 2.5VD, the pin G and the pin J of the FPGA chip N7 are connected with the pin DGND, the pin H of the FPGA chip N7 is connected with the pin 6 of the flash memory N, the pin H of the FPGA chip N7 is connected with the negative electrode of the resistor R, the pin H of the FPGA chip N7 is connected with the negative electrode of the pin F of the pin DGND, the pin E of the FPGA chip N7, the pin E, the pin G, the pin A, the pin C, the pin A, the pin C pin, the pin A pin, the pin C pin A pin, the pin C pin 3, the pin M3, the pin M3.3 of the FPGA chip, the pin 3 The P pin, the T pin, the K pin, the M pin, the E pin, the G pin, the L pin, the F pin and the L pin are all connected with 2.5VD, the P pin and the T pin of the FPGA chip N7 are all connected with 1.8VD, the F pin, the G pin, the H pin, the J pin, the K pin, the N pin, the D pin and the N pin of the FPGA chip N7 are all connected with 1.2VD, the H pin, the J pin, the F pin, the J pin, the K pin, the B pin, the C pin, the D pin, the E pin, the G pin, the K pin, the M pin, the N pin, the P pin, the R pin, the M pin, the E pin, the ND pin and the DGE pin are all connected with 2 VD; a pin 1 of the crystal oscillator N9 is suspended, a pin 2 of the crystal oscillator N9 is respectively connected with the negative electrode and the DGND of the capacitor C80, and a pin 4 of the crystal oscillator N9 is connected with 2.5 VD; 3 pins of a flash memory N8 are connected with 3.3VD, 4 pins of a flash memory N8 are connected with DGND, 7 pins and 8 pins of a flash memory N8 are connected with 3.3VD, and the positive electrode of a capacitor C81; the negative electrode of the capacitor C81 is connected with DGND, the positive electrodes of the resistor R37 and the resistor R39 are both connected with 3.3VD, the negative electrode of the resistor R38 is connected with DGND, the resistor R40 is connected with 2.5VD, and the resistor R41 and the resistor R42 are both connected with 3.3 VD; the negative electrodes of the capacitor C44, the capacitor C45, the capacitor C46, the capacitor C47, the capacitor C48, the capacitor C49, the capacitor C50, the capacitor C51, the capacitor C52, the capacitor C53, the capacitor C54, the capacitor C55, the capacitor C56, the capacitor C57, the capacitor C58, the capacitor C59, the capacitor C60, the capacitor C61, the capacitor C62, the capacitor C63, the capacitor C64, the capacitor C65, the capacitor C66, the capacitor C67, the capacitor C68, the capacitor C69, the capacitor C70, the capacitor C71, the capacitor C72, the capacitor C73, the capacitor C74, the capacitor C75 and the capacitor C80 are connected to DGND; the positive electrodes of the capacitor C44, the capacitor C45, the capacitor C46, the capacitor C47, the capacitor C48, the capacitor C49, the capacitor C50, the capacitor C51, the capacitor C52, the capacitor C53, the capacitor C54 and the capacitor C55 are connected with 1.2 VD; the capacitor C56, the capacitor C57, the capacitor C58, the capacitor C59, the capacitor C60, the capacitor C61, the capacitor C62, the capacitor C63 and the capacitor C64 are connected with 2.5 VD; the capacitor C65, the capacitor C66 and the capacitor C67 are connected with 1.8 VD; the positive electrodes of the capacitor C68, the capacitor C69, the capacitor C70, the capacitor C71, the capacitor C72, the capacitor C73, the capacitor C74 and the capacitor C75 are connected with 3.3 VD; the pins L5, F12, F5 and L12 of the FPGA chip N7M are connected with 2.5 VD; pins N4, D13, D4 and N13 are connected with 1.2 VD; the pins M5, E12, E5 and M12 are connected with DGND.

In the high-speed large-area-array infrared imaging circuit, the models of the operational amplifier N1A, the operational amplifier N1B, the operational amplifier N1C, the operational amplifier N1D, the operational amplifier N2A, the operational amplifier N2B, the operational amplifier N2C and the operational amplifier N2D are OPA 4354.

In the high-speed large-area-array infrared imaging circuit, the models of the differential operational amplifier circuit N3, the differential operational amplifier circuit N4, the differential operational amplifier circuit N5 and the differential operational amplifier circuit N6 are LT 1994.

In the high-speed large-area-array infrared imaging circuit, the model numbers of the FPGA chips N7A, N7I, N7J, N7K, N7L and N7M are EP3C16U256I 7.

In the high-speed large-area-array infrared imaging circuit, the models of the primary operational amplifiers N1 and N2 are OPA 4354.

In the high-speed large-area-array infrared imaging circuit, the second-level differential operational amplifiers N3, N4, N5 and N6 are LT 1994.

In the high-speed large-area-array infrared imaging circuit, the model of the AD chip N10 is AD 9245.

In the high-speed large-area-array infrared imaging circuit, the model number of the FPGA chip N7A is EP3C16U 25617.

In the high-speed large-area-array infrared imaging circuit, the model number of the FPGA chip N7C is EP3C16U 25617.

In the high-speed large-area-array infrared imaging circuit, the model number of the FPGA chip N7I is EP3C16U 25617.

In the high-speed large-area-array infrared imaging circuit, the model number of the FPGA chip N7J is EP3C16U 25617.

In the high-speed large-area-array infrared imaging circuit, the model number of the FPGA chip N7K is EP3C16U 25617.

In the high-speed large-area-array infrared imaging circuit, the model number of the FPGA chip N7L is EP3C16U 25617.

In the high-speed large-area-array infrared imaging circuit, the model number of the FPGA chip N7M is EP3C16U 25617.

In the high-speed large-area-array infrared imaging circuit, the model of the flash memory N8 is EPCQ4ASI 8N.

In the high-speed large-area-array infrared imaging circuit, the model of the crystal oscillator N9 is ZPB28-64 MHz.

Compared with the prior art, the invention has the following beneficial effects:

(1) the filter has adjustable bandwidth, and can set the cut-to frequency point of the filter according to different sampling rates, thereby reducing the high-frequency image acquisition noise.

(2) The invention reduces the proportion of the input signal through the differential operational amplifier, and improves the sampling frequency of the signal.

(3) The invention improves the image acquisition speed through multi-channel data acquisition.

(4) The invention improves the sensitivity range of the product.

(5) The method can quickly update the target information of the product, so that the pre-push track of guidance is more accurate, the bandwidth is increased, the target loss is reduced, and accurate guidance is realized.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a block diagram of the high-speed large-area infrared imaging circuit of the present invention;

FIG. 2 is a schematic diagram of a filter circuit of the present invention;

FIG. 3(a) is a schematic diagram of a one-stage operational amplifier circuit of the present invention;

FIG. 3(b) is another schematic diagram of the primary operational amplifier circuit of the present invention;

FIG. 3(c) is yet another schematic diagram of the primary operational amplifier circuit of the present invention;

FIG. 3(d) is yet another schematic diagram of the primary operational amplifier circuit of the present invention;

FIG. 4(a) is a schematic diagram of a two-stage operational amplifier circuit of the present invention;

FIG. 4(b) is another schematic diagram of the two stage operational amplifier circuit of the present invention;

FIG. 4(c) is yet another schematic diagram of the two stage operational amplifier circuit of the present invention;

FIG. 4(d) is yet another schematic diagram of the two stage operational amplifier circuit of the present invention;

FIG. 5 is a schematic diagram of a multi-channel high-speed AD conversion circuit of the present invention;

FIG. 6 is a diagram of FPGA configuration pin connections of the present invention;

FIG. 7 is a diagram of FPGA power pin connections of the present invention;

fig. 8 is a schematic diagram of the decoupling capacitor connection of the present invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1 is a block diagram of the high-speed large-area-array infrared imaging circuit of the invention. As shown in fig. 1, the high-speed large-area-array infrared imaging circuit includes: the device comprises a filter circuit, a primary operational amplifier circuit, a secondary operational amplifier circuit, a multi-channel high-speed AD conversion circuit and a processor FPGA; wherein the content of the first and second substances,

the FPGA completes the configuration of the detector and the multi-channel high-speed AD conversion circuit, so that the detector normally outputs image signals, and the multi-channel high-speed AD can start to acquire the signals; the filtering circuit low-pass filters the original image signal and then sends the filtered image signal to the first-stage operational amplifier circuit; the first-stage operational amplifier circuit follows and biases the filtered signal; the second-stage operational amplifier circuit performs scaling and differential conversion on the signals processed by the first-stage operational amplifier; the multi-channel high-speed AD conversion circuit collects differential signals and digitalizes the signals to be sent to the FPGA; and the FPGA acquires data of the multi-channel high-speed AD conversion circuit, packages the data and sends the data to a next-stage system.

As shown in fig. 2, the filter circuit includes a capacitor C100 and a resistor R1 of the channel 1, a capacitor C101 and a resistor R4 of the channel 2, a capacitor C102 and a resistor R11 of the channel 3, a capacitor C103 and a resistor R14 of the channel 4; wherein the content of the first and second substances,

the anode of the capacitor C100 and the anode of the resistor R1 of the channel 1 are connected with the pin 3 of the N1A of the primary operational amplifier circuit, and the cathode of the capacitor C100 and the cathode of the resistor R1 are connected with GND _ TCQ.

The anode of the capacitor C101 and the anode of the resistor R4 of the channel 2 are connected with the pin 10 of the N1C of the primary operational amplifier circuit, and the cathode of the capacitor C101 and the cathode of the resistor R4 are connected with GND _ TCQ.

The anode of the capacitor C102 and the anode of the resistor R11 of the channel 3 are connected with the pin 3 of the N2A of the primary operational amplifier circuit, and the cathode of the capacitor C102 and the cathode of the resistor R11 are connected with GND _ TCQ.

The anode of the capacitor C103 and the anode of the resistor R14 of the channel 4 are connected with the pin 3 of the N1A of the primary operational amplifier circuit, and the cathode of the capacitor C103 and the cathode of the resistor R14 are connected with GND _ TCQ.

As shown in fig. 3(a), fig. 3(b), fig. 3(c) and fig. 3(d), the first stage operational amplifier circuit includes: the operational amplifier comprises N1A, N1B, a resistor R7, a resistor R8, a capacitor C1 and a capacitor C7 of a channel 1, N1C, N1D, a resistor R9, a resistor R10 and a capacitor C8 of an operational amplifier of a channel 2, N2A, N2B, a resistor R17, a resistor R18, a capacitor C4 and a capacitor C9 of an operational amplifier of a channel 3, N2C, N2D, a resistor R19, a resistor R20 and a capacitor C10 of an operational amplifier of a channel 4; wherein the content of the first and second substances,

a pin 2 of the operational amplifier N1A of the channel 1 is connected with the cathode of the resistor R7, a pin 4 is connected with the power VC and the anode of the capacitor C1, a pin 1 is connected with the anode of the resistor R7 and the anode of the resistor R29, and a pin 11 is connected with the GND _ TCQ and the cathode of the capacitor C7; the negative electrode of the capacitor C1 is connected with GND _ TCQ; the positive electrode of the capacitor C7 is connected with a direct current bias VF and a pin 5 of an operational amplifier N1B; the pin 6 of the operational amplifier N1B is connected with the negative electrode of the resistor R8, the pin 7 is connected with the positive electrode of the R8 and the positive electrode of the resistor R30.

The 9 pin of the operational amplifier N1C of the channel 2 is connected with the negative electrode of the resistor R9, the 8 pin is connected with the positive electrode of the resistor R9 and the positive electrode of the resistor R31, the positive electrode of the capacitor C8 is connected with the direct current bias VF, the 12 pin of the operational amplifier N1D, the negative electrode of the capacitor C8 is connected with GND _ TCQ, the 13 pin of the operational amplifier N1D is connected with the negative electrode of the resistor R10, and the 14 pin is connected with the positive electrode of the resistor R10 and the positive electrode of the resistor R32.

A pin 2 of the operational amplifier N2A of the channel 3 is connected with the cathode of the resistor R17, a pin 4 is connected with the power VC and the anode of the capacitor C4, a pin 1 is connected with the anode of the resistor R17 and the anode of the resistor R33, and a pin 11 is connected with the GND _ TCQ and the cathode of the capacitor C9; the negative electrode of the capacitor C4 is connected with GND _ TCQ; the positive electrode of the capacitor C9 is connected with a direct current bias VF and a pin 5 of an operational amplifier N2B; the pin 6 of the operational amplifier N2B is connected with the negative electrode of the resistor R18, the pin 7 is connected with the positive electrode of the R18 and the positive electrode of the resistor R34.

The 9 pin of the operational amplifier N2C of the channel 4 is connected with the negative electrode of the resistor R19, the 8 pin is connected with the positive electrode of the resistor R19 and the positive electrode of the resistor R35, the positive electrode of the capacitor C10 is connected with the direct current bias VF, the 12 pin of the operational amplifier N2D, the negative electrode of the capacitor C10 is connected with GND _ TCQ, the 13 pin of the operational amplifier N1D is connected with the negative electrode of the resistor R20, and the 14 pin is connected with the positive electrode of the resistor R20 and the positive electrode of the resistor R36.

As shown in fig. 4(a), fig. 4(b), fig. 4(c) and fig. 4(d), the two-stage operational amplifier circuit includes: a differential operational amplifier circuit N3 of a channel 1, proportional transformation resistors R21, R22, R29 and R30, a capacitor C11 and a capacitor C2; a differential operational amplifier circuit N4 of a channel 2, proportional transformation resistors R23, R24, R31 and R32, a capacitor C12 and a capacitor C3; a differential operational amplifier circuit N5 of a channel 3, proportional transformation resistors R25, R26, R33 and R34, a capacitor C13 and a capacitor C5; a differential operational amplifier circuit N6 of a channel 4, proportional transformation resistors R27, R28, R35 and R36, a capacitor C14 and a capacitor C6; wherein the content of the first and second substances,

a pin 1 of a differential operational amplifier N3 of a channel 1 is connected with a cathode of a resistor R30, an anode of a resistor R22, a pin 2 is connected with an anode of a capacitor C11 and an anode of a resistor R45, a pin 3 is connected with a power supply VC and an anode of a capacitor C2, a pin 4 is connected with an anode of a resistor R22, an anode of a resistor R61, a pin 5 is connected with an anode of a resistor R21 and an anode of a resistor R60, a pin 6 is connected with GND _ TCQ, a pin 7 is suspended, a pin 8 is connected with an anode of a resistor R29 and an anode of a resistor R21; the negative electrode of the capacitor C13 and the negative electrode of the capacitor C5 are connected with GND _ TCQ.

A pin 1 of a differential operational amplifier N4 of a channel 2 is connected with a cathode of a resistor R32, an anode of a resistor R24, a pin 2 is connected with an anode of a capacitor C12 and an anode of a resistor R45, a pin 3 is connected with a power supply VC and an anode of a capacitor C3, a pin 4 is connected with an anode of a resistor R22, an anode of a resistor R62, a pin 5 is connected with an anode of a resistor R23 and an anode of a resistor R63, a pin 6 is connected with GND _ TCQ, a pin 7 is suspended, a pin 8 is connected with an anode of a resistor R31 and an anode of a resistor R23; the negative electrode of the capacitor C12 and the negative electrode of the capacitor C3 are connected with GND _ TCQ.

A1 pin of a differential operational amplifier N5 of a channel 3 is connected with a cathode of a resistor R34, an anode of a resistor R26, a 2 pin is connected with an anode of a capacitor C13 and an anode of a resistor R45, a 3 pin is connected with a power supply VC and an anode of a capacitor C5, a4 pin is connected with a cathode of a resistor R22, an anode of a resistor R65, a 5 pin is connected with a cathode of a resistor R25 and an anode of a resistor R64, a 6 pin is connected with GND _ TCQ, a 7 pin is suspended, and an 8 pin is connected with an anode of a resistor R33 and an anode of a resistor R25; the negative electrode of the capacitor C13 and the negative electrode of the capacitor C5 are connected with GND _ TCQ.

A1 pin of a differential operational amplifier N6 of a channel 4 is connected with a cathode of a resistor R35, an anode of a resistor R27, a 2 pin is connected with an anode of a capacitor C14 and an anode of a resistor R45, a 3 pin is connected with a power supply VC and an anode of a capacitor C6, a4 pin is connected with a cathode of a resistor R28, an anode of a resistor R66, a 5 pin is connected with a cathode of a resistor R27 and an anode of a resistor R67, a 6 pin is connected with GND _ TCQ, a 7 pin is suspended, and an 8 pin is connected with an anode of a resistor R35 and an anode of a resistor R27; the negative electrode of the capacitor C14 and the negative electrode of the capacitor C6 are connected with GND _ TCQ.

As shown in fig. 5, the multi-channel high-speed AD conversion circuit includes: the AD sampling chip N10, a resistor R45, a resistor R60, a resistor R60, a resistor R61, a resistor R62, a resistor R63, a resistor R64, a resistor R65, a resistor R66, a resistor R67, a resistor R68, a capacitor C15, a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C26, a capacitor C27, a capacitor C28, a capacitor C29, a capacitor C76, a capacitor C77, a capacitor C78, a capacitor C19, a capacitor C84, a capacitor C84, a capacitor C30, a capacitor C31 and a capacitor C32; wherein the content of the first and second substances,

a0 pin of an AD sampling chip N is connected with AGND, a1 pin is connected with the negative electrode of a resistor R, the negative electrode of a capacitor C, a 2 pin is connected with the positive electrode of the resistor C, the negative electrode of the resistor R, a 3 pin, a4 pin, a 7 pin, a 34 pin, a 39 pin, a 45 pin, a4 pin is connected with 1.8VA, a 8 pin, a 29 pin is connected with 1.8VAD, a 5 pin is connected with the negative electrode of the capacitor C, a 6 pin is connected with the negative electrode of the capacitor C, a 27 pin is connected with the negative electrode of the resistor R, a P pin of N7, a 28 pin is connected with the positive electrode of the resistor R, an R pin of N7, a 26 pin is connected with the negative electrode of the resistor R, an N pin of N7, a 25 pin is connected with the positive electrode of the resistor R, an N pin of N7, a 24 pin is connected with the negative electrode of the resistor R, an L pin of N7, a 23 pin is connected with the positive electrode of the resistor R, an L pin of N7, a 22 pin is connected with the negative electrode of the resistor R, a K pin of N7, a 21 pin is connected with the positive electrode of the resistor R, a K pin of N7, a 20 pin is connected with the negative electrode of the resistor J, a 19 pin R, a negative electrode of the resistor J, a16 pin R, and a negative electrode of the resistor J7, A pin J16 of N7E, a pin 15 connected with the positive pole of a resistor R53, a pin J15 of N7E, a pin 14 connected with the negative pole of a resistor R54, a pin H54 of N7 54, a pin 13 connected with the positive pole of a resistor R54, a pin H54 of N7 54, a pin 12 connected with the negative pole of a resistor R54, a pin C54 of N7 54, a pin 11 connected with the positive pole of a resistor R54, a pin C54 of N7 54, a pin 10 connected with the negative pole of a resistor R54, a pin D54 of N7 54, a pin 9 connected with the positive pole of a resistor R54, a pin D54 of N7 54, a pin 18 connected with the negative pole of a resistor R54, a pin P54 of N7 54, a pin 17 connected with the positive pole of a resistor R54, a pin R54 of N7 54, a pin R54 of a pin 30 connected with the R54, a pin T3631 of N7, a pin T54 connected with the negative pole of a resistor R54, a pin 54 of a pin 54, a pin 6 connected with the negative pole C54, a pin 6 connected with the negative pole C54, a capacitor C54 of a pin 72, a pin C54, a pin 72 of a pin 72, a pin C54, a pin 7R 54, a pin 72, a pin 54, a pin C54, a pin 72, a pin 54 of a pin C54, a pin 72 of a pin 72, a pin 72 of a pin 54, a pin 72, a pin 54 of a pin 54, a pin 72, a pin 6 connected with a pin 72, a pin 6 connected with a pin C72, a pin C54, a pin 72, a pin 54, a pin C72, a pin 54, a pin 72, a pin 54, a pin 7, a pin 72, a pin 54, a pin 72, a pin 54, a pin 72, a pin 54, a pin 72, a pin 54, a pin 72, a pin, the pin 35 is connected with the negative electrode of the resistor R60, the negative electrode of the capacitor C76, the pin 36 is connected with the positive electrode of the resistor C76 and the negative electrode of the resistor R61, and the pin 41 is connected with AGND; the positive electrode of the capacitor C15, the positive electrode of the capacitor C16, the positive electrode of the capacitor C17, the positive electrode of the capacitor C18, the positive electrode of the capacitor C19, the positive electrode of the capacitor C20, the positive electrode of the capacitor C22, the positive electrode of the capacitor C23, the positive electrode of the capacitor C24, the positive electrode of the capacitor C25, the positive electrode of the capacitor C26, the positive electrode of the capacitor C27 and the positive electrode of the capacitor C28 are connected with 1.8 VA; the negative electrode of the capacitor C15, the negative electrode of the capacitor C16, the negative electrode of the capacitor C17, the negative electrode of the capacitor C18, the negative electrode of the capacitor C19, the negative electrode of the capacitor C20, the negative electrode of the capacitor C21, the negative electrode of the capacitor C22, the negative electrode of the capacitor C23, the negative electrode of the capacitor C24, the negative electrode of the capacitor C25, the negative electrode of the capacitor C26, the negative electrode of the capacitor C27, the negative electrode of the capacitor C28, the negative electrode of the capacitor C29 and the negative electrode of the capacitor C30 are connected to AGND.

As shown in fig. 6, 7 and 8, the processor FPGA includes an FPGA chip N, a crystal oscillator N, a flash memory N, a resistor R, a capacitor C; the pin C1 of the FPGA chip N7A is connected with the pin 5 of the flash memory N8, the pin D2 is connected with the pin 1 of the flash memory N8, the pin H2 is connected with the pin 2 of the flash memory N8, the pin R9 of the N7I is connected with the pin 3 of the crystal oscillator N9, the pin H4 of the N7J is connected with the negative pole of the resistor R37, the pin J4 is connected with the pin 1 of the JTAG, the pin H3 is connected with the negative pole of the resistor R38, the pin J5 is connected with the negative pole of the resistor R39, the pin H13, the pin H12 is connected with the pin 2.5VD, the pin G12, the pin J3 is connected with the pin ND, the pin H1 is connected with the pin 6 of the flash memory N8, the pin H14 is connected with the negative pole of the resistor R40, the pin H5, the pin 5 is connected with the negative pole of the resistor R5, the pin 5, the pins F5, the pins of D13 and N13 are connected with 1.2VD, the pins of N7LH7, H8, H9, H10, J7, J8, J9, J10, F6, F10, J11, K8, B2, B15, C5, C12, D7, D10, E4, E13, G4, G13, K4, K13, M4, M13, N7, N10, P5, P12, R2, R15, M5, E12, E5 and M12 are connected with DGND; the pin 1 of N9 is suspended, the pin 2 is connected with the negative pole of the capacitor C80 and DGND, and the pin 4 is connected with 2.5 VD; a pin 3 of N8 is connected with 3.3VD, a pin 4 is connected with DGND, a pin 7 and a pin 8 are connected with 3.3VD, and the anode of a capacitor C81; the negative electrode of the capacitor C81 is connected with DGND, the positive electrodes of the resistors R37 and R39 are connected with 3.3VD, the negative electrode of the resistor R38 is connected with DGND, the resistor R40 is connected with 2.5VD, and the resistors R41 and R42 are connected with 3.3 VD; a capacitor C44, a capacitor C45, a capacitor C46, a capacitor C47, a capacitor C48, a capacitor C49, a capacitor C50, a capacitor C51, a capacitor C52, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C57, a capacitor C58, a capacitor C59, a capacitor C60, a capacitor C61, a capacitor C62, a capacitor C63, a capacitor C64, a capacitor C65, a capacitor C66, a capacitor C67, a capacitor C68, a capacitor C69, a capacitor C70, a capacitor C71, a capacitor C72, a capacitor C73, a capacitor C74, a capacitor C75 and a negative electrode of a capacitor C80 is connected to DGND; the capacitor C44, the capacitor C45, the capacitor C46, the capacitor C47, the capacitor C48, the capacitor C49, the capacitor C50, the capacitor C51, the capacitor C52, the capacitor C53, the capacitor C54 and the anode of the capacitor C55 are connected with 1.2 VD; the capacitor C56, the capacitor C57, the capacitor C58, the capacitor C59, the capacitor C60, the capacitor C61, the capacitor C62, the capacitor C63 and the capacitor C64 are connected with 2.5 VD; the capacitor C65, the capacitor C66 and the capacitor C67 are connected with 1.8 VD; the capacitor C68, the capacitor C69, the capacitor C70, the capacitor C71, the capacitor C72, the capacitor C73, the capacitor C74 and the anode of the capacitor C75 are connected with 3.3 VD.

The model of the primary operational amplifiers N1 and N2 is OPA 4354. The model numbers of the secondary difference operational amplifiers N3, N4, N5 and N6 are LT 1994. The model number of the AD chip N10 is AD 9245. The FPGA chip N7A is of the type EP3C16U 25617. The FPGA chip N7C is of the type EP3C16U 25617. The FPGA chip N7I is of the type EP3C16U 25617. The FPGA chip N7J is of the type EP3C16U 25617. The FPGA chip N7K is of the type EP3C16U 25617. The FPGA chip N7L is of the type EP3C16U 25617. The FPGA chip N7M is of the type EP3C16U 25617. Flash N8 is model EPCQ4ASI 8N. The model of the crystal oscillator N9 is ZPB28-64 MHz.

The filter has adjustable bandwidth, and can set the cut-to frequency point of the filter according to different sampling rates, thereby reducing the high-frequency image acquisition noise. The invention reduces the proportion of the input signal through the differential operational amplifier, and improves the sampling frequency of the signal. According to the invention, the image acquisition speed is improved through channel data acquisition. The invention improves the sensitivity range of the product. The method can quickly update the target information of the product, so that the pre-push track of guidance is more accurate, the bandwidth is increased, the target loss is reduced, and accurate guidance is realized.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.