阅读说明：本技术 一种基于Rust的多核RISCV-CPU模拟器 (Multi-core RISCV-CPU simulator based on Rust ) 是由 徐君 蒋旭 伍楷舜 于 2021-06-25 设计创作，主要内容包括：本发明公开了一种基于Rust的多核RISCV模拟器。该模拟器包括Risc-V处理核心模块、总线模块、DRAM模块、CLINT模块、PLIC模块和UART模块,其中Risc-V处理核心模块设置为多个,并基于Risc-V开源指令集构造,用于实现取指令,译码和执行功能；DRAM模块用于模拟内存；PLIC模块用于模拟硬盘；UART模块用于模拟外部中断或本地中断；总线模块与用于控制Risc-V处理核心模块、总线模块、DRAM模块、CLINT模块,PLIC模块和UART模块之间的信息交互,以实现无冲突通信。本发明提供的模拟器利用Rust语言强调安全,内存布局控制和并发的特性,提高了模拟器运行时的内存安全性,并且鲁棒性强。(The invention discloses a multi-core RISCV simulator based on Rust. The simulator comprises a plurality of Risc-V processing core modules, a bus module, a DRAM module, a CLINT module, a PLIC module and a UART module, wherein the Risc-V processing core modules are constructed based on a Risc-V open source instruction set and used for realizing the functions of instruction fetching, decoding and execution; the DRAM module is used for simulating a memory; the PLIC module is used for simulating a hard disk; the UART module is used for simulating external interruption or local interruption; the bus module is used for controlling information interaction among the Risc-V processing core module, the bus module, the DRAM module, the CLINT module, the PLIC module and the UART module so as to realize conflict-free communication. The simulator provided by the invention emphasizes the characteristics of safety, memory layout control and concurrency by using the Rust language, improves the memory safety during the running of the simulator and has strong robustness.)

1. A multi-core RISCV simulator based on Rust comprises a plurality of Risc-V processing core modules, a bus module, a DRAM module, a CLINT module, a PLIC module and a UART module, wherein the Risc-V processing core modules are constructed based on a Risc-V open source instruction set and used for realizing the functions of instruction fetching, decoding and execution; the DRAM module is used for simulating a memory; the PLIC module is used for simulating a hard disk; the UART module is used for simulating external interruption or local interruption; the bus module is used for controlling information interaction among the Risc-V processing core module, the bus module, the DRAM module, the CLINT module, the PLIC module and the UART module so as to realize conflict-free communication.

2. The Rust-based multi-core RISCV simulator of claim 1, wherein the simulator utilizes a Rust's threading mechanism to enable simultaneous operation of multiple hardware threads to simulate multi-core parallel operation, wherein each hardware thread has its own program counter for storing the location of the next instruction to be executed.

3. The Rust-based multi-core RISCV simulator of claim 1, wherein for a plurality of the Risc-V processing core modules, atomic instructions are implemented using the RUST lock mechanism, and when one Risc-V processing core module reads a byte, the other Risc-V processing core modules are set to not access the memory address of the byte.

4. The Rust-based multi-core RISCV simulator of claim 1, wherein the bus module is configured to lock the sub-modules by a Rust locking mechanism when it issues a read-write access command to the sub-modules connected to it, and to automatically release the lock after the read-write command is executed.

5. A simulation method of the simulator of any one of claims 1 to 4, comprising:

the parameter resolver reads simulator configuration parameters from a command line;

the simulator main function module generates a hardware thread according to the configuration parameters analyzed by the parameter analyzer, runs a plurality of Risc-V processing core modules on the hardware thread, and manages the starting and the pausing of the Risc-V processing core modules;

the main function module generates examples of a DRAM module, a CLINT module, a PLIC module and a UART module, and stores executable files into the DRAM module;

transmitting the variable references of the instances of the Risc-V processing core module, the DRAM module, the CLINT module, the PLIC module and the UART module into a bus generating function so as to complete the connection of each module and a bus;

the Risc-V processing core module obtains the executable file stored in the DRAM module through the bus and runs the designated program.

6. A method of generating a simulator as claimed in any one of claims 1 to 4, comprising the steps of:

the parameter analyzer reads the configuration parameters of the simulator from the command line, analyzes the input of the command line into initialization parameters required by the initialization of the simulator and transmits the initialization parameters into the main function module;

the main function module instantiates a DRAM module, a CLINT module, a PLIC module and a UART module according to the initialization parameters and the data structure of the corresponding module;

the main function module declares a container for accommodating a Risc-V processing core module, the element type in the container is a Thread type variable, and according to the number n of CPU cores input by a user in a command line, an equal number of hardware threads are established through Thread packets of Rust, and each Thread is pressed into the container;

and multiple threads of the Risc-V processor core module share the same set of DRAM module, CLINT module, PLIC module and UART module through the bus.

7. The generation method according to claim 6, wherein the initialization parameters include a file name to be executed, a file system ramfs file, a CPU core number, and a module name to be used.

8. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 5 to 7.

Technical Field

The invention relates to the technical field of computers, in particular to a Rust-based multi-core RISCV-CPU simulator.

Background

RISC-V is an open instruction set architecture based on the reduced instruction set computing principle, the RISC-V has a simple structure, the basic instruction set is only 40, and the RISC-V has dozens of instructions in total by adding other modularized extension instructions. RISC-V has been used in large quantities in the near term due to its advantages of complete open source, simple architecture, easy migration, etc.

The Rust language is a system programming language focusing on safety, and is mainly characterized by high running speed and memory safety. Rust guarantees the safety of memory and threads through an ownership model and a type system, enables the Rust to eliminate memory-related errors during compiling, and has performance close to C or C + +, so that Rust has an ever-increasing user group.

Simulators are important tools for architecture research and design. The software simulator has the characteristics of high development speed, low cost, easiness in modification and the like, and plays an important role in design verification, development and tuning and the like of the processor. The existing mature simulators are SimOs, QEMU and the like. QEMU is a set of simulation processors which distribute source codes by GPL license, is widely used on GNU/Linux platform, has the characteristics of high speed and cross-platform, and can simulate the speed of a computer to be close to the speed of a normal computer. In addition, the current newer heterogeneous system simulator framework takes a bus as a core, and all operation units and peripheral equipment are connected with the bus through standardized bus interfaces, so that the framework can be used for completing the construction of heterogeneous system simulation under the condition of neglecting the structural difference among modules.

Through analysis, the existing mature simulator has huge code amount and complex structure, and is not beneficial to the expansion of modules in the simulator. Moreover, at present, no mature simulator realized by using a memory-safe language exists, so that system downtime and abnormal operation caused by problems of abnormal memory access, memory overflow and the like may occur during the running of the simulator, and the existing smaller-scale simulator lacks a multi-core running mechanism.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a Rust-based multi-core RISCV-CPU simulator, which is a new technical scheme for agilely constructing a Riccv multi-core simulator with safe memory in operation.

According to the first aspect of the invention, a multi-core RISCV simulator based on Rust is provided, which comprises a plurality of Risc-V processing core modules, a bus module, a DRAM module, a CLINT module, a PLIC module and a UART module, wherein the Risc-V processing core modules are arranged and constructed based on a Risc-V open source instruction set and are used for realizing the functions of instruction fetching, decoding and execution; the DRAM module is used for simulating a memory; the PLIC module is used for simulating a hard disk; the UART module is used for simulating external interruption or local interruption; the bus module is used for controlling information interaction among the Risc-V processing core module, the bus module, the DRAM module, the CLINT module, the PLIC module and the UART module so as to realize conflict-free communication.

According to a second aspect of the present invention, there is provided a simulation method of a Rust-based multi-core RISCV simulator. The method comprises the following steps:

the parameter resolver reads simulator configuration parameters from a command line;

the simulator main function module generates a hardware thread according to the configuration parameters analyzed by the parameter analyzer, runs a plurality of Risc-V processing core modules on the hardware thread, and manages the starting and the pausing of the Risc-V processing core modules;

the main function module generates examples of a DRAM module, a CLINT module, a PLIC module and a UART module, and stores executable files into the DRAM module;

transmitting the variable references of the instances of the Risc-V processing core module, the DRAM module, the CLINT module, the PLIC module and the UART module into a bus generating function so as to complete the connection of each module and a bus;

the Risc-V processing core module obtains the executable file stored in the DRAM module through the bus and runs the designated program.

According to a third aspect of the present invention, a method for generating a Rust-based multi-core RISCV simulator is provided. The method comprises the following steps:

the parameter analyzer reads the configuration parameters of the simulator from the command line, analyzes the input of the command line into initialization parameters required by the initialization of the simulator and transmits the initialization parameters into the main function module;

the main function module instantiates a DRAM module, a CLINT module, a PLIC module and a UART module according to the initialization parameters and the data structure of the corresponding module;

the main function module declares a container for accommodating a Risc-V processing core module, the element type in the container is a Thread type variable, and according to the number n of CPU cores input by a user in a command line, an equal number of hardware threads are established through Thread packets of Rust, and each Thread is pressed into the container;

and multiple threads of the Risc-V processor core module share the same set of DRAM module, CLINT module, PLIC module and UART module through the bus.

Compared with the prior art, the secure multi-core RISCV-CPU processor simulator based on the Rust has the advantages that the framework structure is simple, and the number of processor cores in the simulator is easy to modify and can run in parallel by utilizing the thread mechanism and the locking mechanism of the Rust language. By using the Rust language, the memory security problem of the simulator and other modules during development and operation is reduced, and the robustness of the simulator is improved. The simulator provided by the invention can well exercise the programming capability of the system and deepen the understanding of the knowledge about the architecture.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a Rust-based multi-core RISCV-CPU simulator framework according to one embodiment of the present invention;

FIG. 2 is a schematic diagram of a generation flow of a multi-core RISCV-CPU simulator in accordance with one embodiment of the present invention;

FIG. 3 is a schematic flow diagram of the operation of a multi-core RISCV-CPU simulator in accordance with one embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

Referring to fig. 1, the provided multi-core RISCV-CPU simulator (also called RISCV processor simulator) based on the Rust language includes a Risc-V processing core module, a bus module, a DRAM module, a CLINT module, a PLIC module, and a UART module.

The processor core is capable of performing operations including, but not limited to, fetching, decoding, and executing. The simulator provided by the invention realizes the instruction of RV32I, wherein the lock mechanism of RUST is used to realize the atomic instruction, namely when one Risc-V processing core module reads one byte, other Risc-V processing core modules are set to be unable to access the memory address of the byte. In addition, the thread mechanism utilizing the RUST realizes the simultaneous operation of a plurality of hardware threads to simulate the parallel operation of multiple cores, wherein each hardware thread has an own program counter which stores the position of the next instruction to be executed, thereby improving the operation speed of the simulator.

Specifically, still referring to FIG. 1, the simulator framework of the provided Rust-based secure multi-core RISCV processor comprises the following sections.

And the main function module is responsible for instantiating other modules according to the initialization parameters, generating one or more hardware threads to run the Risc-V processor core, storing the executable file in a specified position and the like.

The Risc-V processing core modules are marked as RISC-V0-RISC-V n and can complete the functions of instruction fetching, decoding and execution based on the Risc-V open source instruction set structure.

And the BUS module (BUS) is responsible for connecting all the modules and realizing conflict-free communication.

The system comprises a DRAM module, a CLINT module, a PLIC module, a UART module and OTHER peripheral modules (marked as OTHER), and the simulation of a memory, a hard disk, a serial port, external interruption and local interruption is realized respectively.

The multi-core RISCV-CPU simulator can realize an agile simulation method. Referring to fig. 2, the agile simulation method of the secure RISC-V multi-core processor based on the Rust language includes.

In step S211, a start command line is acquired.

For example, the parameter parser reads simulator configuration parameters from the command line. Specifically, the simulator is started in a command line mode, the parameter parser acquires the input of the command line from the system, parses the input of the command line into initialization parameters required by the initialization of the simulator, wherein the initialization parameters include the file name of a bin file to be executed, a file system ramfs file, the number of CPU cores and other module names to be used, and transmits the initialization parameters into the main function module.

In this step, the number of RISC-V processor cores in the parameter adjustment simulator can be set by using the parameter resolver.

In step S212, the command line parameters are parsed.

And the simulator main function module generates a hardware thread according to the configuration parameters analyzed by the parameter analyzer, runs processor cores on the hardware thread and manages the starting and the pausing of the cores.

Specifically, the main function module of the simulator instantiates modules such as DRAM, VIRTIO, UART, PLIC, CLINT, and the like according to the initialization configuration and the data structure of the modules, wherein each module respectively implements simulation of a memory, a hard disk, a serial port, an external interrupt, and a local interrupt, and meanwhile, the main function module instantiates other required modules according to requirements. When the modules are instantiated, for example, the Arc type pointer variable in the Rust language is used for instantiation, so that the simulator can access other modules without conflict by a plurality of Risc-V processor core modules under the condition of setting to be multi-core.

In specific implementation, the simulator main function module declares a container for accommodating Risc-V processor cores, the element type in the container is a Thread type variable, and establishes an equal number of hardware threads by using Thread packets of Rust according to the number n of the CPU cores input by a user in a command line, and pushes each Thread into the container,

in step S213, the number of processor cores and other module information are obtained.

Specifically, the main function module generates instances of a DRAM module, a CLINT module, a PLIC module, and a UART module, and stores an executable file in the DRAM module.

Preferably, all Risc-V processor core threads share the same set of DRAM module, VIRTIO module, UART module, PLIC module and CLINT module through a bus, and in this way, the bus is utilized and a Rust lock mechanism is combined to achieve collision-free communication.

Step S214, instantiate other modules.

The bus is provided with a module interface, and the variable references of the Risc-V processing core module, the DRAM module, the CLINT module, the PLIC module and the UART module are transmitted into a bus generating function, so that the connection between the modules and the bus is completed.

The Risc-V processor core module acquires and executes the codes stored in the DRAM module through the bus, and runs the designated program.

Step S215, a hardware sub-thread running processor core is created.

Step S216, configuring the bus and connecting the modules.

FIG. 3 is a flow chart of the multi-core RISCV-CPU simulator, which is illustrated by taking the case that the simulator runs the file in bin format, and includes the following steps.

In step S311, an executable file and a file system are generated.

Firstly, a C language program is compiled into an executable file in an ELF format by using a Riscv cross compiler, then machine instructions are extracted from the executable file by using an objcopy command and stored as a bin file, and a ramfs file is made to serve as a file system.

In this step, a simulator is started using a command line, and a simulator of a configuration desired by the user is generated through the above-described generation flow of the multi-core RISCV simulator.

In step S312, the emulator stores the executable file in the DRAM.

The main function module of the simulator reads the generated bin File into the DRAM by using the File packet of the Rust and waits to be executed by the Risc-V processor core module. Likewise, the Rust File package is used to read the ramfs File into Virtio.

In step S313, the CPU sub-thread is started.

The main function module creates a plurality of CPU sub-threads and starts running.

In step S314, the CPU sub-thread checks the interrupt signal.

The method comprises the steps that a thread used by a main function module enters a cycle after N CPU sub-threads are created, whether interruption occurs or not is inquired and detected in the cycle, if yes, all threads in a thread container execute an unpark method, and execution is resumed; if not, the main thread will execute the yield _ now method to give up its time slice.

In step S315, the CPU sub-thread executes the instruction.

The CPU sub-thread executes instructions as needed.

In an application example, the Risc-V processor runs the same set of code cpu _ run, and the cpu _ run code mainly completes 3 functions, namely instruction fetching, execution and interrupt checking, which respectively correspond to 3 functions, namely fetch, execute and check _ pending.

The fetch function takes a pc variable in the Risc-V processor core as an index, reads a corresponding instruction from the Dram through the bus module, and transmits the instruction to the execute function.

After receiving the instruction to be executed, the execute function completes decoding according to the instruction format specified by the RISC-V instruction set according to the instruction content, and then executes the instruction, wherein the execution of the atomic instruction is realized by using a Lock mechanism of Rust, namely, before the instruction is executed, Lock is obtained through a Lock function in Rust language, and the Lock is automatically released after the instruction operation is finished because the life cycle is finished. In this way, the wrong operation result generated by executing the instructions in an illegal order by other cores in the instruction execution process can be prevented, and the access address conflict during the multi-core operation is avoided.

In summary, the simulator provided by the invention can connect a plurality of modules to one bus. And a plurality of sub-modules are connected with an interface on the Bus after being instantiated by using the Arc type pointer variable, and data collision is avoided by the locking mechanism access of the Rust. In the provided simulation method, a thread library is introduced into a main module, a required number of hardware threads are created in a main function thread through a spawn method in the thread library, the threads run a Risc-V processor core, and an executable file is stored in a specified position. In addition, the simulator provided by the invention emphasizes the characteristics of safety, memory layout control and concurrency by using the Rust language, and reduces errors caused by memory problems such as memory leakage during the running of the simulator. And the provided simulator has simple structure and is easy to modify and expand modules. Experiments prove that the simulator can normally run an operating system such as XV6 under the condition of being configured to be multi-core.

The present invention may be a system, method and/or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied therewith for causing a processor to implement various aspects of the present invention.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present invention may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + +, Python, or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present invention are implemented by personalizing an electronic circuit, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA), with state information of computer-readable program instructions, which can execute the computer-readable program instructions.

Aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. It is well known to those skilled in the art that implementation by hardware, by software, and by a combination of software and hardware are equivalent.

Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.