阅读说明：本技术 一种芯片隔离环设计及筛片方法 (Chip isolation ring design and screening method ) 是由 吕继平 邬海峰 王测天 钟丹 刘莹 石君 吴晓东 杨云婷 陈长风 童伟 于 2021-10-09 设计创作，主要内容包括：本发明公开了一种芯片隔离环设计及筛片方法,在保留现有隔离环设计初衷的同时,通过隔离环上设置两个PAD,进行隔离环的IV测试,通过对IV测试值进行计算和比较,判断芯片是否具有隐裂纹风险,进一步的隔离晶圆上具有隐裂纹风险的芯片,避免其流入下道工序,造成更大的损失。(The invention discloses a chip isolation ring design and a screening method, which are characterized in that while the original purpose of the existing isolation ring design is kept, two PADs are arranged on an isolation ring to carry out IV test on the isolation ring, and whether a chip has hidden crack risks or not is judged by calculating and comparing IV test values, so that the chip with hidden crack risks on a wafer is further isolated, and the chip is prevented from flowing into the next procedure to cause larger loss.)

1. A chip isolation ring design and screening method is characterized by comprising the following steps:

s1, designing an isolation ring for each chip in the chip layout design stage;

s2, in the CP test stage of the wafer, performing IV test on the isolation ring on each chip in the wafer;

s3, calculating to obtain a voltage difference value according to the IV test result of the isolating ring;

s4, judging whether the voltage difference value of each chip in the wafer is within a preset range, if so, judging the chip to be a normal chip, and otherwise, judging the chip to have hidden crack defects;

and S5, making an isolation mark on the wafer by using the chip with the hidden crack defect, and defining an isolation area of the wafer to finish screening.

2. The method of claim 1, wherein the specific method of designing the isolation ring for each chip in step S1 is as follows: the method comprises the steps of arranging a split ring capable of completely wrapping a circuit in a chip on the chip by using an isolation line, arranging a PAD at one end of the isolation line, avoiding the other end of the isolation line from the PAD, arranging the PAD at an end point after wiring is prolonged, and taking the split ring with the PAD at two end points as the isolation ring.

3. The die isolator ring design and screening method of claim 2, wherein said step S2 includes the sub-steps of:

s21, in the CP test stage of the wafer, regarding each chip in the wafer, taking one PAD on the isolation ring as a Port1 Port, and taking the other PAD as a Port2 Port;

s22, connecting a 50 omega grounding resistor at a Port 2;

s23, current I is input into Port1 in sequence₁And I₂And measuring the voltage V corresponding to the Port1₁And V₂。

4. The die paddle of claim 3The off-ring design and screening method is characterized in that the IV test conditions of each chip in the wafer in the step S2 are the same, namely, the current I input at the Port1 of each chip is₁All the same, the current I input at each chip Port1 Port₂Are all the same, and I₁≠I₂。

5. The chip isolating ring design and screening method of claim 3, wherein the step S3 is specifically: voltage V from Port1 Port₁And V₂Calculating the voltage difference Δ V = V₁ - V₂。

6. The method of claim 5, wherein the voltage difference in step S4 is within a predetermined range of: v_low≤ΔV≤V_highIn which V is_lowRepresenting a preset minimum value, V, of the stuck threshold_highRepresenting a preset maximum stuck threshold.

7. The chip isolation ring design and screening method of claim 6, wherein the stuck threshold minimum value V_lowMaximum value V of sum-and-stuck threshold_highAll obtained through the voltage difference value delta V of N chips, wherein N is the total number of the chips in the wafer.

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a chip isolation ring design and a design of a chip screening method.

Background

The production process of a semiconductor circuit is generally: after the wafer is cleaned properly (Cleaning), Oxidation (Oxidation) and deposition are performed, and finally, photolithography, etching, ion implantation and other repeated steps are performed, so that mechanical damage and cracks are inevitably generated to the wafer in the process of processing and manufacturing a circuit on the wafer.

The latent cracks initially occur at the wafer stage and cannot be easily detected completely by a high power microscope because the latent cracks are not obvious or are hidden in the intermediate layer. Subsequently, mechanical stress is applied to the wafer during dicing of the wafer. Therefore, on one hand, the originally existing hidden cracks can deepen the crack strength and enlarge the area under the action of mechanical stress, so that the defect rate of the wafer is increased. On the other hand, cracks are easily generated in the cut chips near the hidden crack area, and the chips with the cracks flow into the next process, so that the task of chip screening in the subsequent process is increased, and the packaging yield is possibly influenced. Chip cracking is one of the most serious defects in semiconductor integrated circuit packaging processes and is also the most fatal failure mode of integrated circuit packaging. It is very important to avoid the generation of cracks in chips and to detect cracked chips in time, regardless of any stage of semiconductor manufacturing.

After the wafer fabrication process is completed, each chip must be tested, which is commonly referred to as CP testing (Circuit testing). The isolation ring is a protection ring interposed between the chip and the scribe line. The isolating ring plays the most important role in preventing the chip from being damaged mechanically during cutting.

Disclosure of Invention

The invention aims to solve the problem that hidden cracks are easily generated in the process of processing and manufacturing a circuit on a wafer by a semiconductor chip, and provides a chip isolation ring design and a chip screening method.

The technical scheme of the invention is as follows: a chip isolation ring design and screening method comprises the following steps:

and S1, designing an isolation ring for each chip in the chip layout design stage.

And S2, in the CP test stage of the wafer, performing IV test on the isolation ring on each chip in the wafer.

And S3, calculating to obtain a voltage difference value according to the IV test result of the isolating ring.

And S4, judging whether the voltage difference value of each chip in the wafer is within a preset range, if so, judging that the chip is a normal chip, and otherwise, judging that the chip has a hidden crack defect.

And S5, making an isolation mark on the wafer by using the chip with the hidden crack defect, and defining an isolation area of the wafer to finish screening.

Further, the specific method for designing the isolation ring for each chip in step S1 is as follows: the method comprises the steps of arranging a split ring capable of completely wrapping a circuit in a chip on the chip by using an isolation line, arranging a PAD at one end of the isolation line, avoiding the other end of the isolation line from the PAD, arranging the PAD at an end point after wiring is prolonged, and taking the split ring with the PAD at two end points as the isolation ring.

Further, step S2 includes the following substeps:

and S21, in the CP test stage of the wafer, regarding one PAD on the isolation ring as a Port1 Port and the other PAD as a Port2 Port for each chip in the wafer.

S22, a 50 omega ground resistor is connected to Port 2.

S23, current I is input into Port1 in sequence₁And I₂And measuring the voltage V corresponding to the Port1₁And V₂。

Further, in step S2, for each chip in the wafer, it isThe IV test conditions are the same, namely the current I input at each chip Port1 Port₁All the same, the current I input at each chip Port1 Port₂Are all the same, and I₁≠I₂。

Further, step S3 is specifically: voltage V from Port1 Port₁And V₂Calculating the voltage difference Δ V = V₁ - V₂。

Further, the preset range of the voltage difference in step S4 is: v_low≤ΔV≤V_highIn which V is_lowRepresenting a preset minimum value, V, of the stuck threshold_highRepresenting a preset maximum stuck threshold.

Further, the minimum value V of the stuck threshold_lowMaximum value V of sum-and-stuck threshold_highAll obtained through the voltage difference value delta V of N chips, wherein N is the total number of the chips in the wafer.

The invention has the beneficial effects that:

(1) the invention keeps the original design intention of the existing isolation ring, simultaneously carries out the IV test of the isolation ring by arranging two PADs on the isolation ring, judges whether the chip has hidden crack risks or not by calculating and comparing the IV test value, further isolates the chip with hidden crack risks on the wafer, and avoids the chip from flowing into the next procedure to cause larger loss.

(2) In the testing process, a 50 omega grounding resistor is connected to a Port2, and by using a method of testing voltage by using input current, the voltage testing fluctuation caused by high resistance (more than 500 omega) and the fluctuation caused by low resistance (less than 5 omega) current noise can be avoided, so that good compromise of testing precision is realized, and the accuracy of hidden crack detection is ensured; meanwhile, the high-precision standard 50 omega grounding resistor has strong system compatibility and low cost.

Drawings

Fig. 1 is a flowchart illustrating a chip isolation ring design and a method for screening chips according to an embodiment of the present invention.

Fig. 2 is a schematic diagram illustrating a design of an isolation ring according to an embodiment of the present invention.

Fig. 3 is a schematic diagram illustrating a configuration and a test of a chip isolation ring port according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, not to limit the scope of the invention.

The embodiment of the invention provides a chip isolation ring design and a chip screening method, as shown in FIG. 1, the method comprises the following steps of S1-S5:

and S1, designing an isolation ring for each chip in the chip layout design stage.

In the embodiment of the invention, as shown in fig. 2, a split ring capable of completely wrapping the internal circuit of the chip is arranged on the chip by using an isolation line, a PAD (chip routing pin) is arranged at one end of the isolation line, the other end of the isolation line is kept away from the PAD, the PAD is arranged at an end point after the routing is extended, and the split ring with the PADs arranged at two end points is used as the isolation ring. Therefore, two ends of the isolating ring are respectively provided with 1 PAD, and the isolating ring can still completely wrap the internal circuit of the chip.

And S2, in the CP test stage of the wafer, performing IV test on the isolation ring on each chip in the wafer.

The step S2 includes the following substeps S21-S23:

and S21, in the CP test stage of the wafer, regarding one PAD on the isolation ring as a Port1 Port and the other PAD as a Port2 Port for each chip in the wafer.

In the embodiment of the present invention, as shown in fig. 3, the PAD on the left side of the isolation ring is referred to as a Port1 Port, and the PAD on the right side is referred to as a Port2 Port.

S22, a 50 omega ground resistor is connected to the Port2, as shown in FIG. 3.

S23, current I is input into Port1 in sequence₁And I₂And measuring the voltage V corresponding to the Port1₁And V₂As shown in fig. 3.

In the embodiment of the invention, the IV test is carried out on each chip in the waferThe test strips are identical, i.e., the current I input at each chip Port1 Port₁All the same, the current I input at each chip Port1 Port₂Are all the same, and I₁≠I₂。

S3, calculating to obtain a voltage difference value according to the IV test result of the isolation ring, namely the voltage V of the Port1₁And V₂Calculating the voltage difference Δ V = V₁ - V₂。

And S4, judging whether the voltage difference value of each chip in the wafer is within a preset range, if so, judging that the chip is a normal chip, and otherwise, judging that the chip has a hidden crack defect.

In the embodiment of the present invention, the preset range of the voltage difference is as follows: v_low≤ΔV≤V_highIn which V is_lowRepresenting a preset minimum value, V, of the stuck threshold_highRepresenting a preset maximum stuck threshold.

In the embodiment of the invention, the minimum value V of the card control threshold_lowMaximum value V of sum-and-stuck threshold_highAll obtained through the voltage difference value delta V of N chips, wherein N is the total number of the chips in the wafer. Specifically, the minimum value V of the stuck threshold in the embodiment of the present invention_lowMaximum value V of sum-and-stuck threshold_highThe voltage difference value delta V of the N chips is subjected to a large amount of data testing and then determined according to three sigma intervals of data distribution.

And S5, making an isolation mark on the wafer by using the chip with the hidden crack defect, and defining an isolation area of the wafer to finish screening.

It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.