阅读说明：本技术 一种低杂散低相噪扫频源 (Low stray low phase noise sweep frequency source ) 是由 曹晓冬 郭萌 何海星 王晗 王立玢 苏玉婷 杨磊 于 2021-07-30 设计创作，主要内容包括：本发明提供了一种低杂散低相噪扫频源,包括：锁相环芯片、环路滤波器、高稳参考时钟和中频信号处理单元,所述锁相环芯片为LMX2571芯片,所述LMX2571芯片分别与所述环路滤波器、中频信号处理单元和高稳参考时钟电连接,所述高稳参考时钟用于向LMX2571芯片提供超低相位噪声和低抖动输出,所述LMX2571芯片用于根据高稳参考时钟的输出信号输出低相噪频率源信号,所述环路滤波器用于对所述LMX2571芯片输出的频率源信号中的交流分量进行滤除并反馈回所述LMX2571芯片,所述中频信号处理单元用于对所述LMX2571芯片输出的频率源信号中中频信号提供增益。无需使用DSP或FPGA,有效减低了成本和功耗。(The invention provides a low-stray low-phase-noise sweep frequency source, which comprises: the phase-locked loop comprises a phase-locked loop chip, a loop filter, a high-stability reference clock and an intermediate frequency signal processing unit, wherein the phase-locked loop chip is an LMX2571 chip, the LMX2571 chip is respectively electrically connected with the loop filter, the intermediate frequency signal processing unit and the high-stability reference clock, the high-stability reference clock is used for providing ultralow phase noise and low jitter output for the LMX2571 chip, the LMX2571 chip is used for outputting a low phase noise frequency source signal according to an output signal of the high-stability reference clock, the loop filter is used for filtering an alternating component in a frequency source signal output by the LMX2571 chip and feeding back the alternating component to the LMX2571 chip, and the intermediate frequency signal processing unit is used for providing gain for the intermediate frequency signal in the frequency source signal output by the LMX2571 chip. And a DSP or an FPGA is not needed, so that the cost and the power consumption are effectively reduced.)

1. A low spurious low phase noise swept source, comprising: the phase-locked loop comprises a phase-locked loop chip, a loop filter, a high-stability reference clock and an intermediate frequency signal processing unit, wherein the phase-locked loop chip is an LMX2571 chip, the LMX2571 chip is respectively electrically connected with the loop filter, the intermediate frequency signal processing unit and the high-stability reference clock, the high-stability reference clock is used for providing ultralow phase noise and low jitter output for the LMX2571 chip, the LMX2571 chip is used for outputting a low phase noise frequency source signal according to an output signal of the high-stability reference clock, the loop filter is used for filtering an alternating component in a frequency source signal output by the LMX2571 chip and feeding back the alternating component to the LMX2571 chip, and the intermediate frequency signal processing unit is used for providing gain for the intermediate frequency signal in the frequency source signal output by the LMX2571 chip.

2. The low spurious low phase noise swept source of claim 1, further comprising: and the power supply unit is respectively electrically connected with the LMX2571 chip and the intermediate frequency signal processing unit, and the power supply unit provides a 3.3V power supply for the LMX2571 chip and provides a +5V power supply for the intermediate frequency signal processing unit.

3. The low spurious low phase noise source of claim 1, wherein the high stable reference clock comprises an external reference source and an internal reference source, the external reference source being electrically connected to the input source.

4. The low spurious low phase noise source of claim 3, wherein: the high-stability reference clock is a CCHD-950 crystal oscillator clock.

5. The low spurious low phase noise source of claim 1, wherein the loop filter is a passive fourth order low pass filter.

6. The low spurious low phase noise source of claim 5, wherein the passive fourth order low pass filter comprises: first electric capacity, second electric capacity, third electric capacity and fourth electric capacity, first resistance, second resistance, third resistance and fourth resistance, first electric capacity C1 first end is connected with the input electricity, second end ground, second electric capacity C2 first end ground, the second end is connected with second resistance R2 first end electricity, second resistance R2 second end is connected with the input electricity, third resistance R3 first end with the input electricity is connected, third resistance R3 second end with fourth resistance R4's first end electricity is connected, fourth resistance R4's second end is connected with the output electricity, third electric capacity C3's first end with fourth resistance R4's first end electricity is connected, third electric capacity C3's second end ground, fourth electric capacity C4's first end is connected with the output electricity, fourth electric capacity C4's second end ground.

7. The low spurious low phase noise source of claim 1, wherein said if signal processing unit comprises:

the input end of the amplifier is electrically connected with the first end of the fifth capacitor, the second end of the fifth capacitor is electrically connected with the output end of the LMX2571 chip, the positive and negative power supply ends of the amplifier are electrically connected with the ground end, the first end of the fifth resistor is electrically connected with the output end of the amplifier, the second end of the fifth resistor is electrically connected with the first end of the sixth resistor, the second end of the sixth resistor is electrically connected with the first end of the seventh capacitor, the second end of the seventh capacitor is electrically connected with the ground end, the first end of the sixth capacitor is electrically connected with the first end of the fifth resistor, and the second end of the sixth capacitor is electrically connected with the ground end.

8. The low spurious low phase noise source of claim 7, wherein the amplifier is an ERA-51SM amplifier.

Technical Field

The invention belongs to the technical field of communication, and particularly relates to a low-stray low-phase-noise frequency sweep source.

Background

Frequency sources are a critical part of modern electronic systems and are important devices that determine the performance of electronic systems. With the development of modern military affairs, national defense and wireless communication technologies, short-wave communication is often adopted in electronic systems such as radars, mobile communication, electronic measuring instruments and electronic countermeasures.

In several common communication modes of intermediate frequency communication, information is contained in the phase of a signal, and after frequency conversion is carried out on a radio frequency signal, near-end phase noise of a local vibration source is superposed on the signal, so that the signal-to-noise ratio of an output signal is deteriorated. The excessive phase noise reduces the dynamic range of the short-wave communication equipment, reduces the anti-interference capability, directly influences the communication quality, and has particularly strict requirements on the phase noise of the short-wave frequency synthesizer. If the local oscillator has stray, harmonic and the like, the stray and the harmonic enter a mixer for mixing, and an unnecessary stray signal is generated, enters a band and is amplified by an intermediate frequency amplifier, the sensitivity of a receiver is influenced, and even a false signal is generated. The technical development of the short wave receiver requires miniaturization, low power consumption, low cost and high performance, and the frequency source is used as a core component of the short wave receiver, so that the power consumption, the performance and the volume of the frequency source have great influence on the system. A traditional short wave frequency source adopts a PLL + DDS scheme, is complex to realize, and is large in size, and has quantization errors of DDS and strays caused by DA nonlinearity.

Disclosure of Invention

In view of this, the present invention provides a low-spurious low-phase-noise frequency-sweeping source to solve the technical problems of complex structure and large spurious existing in the conventional short-wave communication source.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

a low spurious low phase noise swept source, comprising: the phase-locked loop comprises a phase-locked loop chip, a loop filter, a high-stability reference clock and an intermediate frequency signal processing unit, wherein the phase-locked loop chip is an LMX2571 chip, the LMX2571 chip is respectively electrically connected with the loop filter, the intermediate frequency signal processing unit and the high-stability reference clock, the high-stability reference clock is used for providing ultralow phase noise and low jitter output for the LMX2571 chip, the LMX2571 chip is used for outputting a low phase noise frequency source signal according to an output signal of the high-stability reference clock, the loop filter is used for filtering an alternating component in a frequency source signal output by the LMX2571 chip and feeding back the alternating component to the LMX2571 chip, and the intermediate frequency signal processing unit is used for providing gain for the intermediate frequency signal in the frequency source signal output by the LMX2571 chip.

Further, the low spurious low phase noise frequency sweep source further includes: and the power supply unit is respectively electrically connected with the LMX2571 chip and the intermediate frequency signal processing unit, and the power supply unit provides a 3.3V power supply for the LMX2571 chip and provides a +5V power supply for the intermediate frequency signal processing unit.

Further, the high-stability reference clock comprises an external reference source and an internal reference source, and the external reference source is electrically connected with the input source.

Further, the high-stability reference clock is a CCHD-950 crystal oscillator clock.

Further, the loop filter is a passive fourth-order low-pass filter.

Further, the passive fourth-order low-pass filter includes: first electric capacity, second electric capacity, third electric capacity and fourth electric capacity, first resistance, second resistance, third resistance and fourth resistance, first electric capacity C1 first end is connected with the input electricity, second end ground, second electric capacity C2 first end ground, the second end is connected with second resistance R2 first end electricity, second resistance R2 second end is connected with the input electricity, third resistance R3 first end with the input electricity is connected, third resistance R3 second end with fourth resistance R4's first end electricity is connected, fourth resistance R4's second end is connected with the output electricity, third electric capacity C3's first end with fourth resistance R4's first end electricity is connected, third electric capacity C3's second end ground, fourth electric capacity C4's first end is connected with the output electricity, fourth electric capacity C4's second end ground.

Further, the intermediate frequency signal processing unit includes:

the input end of the amplifier is electrically connected with the first end of the fifth capacitor, the second end of the fifth capacitor is electrically connected with the output end of the LMX2571 chip, the positive and negative power supply ends of the amplifier are electrically connected with the ground end, the first end of the fifth resistor is electrically connected with the output end of the amplifier, the second end of the fifth resistor is electrically connected with the first end of the sixth resistor, the second end of the sixth resistor is electrically connected with the first end of the seventh capacitor, the second end of the seventh capacitor is electrically connected with the ground end, the first end of the sixth capacitor is electrically connected with the first end of the fifth resistor, and the second end of the sixth capacitor is electrically connected with the ground end.

Further, the amplifier is an ERA-51SM amplifier.

Compared with the prior art, the low-stray low-phase-noise frequency sweep source has the following advantages:

(1) the low-stray low-phase-noise frequency-sweeping source adopts a phase-locked loop chip LMX2571 to realize the miniaturization, low-phase-noise and low-stray frequency source applied to a medium-frequency transmitter. The frequency source with low phase noise is realized, and the filtering and gain control of the intermediate frequency signal processing unit at the rear end are matched, so that the stray amplitude is reduced, the common mode interference and the even harmonic wave are inhibited, and the parasitic parameters of single-ended output are avoided.

(2) According to the low-stray low-phase-noise frequency sweeping source, the phase-locked loop chip is used for realizing the low-phase-noise frequency source, and the direct digital frequency synthesis (DDS) technology is not adopted for realizing frequency modulation. Therefore, a DSP or an FPGA is not needed, and the cost and the power consumption are effectively reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of a low spurious low phase noise source according to an embodiment of the present invention;

FIG. 2 is a functional structure diagram of an LMX2571 chip in a low spurious low phase noise source according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a loop filter in a low-spurious low-phase-noise swept source according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an intermediate-frequency signal processing unit in a low-spurious low-phase-noise swept source according to an embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.

The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.

Fig. 1 is a schematic structural diagram of a low spurious low phase noise swept source provided in an embodiment of the present invention, and referring to fig. 1, the low spurious low phase noise swept source includes: the phase-locked loop comprises a phase-locked loop chip, a loop filter, a high-stability reference clock and an intermediate frequency signal processing unit, wherein the phase-locked loop chip is an LMX2571 chip, the LMX2571 chip is respectively electrically connected with the loop filter, the intermediate frequency signal processing unit and the high-stability reference clock, the high-stability reference clock is used for providing ultralow phase noise and low jitter output for the LMX2571 chip, the LMX2571 chip is used for outputting a low phase noise frequency source signal according to an output signal of the high-stability reference clock, the loop filter is used for filtering an alternating component in a frequency source signal output by the LMX2571 chip and feeding back the alternating component to the LMX2571 chip, and the intermediate frequency signal processing unit is used for providing gain for the intermediate frequency signal in the frequency source signal output by the LMX2571 chip.

The low spurious low phase noise frequency sweep source further comprises: and the power supply unit is respectively electrically connected with the LMX2571 chip and the intermediate frequency signal processing unit, and the power supply unit provides a 3.3V power supply for the LMX2571 chip and provides a +5V power supply for the intermediate frequency signal processing unit.

The high-stability reference clock can be a CCHD-950 crystal oscillator clock, which adopts a 100MHz high-stability constant-temperature crystal oscillator and switches and selects the internal reference source and the external reference source through a switch; the CCHD \ CVHD-950 series clock oscillator supports a reference signal output of 50MHz-125MHz, provides ultra-low phase noise and low jitter output, and has a noise floor as low as-168 dBc/Hz, so that sub-harmonics cannot be generated in the oscillator. The high-stability reference clock can provide an accurate and stable input clock source for the phase-locked loop.

In this embodiment, the phase-locked loop chip may adopt an MX2571 chip. The LMX2571 is a low-power-consumption and high-performance RF synthesizer, the output frequency range is 10-1344 MHz, and direct digital FSK modulation can be supported through programming. Fig. 2 is a functional structure diagram of an LMX2571 chip in the low spurious low phase noise source according to an embodiment of the present invention, and referring to fig. 2, the LMX2571 can operate in a synthesizer mode and a phase locked loop mode. The LMX2571 is internally composed of an R frequency divider, a multiplier, a phase discriminator, a loop filter, a voltage-controlled oscillator, an N frequency divider and an output frequency divider, and specific parameters of the LMX2571 are stored in a register inside the LMX2571 and can be set through programming. The R frequency divider and the multiplier are used for dividing and multiplying the input crystal oscillator frequency and controlling the frequency input to the PLL. The phase detector, the loop filter, the voltage-controlled oscillator and the N frequency divider form a phase-locked loop (PLL). The N-frequency divider comprises an integer part and a fractional part, and the FSK modulation is realized by changing the value of the N-frequency divider. The frequency output by the PLL is divided by the output frequency divider, and then the corresponding carrier frequency can be obtained. After the input frequency of the crystal oscillator and the output frequency of the LMX2571 are determined, the value of each parameter can be calculated. An RF synthesizer in the LMX2571 chip can achieve low operating power, illustratively, can support land mobile radio with low power consumption of 39mA (128mW), and battery-powered applications such as portable test and measurement equipment. And the fractional frequency division PLL with the noise PPLaTInum can realize a PLL noise substrate of-231 dBc/Hz which is 8 times of that of the similar product, thereby greatly improving the sensitivity of the receiver. And also has flexible frequency modulation: an integrated FSK modulator with an easy to use I2S interface provides flexibility and excellent performance. The FSK modulator conforms to the European Telecommunications Standards Institute (ETSI) telecommunications standards for wireless microphones and land mobile radios. And IBS can be removed using a completely new spur cancellation technique, thereby enabling engineers to maximize the use of radio channels in the design. The method has the advantages of high integration level: the integrated low dropout regulator (LDO), 5V charge pump, and fast transmit/receive (TRx) switch reduces bill of materials and solution footprint.

Specifically, the LMX2571 output frequency is:

where fref is the reference signal frequency, R is the reference branch frequency division coefficient, Nint is the integer part of the feedback branch frequency division coefficient, Nfrac is the fractional part of the feedback branch frequency division coefficient, when operating in the integer mode, the value is 0, k is the frequency division coefficient from the VCO, and according to the chip specification, it can only be an even number. The required frequency range is 40-80 MHz, so the k frequency division factor is used. The phase noise of the VCO at the low frequency band is better than that of the VCO at the high frequency band, so that the phase noise is optimized by taking the lowest frequency point of the fVCO in a reasonable range. Then Nint and Nfrac are calculated from the calculated fVCO, fref, and R, fref being 100MHz, and R being set to 1 for optimum phase noise. The PLL register comprises a plurality of frequency division coefficient registers, a charge pump register, a lock monitoring register, a VCO frequency division coefficient setting, an output power setting, a signal output setting and the like. Data writing may be accomplished in the form of an SPI bus.

Optionally, the PLL register may be operated by using a single chip, the SCK is a clock signal from the single chip, the SDI is a data signal, and the SEN is a write enable signal. The SDI has the first clock of low level to write data, and then inputs the address signal of the register and data, which is the value of the corresponding address register, and at each clock rising edge, the data is sent to the chip, and the high order is advanced, and finally downloaded to the singlechip to be executed.

When the loop filter is designed, the bandwidth needs to be considered in a compromise mode, the bandwidth is small, the influence of VCO noise is large, and the loop locking time is prolonged; the bandwidth is large, and the noise influence of the crystal oscillator and the phase discriminator is large. In this embodiment, when the phase detection frequency is 100MHz and the output frequency is 60MHz, the filter is set to be a passive fourth-order low-pass filter, the 3dB bandwidth is 90kHz, and two ends of the circuit are respectively connected to the CP pin and the VTUNE pin. Fig. 3 is a schematic structural diagram of a loop filter in the low-spurious low-phase-noise swept source according to the embodiment of the present invention, and referring to fig. 3, the loop filter is a passive fourth-order low-pass filter, and can filter an alternating current component in a frequency source signal output by the LMX2571 chip and feed back the alternating current component to the LMX2571 chip. Optionally, the passive fourth-order low-pass filter includes: first electric capacity, second electric capacity, third electric capacity and fourth electric capacity, first resistance, second resistance, third resistance and fourth resistance, first electric capacity C1 first end is connected with the input electricity, second end ground, second electric capacity C2 first end ground, the second end is connected with second resistance R2 first end electricity, second resistance R2 second end is connected with the input electricity, third resistance R3 first end with the input electricity is connected, third resistance R3 second end with fourth resistance R4's first end electricity is connected, fourth resistance R4's second end is connected with the output electricity, third electric capacity C3's first end with fourth resistance R4's first end electricity is connected, third electric capacity C3's second end ground, fourth electric capacity C4's first end is connected with the output electricity, fourth electric capacity C4's second end ground.

In this embodiment, the output power of the phase-locked loop is 0dBm at most, the second harmonic is degraded to-21 dBc, and the output of the PLL should be connected to an intermediate frequency signal processing unit, so as to amplify and filter the signal in the operating frequency band. Fig. 4 is a schematic structural diagram of an intermediate-frequency signal processing unit in a low-spurious low-phase-noise swept source according to an embodiment of the present invention, and referring to fig. 4, the intermediate-frequency signal processing unit may include: the input end of the amplifier is electrically connected with the first end of the fifth capacitor, the second end of the fifth capacitor is electrically connected with the output end of the LMX2571 chip, the positive and negative power supply ends of the amplifier are electrically connected with the ground end, the first end of the fifth resistor is electrically connected with the output end of the amplifier, the second end of the fifth resistor is electrically connected with the first end of the sixth resistor, the second end of the sixth resistor is electrically connected with the first end of the seventh capacitor, the second end of the seventh capacitor is electrically connected with the ground end, the first end of the sixth capacitor is electrically connected with the first end of the fifth resistor, and the second end of the sixth capacitor is electrically connected with the ground end. The amplifier may be an ERA-51SM amplifier. Partial gain can be provided for the intermediate frequency signal, and the weak intermediate frequency signal (lower than 0dBm) output by the phase-locked loop is amplified by the amplifier and is convenient for the normal work of the back-end gain control circuit.

The low-stray low-phase-noise frequency-sweeping source adopts a phase-locked loop chip LMX2571 to realize the miniaturization, low-phase-noise and low-stray frequency source applied to a medium-frequency transmitter. The frequency source with low phase noise is realized, and the filtering and gain control of the intermediate frequency signal processing unit at the rear end are matched, so that the stray amplitude is reduced, the common mode interference and the even harmonic wave are inhibited, and the parasitic parameters of single-ended output are avoided. And because the phase-locked loop chip is used for realizing the frequency source with low phase noise, the direct digital frequency synthesis (DDS) technology is not adopted for realizing frequency modulation. Therefore, a DSP or an FPGA is not needed, and the cost and the power consumption are effectively reduced.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.