阅读说明：本技术 一种提高芯片设计模块性能的快速环境切换方法 (Rapid environment switching method for improving performance of chip design module ) 是由 王宽德 刘运松 于 2021-07-13 设计创作，主要内容包括：本发明公开了一种提高芯片设计模块性能的快速环境切换方法,包括：依序将目标寄存器数值写入存储器；提供至少两组配置和状态寄存器；在将目标寄存器数值写入存储器后,触发将该存储器的寄存器数值写入第一组配置和状态寄存器；在完成该组配置和状态寄存器的写入后,将IP核的执行环境切换至该组配置和状态寄存器；以及在下一次环境切换前,基于下一组存储器的寄存器数值写入第二组配置和状态寄存器。本发明实施例通过至少两组配置和状态寄存器,由此可以在下一次环境切换前,完成配置和状态寄存器的写入,从而无需逐个读写寄存器,实现任务的连续执行,由此降低了性能损失。(The invention discloses a fast environment switching method for improving the performance of a chip design module, which comprises the following steps: sequentially writing the target register values into the memory; providing at least two sets of configuration and status registers; after the target register value is written into the memory, triggering to write the register value of the memory into a first group of configuration and status registers; after completing the writing of the set of configuration and status registers, switching the execution environment of the IP core to the set of configuration and status registers; and writing to a second set of configuration and status registers based on register values of a next set of memories prior to a next context switch. The embodiment of the invention can complete the writing of the configuration and state registers before the next environment switching through at least two groups of configuration and state registers, thereby realizing the continuous execution of tasks without reading and writing the registers one by one and reducing the performance loss.)

1. A fast environment switching method for improving chip design module performance is characterized by comprising the following steps:

sequentially writing the target register values into the memory;

providing at least two sets of configuration and status registers;

after the target register value is written into the memory, triggering to write the register value of the memory into a first group of configuration and status registers;

after completing the writing of the set of configuration and status registers, switching the execution environment of the IP core to the set of configuration and status registers; and

a second set of configuration and status registers is written based on register values of a next set of memories before a next context switch.

2. The fast context switch method of claim 1, further comprising:

performing a cyclic context switch between the at least two sets of configuration and status registers by a switch.

3. The fast context switch method of claim 2, wherein the switch is triggered by an executive task completion event of an IP core.

4. The fast context switch method of claim 1, wherein parameters of at least two sets of configuration and status registers are the same.

5. A task fast switching device, comprising:

at least two sets of configuration and status registers;

a processor configured to sequentially write target register values to a memory;

a microcontroller configured to trigger writing of register values of a memory to a first set of configuration and status registers after writing of target register values to the memory;

a switch configured to switch the execution environment of the IP core to the set of configuration and status registers after completing the writing of the set of configuration and status registers; and

a microcontroller further configured to write a second set of configuration and status registers based on register values of a next set of memories prior to a next context switch.

6. The task fast switching device according to claim 5,

the switch is further configured to perform a cyclic context switch between the at least two sets of configuration and status registers.

7. The task fast switching device of claim 5, wherein the toggle switch is triggered by an execute task complete event of an IP core.

8. A task fast switching device according to claim 5, characterized in that the parameters of at least two sets of configuration and status registers are identical.

9. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the fast task switching method according to any one of claims 1 to 4.

Technical Field

The invention relates to the technical field of task fast switching, in particular to a fast environment switching method for improving the performance of a chip design module.

Background

In existing chip designs, especially high performance IP cores such as video codec designs, the IP cores support a wide variety of modes in order to maximize design reusability and support legacy technology standards and formats. As the number of modes supported by IP designs increases, the number of configuration and status registers of IP cores also increases substantially. Meanwhile, due to the progress of a semiconductor process, the performance of the IP core is improved more and more, data of more tasks can be processed in unit time, and the time-sharing multiplexing of data streams of different tasks in the same IP core brings great performance improvement and flexibility to system design, but also brings more read-write cycles of configuration and state registers. In the application of the existing video codec, because each frame of image codec needs environment switching, the traditional method of reading and writing registers one by a Central Processing Unit (CPU) on a chip can cause performance loss as high as 10%.

Disclosure of Invention

The embodiment of the invention provides a quick environment switching method for improving the performance of a chip design module, which is used for solving the technical problem of performance loss caused by reading and writing registers one by one in the existing task quick switching process.

The embodiment of the disclosure provides a fast environment switching method for improving performance of a chip design module, which includes:

sequentially writing the target register values into the memory;

providing at least two sets of configuration and status registers;

after the target register value is written into the memory, triggering to write the register value of the memory into a first group of configuration and status registers;

after completing the writing of the set of configuration and status registers, switching the execution environment of the IP core to the set of configuration and status registers; and

a second set of configuration and status registers is written based on register values of a next set of memories before a next context switch.

In some embodiments, further comprising: performing a cyclic context switch between the at least two sets of configuration and status registers by a switch.

In some embodiments, the toggle switch is triggered by an executive task completion event of the IP core.

In some embodiments, the parameters of at least two sets of configuration and status registers are the same.

The embodiment of the present disclosure further provides a device for fast switching between tasks, including:

at least two sets of configuration and status registers;

a processor configured to sequentially write target register values to a memory;

a microcontroller configured to trigger writing of register values of a memory to a first set of configuration and status registers after writing of target register values to the memory;

a switch configured to switch the execution environment of the IP core to the set of configuration and status registers after completing the writing of the set of configuration and status registers; and

a microcontroller further configured to write a second set of configuration and status registers based on register values of a next set of memories prior to a next context switch.

In some embodiments, the toggle switch is further configured to perform a cyclic context switch between the at least two sets of configuration and status registers.

In some embodiments, the toggle switch is triggered by an executive task completion event of the IP core.

In some embodiments, the parameters of at least two sets of configuration and status registers are the same.

The embodiment of the present disclosure further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the foregoing task fast switching method are implemented.

The embodiment of the invention can complete the writing of the configuration and state registers before the next environment switching through at least two groups of configuration and state registers, thereby realizing the continuous execution of tasks without reading and writing the registers one by one and reducing the performance loss.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

figure 1 is a technical comparison of the disclosed method with a prior art scheme.

Fig. 2 is a basic flow diagram of the method of the present disclosure.

Fig. 3 is a basic frame structure diagram of the apparatus of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

As shown in fig. 1, in the conventional IP core environment switching, the on-chip cpu calculates the required configuration and status register values according to the next task that needs to be completed by the IP core, and waits for the completion of the current task. After the current task is completed, the central processing unit writes the numerical values into the registers of the IP cores one by one, and starts the IP cores again to execute the tasks. When the processor reads and writes the IP core register, the IP core is in an idle state. If the number of IP core registers is large, the idle period can be long affecting performance during context switches. The embodiment of the present disclosure provides a fast environment switching method for improving performance of a chip design module, as shown in fig. 2, a target register value may be sequentially written into a memory in step S201. That is, in this example, the target register value may be written into the memory by the processor, and subsequent memory writing may be performed directly after the current memory writing is completed. To address the inefficiencies of the conventional approach of having the central processor read and write one by one, a microcontroller may be integrated within the IP core in this example, so that the central processor can write register values into a block of contiguously addressed on-chip memory (e.g., static random access memory) or off-chip memory (e.g., dynamic random access memory). The IP core in this example may be an intellectual property module, and the IP core may be a chip design circuit module for implementing a specified function, which may be developed by the inventor, or may be licensed from a third party. The present example provides at least two sets of configuration and status registers in step S202, i.e., at least two sets of configuration and status registers are provided for the IP core in the present example. Then after writing the target register value into a set of memories, the writing of the register value of the memory into the first set of configuration and status registers is triggered in step S203. The writing of register values of the memory to the first set of configuration and status registers may be controlled by triggering the microcontroller in this example. After the writing of the set of configuration and status registers is completed, the execution environment of the IP core is switched to the set of configuration and status registers in step S204. Whereby the IP core can perform tasks based on the data in the current first set of configuration and status registers. And writing a second set of configuration and status registers based on register values in the next set of memories before the next context switch in step S205. The change and storage of configuration and status registers may be referred to in this example as context switching of the IP core. And the second group of configuration and status registers are in an idle state in the process of executing the tasks by the IP core and cannot be executed by the IP core, so that the register values of the next group of memories can be controlled to be written into the second group of configuration and status registers by the microcontroller. Therefore, when the IP core executes the next task, as shown in fig. 1, the IP core execution environment can be switched to the second set of configuration and status registers, thereby effectively avoiding the performance loss in the environment switching process caused by the read-in delay of the on-chip or off-chip memory and the delay of the configuration of the microcontroller inside the IP core.

In some embodiments, the parameters of at least two sets of configuration and status registers are the same. I.e. at least two sets of configuration and status registers with exactly the same configuration parameters may be configured.

In some embodiments, further comprising: performing a cyclic context switch between the at least two sets of configuration and status registers by a switch. Exemplary switching between at least two sets of configuration and status registers may be performed by means of a toggle switch. For example, a switch may be made from the first set of configuration and status registers to the second set of configuration and status registers, …, the nth set of configuration and status registers, and then to the first set of configuration and status registers. Of course, this is only one implementation manner of switching, and in a specific implementation process, the IP core may be switched to the corresponding configuration and status register through the switch to execute a task. As an exemplary situation, for example, in the case of including two sets of configuration and status registers, a "ping-pong" operation can be implemented by switching a switch, thereby effectively reducing the circuit cost, and the method of the present invention is particularly suitable for a scenario that frequent environment switching is required, such as video codec, etc., and the method of the present invention can implement fast environment switching for the video codec, and since the register value required by the next task is written in the next configuration and status register before each switching, seamless connection can be implemented after switching, thereby greatly reducing the performance loss and greatly improving the performance of the codec.

In some embodiments, the toggle switch is triggered by an executive task completion event of the IP core. That is, when the IP core completes the task execution of the current configuration and status register, the switch may be triggered to select the second set of configuration and status registers. An alternative selector, which is an exemplary toggle control, can complete the switching in one clock cycle, so the performance penalty required for context switching is almost negligible, achieving near 100% performance utilization.

According to the embodiment of the disclosure, through at least two groups of configuration and state registers, the writing of the configuration and state registers can be completed before the next environment switching, so that the registers do not need to be read and written one by one, the continuous execution of tasks is perfectly realized, and the performance loss is reduced.

An embodiment of the present disclosure further provides a device for quickly switching tasks, as shown in fig. 3, including: at least two sets of configuration and status registers; a processor configured to sequentially write target register values to a memory; a microcontroller configured to trigger writing of register values of the set of memories into a first set of configuration and status registers after writing of target register values into one of the memories; a switch configured to switch the execution environment of the IP core to the set of configuration and status registers after completing the writing of the set of configuration and status registers; and a microcontroller further configured to write a second set of configuration and status registers based on register values of a next set of memories prior to a next context switch. As shown in fig. 3, the on-chip memory may include a plurality of memories connected to the processor through an interface, and the processor may sequentially write the target register value into one of the memories. A microcontroller is connected behind the on-chip memory and is configured to trigger writing of register values of the memory into a set of configuration and status registers after writing of target register values into the memory. In some embodiments, the toggle switch is further configured to perform a cyclic context switch between the at least two sets of configuration and status registers. For example, for the case of two sets of configuration and status registers, the switch may be configured to switch back and forth between the two sets of configuration and status registers by controlling the alternative selector. An alternative selector, which is an exemplary toggle control, can complete the switching in one clock cycle, so the performance penalty required for context switching is almost negligible, and the IP core can achieve near 100% performance utilization.

In some embodiments, the parameters of at least two sets of configuration and status registers are the same. In some embodiments, the toggle switch is triggered by an executive task completion event of the IP core.

The embodiment of the present disclosure further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the foregoing task fast switching method are implemented.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.