阅读说明：本技术 一种多路cpu互联系统 (Multi-path CPU interconnection system ) 是由 黄凯 于 2021-07-29 设计创作，主要内容包括：本发明公开了一种多路CPU互联系统,包括：中背板；盲插高速信号连接器；通过中背板互联的第一、第二、第三和第四节点,每个节点包括高速信号连接器以及2个CPU,每个CPU通过超路径互联链路UPI0、UPI1、UPI2、UPI3与其他CPU互联；其中,每个CPU的UPI3连接到对应的高速信号连接器,对应的高速信号连接器通过线缆与节点上的对应的盲插高速信号连接器连接,第一和第三节点(第二和第四节点)上的UPI3对应的盲插高速信号连接器分别与固定在中背板上的由一条线缆连接的两个盲插高速信号连接器连接。通过本发明的方案,实现了节点的快速抽出与推入,提高了系统运维的效率。(The invention discloses a multi-path CPU interconnection system, comprising: a middle back plate; blind plugging a high-speed signal connector; first, second, third and fourth nodes interconnected by a midplane, each node comprising a high speed signal connector and 2 CPUs, each CPU interconnected to other CPUs by hyper path interconnection links UPI0, UPI1, UPI2, UPI 3; the UPI3 of each CPU is connected to a corresponding high-speed signal connector, the corresponding high-speed signal connector is connected to a corresponding blind-mate high-speed signal connector on a node through a cable, and the blind-mate high-speed signal connectors corresponding to the UPI3 on the first and third nodes (second and fourth nodes) are connected to two blind-mate high-speed signal connectors fixed on the midplane and connected by one cable, respectively. By the scheme of the invention, the nodes are rapidly pulled out and pushed in, and the operation and maintenance efficiency of the system is improved.)

1. A multi-CPU interconnect system, comprising:

a middle back plate;

a plurality of blind mate high speed signal connectors;

a first node, a second node, a third node, and a fourth node interconnected by the midplane, each of the first node, the second node, the third node, and the fourth node comprising a plurality of high speed signal connectors and 2 CPUs, each of the CPUs interconnected with other CPUs by hyper-path interconnection links UPI0, UPI1, UPI2, UPI 3;

the UPI3 of each CPU is connected to a corresponding high-speed signal connector through PCB wiring on a board card, the corresponding high-speed signal connector is connected with a corresponding blind-mate high-speed signal connector fixed on a node through a cable, the blind-mate high-speed signal connector corresponding to the UPI3 on the first node and the blind-mate high-speed signal connector corresponding to the UPI3 on the third node are respectively connected with two blind-mate high-speed signal connectors which are fixed on a middle back plate and connected through a cable, and the blind-mate high-speed signal connector corresponding to the UPI3 on the second node and the blind-mate high-speed signal connector corresponding to the UPI3 on the fourth node are respectively connected with two blind-mate high-speed signal connectors which are fixed on the middle back plate and connected through a cable.

2. The system of claim 1, wherein every 4 nodes make up 1 8-way CPU system;

the UPI0 of the first CPU on each node is connected with the UPI1 of the second CPU through a PCB trace on a board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node through the PCB trace on the board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the third node through the PCB trace on the board card, the UPI2 of the two CPUs on the first node are respectively and correspondingly connected with the UPI2 of the two CPUs on the second node through cables, and the UPI2 of the two CPUs on the third node are respectively and correspondingly connected with the UPI2 of the two CPUs on the fourth node through cables.

3. The system of claim 2, wherein the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node.

4. The system of claim 2, wherein the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the third node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the third node.

5. The system of claim 2, wherein the UPI2 on a first node is connected to a corresponding high-speed signal connector by PCB traces on the board, the UPI2 on a second node is connected to a corresponding high-speed signal connector by PCB traces on the board, and the high-speed signal connector corresponding to the UPI2 on the first node is connected to the high-speed signal connector corresponding to the UPI2 on the second node by the cable.

6. The system of claim 2, wherein the UPI2 on a third node is connected to a corresponding high-speed signal connector by PCB traces on the board, the UPI2 on a fourth node is connected to a corresponding high-speed signal connector by PCB traces on the board, and the high-speed signal connector corresponding to the UPI2 on a third node is connected to the high-speed signal connector corresponding to the UPI2 on a fourth node by the cable.

7. The system of claim 1, wherein said node-mounted, corresponding blind mate high speed signal connectors are mounted to a node board adjacent one side of said midplane.

8. The system of claim 1 wherein said blind mate high speed signal connector is secured to said midplane and to said node by structural fasteners and fasteners passing through said structural fasteners.

9. The system of claim 8 wherein the structural fastener includes a main body and a side wing extending from the main body, the main body including wiring holes for receiving the blind mate high speed signal connector cavities and cavity side walls, the side wing including through holes through which the fasteners are secured to the midplane and nodes.

10. The system of claim 1, wherein the blind mate high speed signal connector secured to the node is one of a male blind mate high speed signal connector or a female blind mate high speed signal connector, and the blind mate high speed signal connector secured to the midplane is the other of the female blind mate high speed signal connector or the male blind mate high speed signal connector.

Technical Field

The invention relates to the technical field of servers, in particular to a multi-path CPU interconnection system.

Background

The UPI (Ultra Path Interconnect) signal rate of interconnection between the CPUs of the previous generations is low and is lower than 11.2GT/s, PCB wiring can be directly performed in a board card, the UPI of interconnection of CPUs of a new platform is upgraded to UPI2.0, the rate can reach 20GT/s, according to performance and functional requirements, because the requirements on loss and impedance are severer due to the improvement of the signal rate, the interconnection of partial UPI signals needs to introduce the interconnection design of cables to meet the requirement on signal integrity, compared with the PCB wiring, the UPI interconnection is performed by applying cables, the impedance is smaller, the loss is lower, the signal transmissible distance is far, and the system ductility is improved. But with the introduction of cable connections, the difficulty of operation and maintenance is increased.

Disclosure of Invention

In view of this, the invention provides a multi-path CPU interconnect system, which introduces cable interconnection for a part of UPIs on the premise of meeting signal integrity, so that the impedance of the CPU interconnect system is smaller, the consumption loss is lower, the transmissible distance is longer, the ductility of the CPU interconnect system is improved, and the efficiency of system operation and maintenance is improved through blind plugging and quick dismounting of nodes.

Based on the above object, an aspect of the embodiments of the present invention provides a multi-CPU interconnect system, which specifically includes:

a middle back plate;

a plurality of blind mate high speed signal connectors;

a first node, a second node, a third node and a fourth node interconnected by a plurality of nodes connected to the midplane, each of the first node, the second node, the third node and the fourth node comprising a plurality of high speed signal connectors and 2 CPUs, each of the CPUs interconnected to other CPUs by hyper-path interconnect links UPI0, UPI1, UPI2, UPI 3;

the UPI3 of each CPU is connected to a corresponding high-speed signal connector through PCB wiring on a board card, the corresponding high-speed signal connector is connected with a corresponding blind-mate high-speed signal connector fixed on a node through a cable, the blind-mate high-speed signal connector corresponding to the UPI3 on the first node and the blind-mate high-speed signal connector corresponding to the UPI3 on the third node are respectively connected with two blind-mate high-speed signal connectors which are fixed on a middle back plate and connected through a cable, and the blind-mate high-speed signal connector corresponding to the UPI3 on the second node and the blind-mate high-speed signal connector corresponding to the UPI3 on the fourth node are respectively connected with two blind-mate high-speed signal connectors which are fixed on the middle back plate and connected through a cable.

In some embodiments, every 4 nodes make up 1 8-way CPU system;

the UPI0 of the first CPU on each node is connected with the UPI1 of the second CPU through a PCB trace on a board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node through the PCB trace on the board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the third node through the PCB trace on the board card, the UPI2 of the two CPUs on the first node are respectively and correspondingly connected with the UPI2 of the two CPUs on the second node through cables, and the UPI2 of the two CPUs on the third node are respectively and correspondingly connected with the UPI2 of the two CPUs on the fourth node through cables.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the third node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the third node.

In some embodiments, the UPI2 on the first node is connected to a corresponding high-speed signal connector by PCB traces on the board, the UPI2 on the second node is connected to a corresponding high-speed signal connector by PCB traces on the board, and the high-speed signal connector corresponding to the UPI2 on the first node is connected to the high-speed signal connector corresponding to the UPI2 on the second node by the cable.

In some embodiments, the UPI2 on the third node is connected to a corresponding high speed signal connector by PCB traces on the board, the UPI2 on the fourth node is connected to a corresponding high speed signal connector by PCB traces on the board, and the high speed signal connector corresponding to the UPI2 on the third node is connected to the high speed signal connector corresponding to the UPI2 on the fourth node by the cable.

In some embodiments, a corresponding blind mate high speed signal connector secured to a node is secured to a node board adjacent one side of the midplane.

In some embodiments, the blind mate high speed signal connector is secured to the midplane and to the node by structural fasteners and fasteners passing through the structural fasteners.

In some embodiments, the structural fastener includes a main body including a cavity for receiving the blind mate high speed signal connector and wiring holes in a sidewall of the cavity, and a wing plate extending from the main body, the wing plate including a through hole through which the fastener is secured to the midplane and the node.

In some embodiments, the blind mate high speed signal connector secured to the node is one of a blind mate high speed signal connector male header or a blind mate high speed signal connector female header, and the blind mate high speed signal connector secured to the midplane is the other of the blind mate high speed signal connector female header or the blind mate high speed signal connector male header.

In another aspect of the embodiments of the present invention, a server is further provided, which includes the following multiple CPU interconnection systems:

a middle back plate;

a plurality of blind mate high speed signal connectors;

a first node, a second node, a third node, and a fourth node interconnected by the midplane, each of the first node, the second node, the third node, and the fourth node comprising a plurality of high speed signal connectors and 2 CPUs, each of the CPUs interconnected with other CPUs by hyper-path interconnection links UPI0, UPI1, UPI2, UPI 3;

the UPI3 of each CPU is connected to a corresponding high-speed signal connector through PCB wiring on a board card, the corresponding high-speed signal connector is connected with a corresponding blind-mate high-speed signal connector fixed on a node through a cable, the blind-mate high-speed signal connector corresponding to the UPI3 on the first node and the blind-mate high-speed signal connector corresponding to the UPI3 on the third node are respectively connected with two blind-mate high-speed signal connectors which are fixed on a middle back plate and connected through a cable, and the blind-mate high-speed signal connector corresponding to the UPI3 on the second node and the blind-mate high-speed signal connector corresponding to the UPI3 on the fourth node are respectively connected with two blind-mate high-speed signal connectors which are fixed on the middle back plate and connected through a cable.

In some embodiments, every 4 nodes make up 1 8-way CPU system;

the UPI0 of the first CPU on each node is connected with the UPI1 of the second CPU through a PCB trace on a board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node through the PCB trace on the board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the third node through the PCB trace on the board card, the UPI2 of the two CPUs on the first node are respectively and correspondingly connected with the UPI2 of the two CPUs on the second node through cables, and the UPI2 of the two CPUs on the third node are respectively and correspondingly connected with the UPI2 of the two CPUs on the fourth node through cables.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the third node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the third node.

In some embodiments, the UPI2 on the first node is connected to a corresponding high-speed signal connector by PCB traces on the board, the UPI2 on the second node is connected to a corresponding high-speed signal connector by PCB traces on the board, and the high-speed signal connector corresponding to the UPI2 on the first node is connected to the high-speed signal connector corresponding to the UPI2 on the second node by the cable.

In some embodiments, the UPI2 on the third node is connected to a corresponding high speed signal connector by PCB traces on the board, the UPI2 on the fourth node is connected to a corresponding high speed signal connector by PCB traces on the board, and the high speed signal connector corresponding to the UPI2 on the third node is connected to the high speed signal connector corresponding to the UPI2 on the fourth node by the cable.

In some embodiments, a corresponding blind mate high speed signal connector secured to a node is secured to a node board adjacent one side of the midplane.

In some embodiments, the blind mate high speed signal connector is secured to the midplane and to the node by structural fasteners and fasteners passing through the structural fasteners.

In some embodiments, the structural fastener includes a main body including a cavity for receiving the blind mate high speed signal connector and wiring holes in a sidewall of the cavity, and a wing plate extending from the main body, the wing plate including a through hole through which the fastener is secured to the midplane and the node.

In some embodiments, the blind mate high speed signal connector secured to the node is one of a blind mate high speed signal connector male header or a blind mate high speed signal connector female header, and the blind mate high speed signal connector secured to the midplane is the other of the blind mate high speed signal connector female header or the blind mate high speed signal connector male header.

The invention has the following beneficial technical effects: on the premise of meeting signal integrity, the interconnection of partial UPI lead-in cables makes the impedance of a CPU interconnection system smaller, the consumed loss is lower, the transmissible distance is farther, the ductility of the CPU interconnection system is improved, meanwhile, the nodes are rapidly drawn out and pushed in through a blind-plug high-speed signal connector connected to the cables, and the operation and maintenance efficiency of the system is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an embodiment of an 8-way CPU system composed of 4 nodes provided by the present invention;

fig. 2 is a schematic diagram of an embodiment of a UPI interconnection topology provided by the present invention.

The description of the reference numerals,

10 middle back plate, 110 first blind-mate high-speed signal connector male, 120 first cable, 130 third blind-mate high-speed signal connector male, 140 second blind-mate high-speed signal connector male, 150 second cable, 160 fourth blind-mate high-speed signal connector male;

20 a first node (node 0), 200 a CPU on node 0, 202 a first CPU on node 0, 204 a second CPU on node 0, 210 a high speed signal connector on node 0, 220 a blind mate high speed signal connector female on node 0, 222 a cable on node 0;

30 second node (node 1), 300 CPU on node 1, 302 first CPU on node 1, 304 second CPU on node 1, 310 high speed signal connector on node 1, 320 female of blind mate high speed signal connector on node 1, 322 cable on node 1;

40 a third node (node 2), 400 a CPU on node 2, 402 a first CPU on node 2, 404 a second CPU on node 2, 410 a high speed signal connector on node 2, 420 a blind mate high speed signal connector female on node 2, 422 a cable on node 2;

50 fourth node (node 3), 500 CPU on node 3, 502 first CPU on node 3, 504 second CPU on node 3, 510 high speed signal connector on node 3, 520 blind mate high speed signal connector female on node 3, 522 cable on node 3.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In view of the above objects, a first aspect of the embodiments of the present invention, as shown in fig. 1, proposes an embodiment of a multi-CPU interconnect system.

The multi-CPU interconnection system specifically comprises:

a middle back plate;

a plurality of blind mate high speed signal connectors;

a first node, a second node, a third node, and a fourth node interconnected by the midplane, each of the first node, the second node, the third node, and the fourth node comprising a plurality of high speed signal connectors and 2 CPUs, each of the CPUs interconnected with other CPUs by hyper-path interconnection links UPI0, UPI1, UPI2, UPI 3; the first node, the second node, the third node and the fourth node only represent non-identical entities with the same name and do not have functional limitations.

The UPI3 of each CPU is connected to a corresponding high-speed signal connector through PCB wiring on a board card, the corresponding high-speed signal connector is connected with a corresponding blind-mate high-speed signal connector fixed on a node through a cable, the blind-mate high-speed signal connector corresponding to the UPI3 on the first node and the blind-mate high-speed signal connector corresponding to the UPI3 on the third node are respectively connected with two blind-mate high-speed signal connectors which are fixed on a middle back plate and connected through a cable, and the blind-mate high-speed signal connector corresponding to the UPI3 on the second node and the blind-mate high-speed signal connector corresponding to the UPI3 on the fourth node are respectively connected with two blind-mate high-speed signal connectors which are fixed on the middle back plate and connected through a cable.

Specifically, the CPUs of the multi-path system are interconnected through a super path interconnection link UPI, as shown in fig. 1, fig. 1 is a schematic structural diagram of an embodiment of an 8-path CPU system composed of 4 nodes, and the 8-path CPU system includes: a midplane 10, a first node 20 (node 0), a second node 30 (node 1), a third node 40 (node 2), and a fourth node 50 (node 3). Node 0 includes a CPU 200 on node 0, a high-speed signal connector 210 on node 0, and a blind-mate female high-speed signal connector 220 on node 0, where the blind-mate female high-speed signal connector 220 on node 0 is connected to a cable 222 on node 0, a hyper-path interconnection link UPI3 of the CPU 200 on node 0 is connected to the high-speed signal connector 210 on node 0 through a PCB trace (not shown in the figure) on a node board card, and the high-speed signal connector 210 on node 0 is connected to the cable 222 on node 0. Similarly, the node 1 includes a CPU 300 on the node 1, a high-speed signal connector 310 on the node 1, and a blind-mate high-speed signal connector female 320 on the node 1, where the blind-mate high-speed signal connector female 320 on the node 1 is connected with a cable 322 on the node 1, a hyper-path interconnection link UPI3 of the CPU 300 on the node 1 is connected to the high-speed signal connector 310 on the node 1 through a PCB trace on a node board, and the high-speed signal connector 310 on the node 1 is connected with the cable 322 on the node 1. The node 2 comprises a CPU 400 on the node 2, a high-speed signal connector 410 on the node 2, and a blind-mate high-speed signal connector female head 420 on the node 2, wherein a cable 422 on the node 2 is connected to the blind-mate high-speed signal connector female head 420 on the node 2, a hyper-path interconnection link UPI3 of the CPU 400 on the node 2 is connected to the high-speed signal connector 410 on the node 2 through a PCB trace on a node board card, and the high-speed signal connector 410 on the node 2 is connected to the cable 422 on the node 2. The node 3 comprises a CPU 500 on the node 3, a high-speed signal connector 510 on the node 3, and a blind-mate high-speed signal connector female 520 on the node 3, wherein a cable 522 on the node 3 is connected to the blind-mate high-speed signal connector female 520 on the node 3, a hyper-path interconnection link UPI3 of the CPU 500 on the node 3 is connected to the high-speed signal connector 510 on the node 3 through a PCB trace on a node board card, and the high-speed signal connector 510 on the node 3 is connected to the cable 522 on the node 3. The blind-mate high-speed signal connector female head 220 on the node 0 corresponding to the UPI3 output by the CPU 200 on the node 0 and the blind-mate high-speed signal connector female head 420 on the node 2 corresponding to the UPI3 output by the CPU 400 on the node 2 are respectively connected with the first and third blind-mate high-speed signal connector male heads 110 and 130 connected by the first cable 120 fixed on the midplane 10. The female connector 320 of the blind-mate high-speed signal connector on the node 1 corresponding to the UPI3 output by the CPU 300 on the node 1 and the female connector 520 of the blind-mate high-speed signal connector on the node 3 corresponding to the UPI3 output by the CPU 500 on the node 3 are respectively connected with the male connectors 140 and 160 of the second and fourth blind-mate high-speed signal connectors fixed on the midplane and connected by the second cable 150.

The blind-mate high-speed signal connector comprises a blind-mate high-speed signal connector male head and a blind-mate high-speed signal connector female head, when the blind-mate high-speed signal connector male head and the blind-mate high-speed signal connector female head are connected, the blind-mate high-speed signal connector male head and the blind-mate high-speed signal connector female head are required to be in butt joint for use, in the embodiment, the blind-mate high-speed signal connector female head is fixed on a node, the blind-mate high-speed signal connector male head is fixed on a middle back plate, the blind-mate high-speed signal connector male head can be fixed on the node when the blind-mate high-speed signal connector male head is used, and the blind-mate high-speed signal connector female head is fixed on the middle back plate.

According to the embodiment of the invention, the blind-mate high-speed signal connector connected to the cable is used for realizing the rapid extraction and pushing of the node, and the operation and maintenance efficiency of the system is improved.

In some embodiments, every 4 nodes make up 1 8-way CPU system;

the UPI0 of the first CPU on each node is connected with the UPI1 of the second CPU through a PCB trace on a board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node through the PCB trace on the board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively and correspondingly connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the third node through the PCB trace on the board card, the UPI2 of the two CPUs on the first node are connected with the UPI2 of the two CPUs on the second node through cables, and the UPI2 of the two CPUs on the third node are respectively and correspondingly connected with the UPI2 of the two CPUs on the fourth node through cables.

Specifically, as shown in fig. 2, a schematic diagram of a UPI interconnection topology for introducing cable connections is provided for the UPI interconnection architecture of an intel-based 8-way CPU system according to the present invention.

The UPI cable interconnection topology comprises: a first node 20 (node 0), a second node 30 (node 1), a third node 40 (node 2), and a fourth node 50 (node 3). Node 0 includes a first CPU 202 on node 0, a second CPU204 on node 0. Node 1 includes a first CPU 302 on node 1, a second CPU 304 on node 1. Node 2 includes a first CPU 402 on node 2, a second CPU 404 on node 2. Node 3 includes a first CPU 502 on node 3, a second CPU 504 on node 3. Each CPU is interconnected with other CPUs by the hyper path interconnection links UPI0, UPI1, UPI2 and UPI3, the UPI0, UPI1, UPI2 and UPI3 are respectively represented by 0, 1, 2 and 3 in the figure, the solid lines with arrows in the figure represent PCB traces, and the dotted lines with arrows represent cable connections.

The UPI0 of the first CPU on each node is connected with the UPI1 of the second CPU through PCB traces on a board, the UPI1 of the first CPU 202 on the node 0 and the UPI0 of the second CPU204 on the node 0 are connected with the UPI1 of the first CPU 502 on the node 3 and the UPI0 of the second CPU 504 on the node 3 respectively through PCB traces on the board, the UPI1 of the first CPU 302 on the node 1 and the UPI0 of the second CPU 304 on the node 1 are connected with the UPI1 of the first CPU 402 on the node 2 and the UPI0 of the second CPU 404 on the node 2 respectively through PCB traces on a board, the UPI 8945 of the first CPU 202 on the node 0 and the UPI2 of the second CPU204 on the node 0 are connected with the UPI2 of the first CPU 302 on the node 1, the UPI2 of the second CPU 304 on the node 1 and the UPI2 of the first CPU 402 on the node 2 and the UPI2 of the second CPU 404 on the node 1 respectively through cables, The UPI2 of the second CPU 504 on node 3 is connected.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the third node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the third node.

In some embodiments, the UPI2 on the first node is connected to a corresponding high-speed signal connector by PCB traces on the board, the UPI2 on the second node is connected to a corresponding high-speed signal connector by PCB traces on the board, and the high-speed signal connector corresponding to the UPI2 on the first node is connected to the high-speed signal connector corresponding to the UPI2 on the second node by the cable.

In some embodiments, the UPI2 on the third node is connected to a corresponding high speed signal connector by PCB traces on the board, the UPI2 on the fourth node is connected to a corresponding high speed signal connector by PCB traces on the board, and the high speed signal connector corresponding to the UPI2 on the third node is connected to the high speed signal connector corresponding to the UPI2 on the fourth node by the cable.

According to a specific example of several embodiments of the present invention, the on-node CPU output UPI2 is routed through the PCB to the high speed signal connectors and the UPI2 in node 0 and node 1, node 2 and node 3 are connected by cables. Node 0 and node 1 are interconnected by cable, node 0 and node 1 may be maintained as a unit (first drawer), node 2 and node 3 may be interconnected by cable, and node 2 and node 3 may be maintained as a unit (second drawer). In 4 nodes to be maintained by the system, the node 0 and the node 1 are in a group and can be integrally extracted and pushed in from the direction of the front window of the whole machine, and the node 2 and the node 3 are in a group and can be integrally extracted and pushed in from the direction of the front window of the whole machine.

In some embodiments, a corresponding blind mate high speed signal connector secured to a node is secured to a node board adjacent one side of the midplane.

In some embodiments, a blind mate high speed signal connector is secured to the midplane and to the node by a structural fastener and a fastener passing through the structural fastener.

In some embodiments, the structural fixings include a main body including cavities for receiving blind-mate high-speed signal connectors and routing holes in the sidewalls of the cavities, and side wings extending from the main body and including through-holes through which fasteners are secured to the midplane and the nodes.

According to specific examples of various embodiments of the present invention, the blind-mate high-speed signal connector is locked to the node by a fastener, such as a screw, and the blind-mate high-speed signal connector is locked to the middle back plate bracket by a fastener, such as a screw, using a structural fixing member, and the blind-mate high-speed signal connector can be pulled out and pushed in along with the node, so as to realize quick connection of cables and blind-mate and quick release of the system.

Preferably, the blind mate high speed signal connectors attached to the nodes are attached to the edge of the node board adjacent to one side of the midplane, which facilitates routing of cables to the UPI3, facilitating connection of the blind mate high speed signal connectors on the nodes to the blind mate high speed signal connectors on the midplane.

In some embodiments, the blind mate high speed signal connector secured to the node is one of a blind mate high speed signal connector male header or a blind mate high speed signal connector female header, and the blind mate high speed signal connector secured to the midplane is the other of the blind mate high speed signal connector female header or the blind mate high speed signal connector male header.

According to the embodiment of the invention, if the UPI connection is abnormal, in order to help research and development, customer service and clients can quickly locate the UPI fault and the specific UPI with the abnormal UPI connection, the system can collect and print the UPI connection information in the BIOS log, and perform notification action by checking the degradation information or the abnormal connection information of the abnormal UPI connection displayed in the BIOS log. The BIOS sends a degradation log to the BMC based on the status of each UPI, such as bandwidth reduction or no connection, and outputs degradation information. The fault reporting information in the degradation log comprises which UPI of which CPU is not well connected, so that if the UPI of the CPU is abnormal, the fault can be quickly positioned without being checked one by one, fault diagnosis can be effectively and efficiently carried out, and nodes can be quickly pulled out and pushed in through a blind-plugging high-speed signal connector, so that the service operation and maintenance efficiency is improved, and the debug time is reduced.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a server, including the following multi-CPU interconnection system:

a middle back plate;

a plurality of blind mate high speed signal connectors;

a first node, a second node, a third node, and a fourth node interconnected by the midplane, each of the first node, the second node, the third node, and the fourth node comprising a plurality of high speed signal connectors and 2 CPUs, each of the CPUs interconnected with other CPUs by hyper-path interconnection links UPI0, UPI1, UPI2, UPI 3;

the UPI3 of each CPU is connected to a corresponding high-speed signal connector through PCB wiring on a board card, the corresponding high-speed signal connector is connected with a corresponding blind-mate high-speed signal connector fixed on a node through a cable, the blind-mate high-speed signal connector corresponding to the UPI3 on the first node and the blind-mate high-speed signal connector corresponding to the UPI3 on the third node are respectively connected with two blind-mate high-speed signal connectors which are fixed on a middle back plate and connected through a cable, and the blind-mate high-speed signal connector corresponding to the UPI3 on the second node and the blind-mate high-speed signal connector corresponding to the UPI3 on the fourth node are respectively connected with two blind-mate high-speed signal connectors which are fixed on the middle back plate and connected through a cable.

In some embodiments, every 4 nodes make up 1 8-way CPU system;

the UPI0 of the first CPU on each node is connected with the UPI1 of the second CPU through a PCB trace on a board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node through the PCB trace on the board card, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively and correspondingly connected with the UPI1 of the first CPU and the UPI0 of the second CPU on the third node through the PCB trace on the board card, the UPI2 of the two CPUs on the first node are connected with the UPI2 of the two CPUs on the second node through cables, and the UPI2 of the two CPUs on the third node are respectively and correspondingly connected with the UPI2 of the two CPUs on the fourth node through cables.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the first node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the fourth node.

In some embodiments, the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, the UPI1 of the first CPU and the UPI0 of the second CPU on the third node are respectively connected to the corresponding high-speed signal connectors through PCB traces on the board, and the UPI1 of the first CPU and the UPI0 of the second CPU on the second node are respectively connected to the corresponding high-speed signal connectors of the UPI1 of the first CPU and the UPI0 of the second CPU on the third node.

In some embodiments, the UPI2 on the first node is connected to a corresponding high-speed signal connector by PCB traces on the board, the UPI2 on the second node is connected to a corresponding high-speed signal connector by PCB traces on the board, and the high-speed signal connector corresponding to the UPI2 on the first node is connected to the high-speed signal connector corresponding to the UPI2 on the second node by the cable.

In some embodiments, the UPI2 on the third node is connected to a corresponding high speed signal connector by PCB traces on the board, the UPI2 on the fourth node is connected to a corresponding high speed signal connector by PCB traces on the board, and the high speed signal connector corresponding to the UPI2 on the third node is connected to the high speed signal connector corresponding to the UPI2 on the fourth node by the cable.

In some embodiments, a corresponding blind mate high speed signal connector secured to a node is secured to a node board adjacent one side of the midplane.

In some embodiments, a blind mate high speed signal connector is secured to the midplane and to the node by a structural fastener and a fastener passing through the structural fastener.

In some embodiments, the structural fixings include a main body including cavities for receiving blind-mate high-speed signal connectors and routing holes in the sidewalls of the cavities, and side wings extending from the main body and including through-holes through which fasteners are secured to the midplane and the nodes.

In some embodiments, the blind mate high speed signal connector secured to the node is one of a blind mate high speed signal connector male header or a blind mate high speed signal connector female header, and the blind mate high speed signal connector secured to the midplane is the other of the blind mate high speed signal connector female header or the blind mate high speed signal connector male header.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.