阅读说明：本技术 一种ddr sdram的自检方法 (Self-checking method of DDR SDRAM ) 是由 杨海涛 张伟彬 刘丽君 于 2021-07-20 设计创作，主要内容包括：本发明提供了一种DDRSDRAM的自检方法,所述方法包括：S10、写入0x5555AAAA；S20、回读并判断读取值与写入值是否相同,若是,转至S30,否则结束自检；S30、写入0xAAAA5555；S40、回读并判断读取值与写入值是否相同,若是,转至S50,否则结束自检；S50、判断S10至S40的循环次数是否达到预设次数,若是,转至S60,否则转至S10；S60、写入低16位与高16位为互补数的立即数；S70、回读并判断读取值与写入值是否相同,若是,转至S80,否则结束自检；S80、写入0xFFFF0000；S90、回读并判断读取值与写入值是否相同,若是,转至S100,否则结束自检；S100、写入0x0000FFFF；S110、回读并判断读取值与写入值是否相同,若是,判断自检正常,否则结束自检。本发明能解决现有自检方法故障覆盖率和测试效率均较低的技术问题。(The invention provides a self-checking method of a DDRSDRAM (dynamic random access memory), which comprises the following steps: s10, writing 0x5555 AAAA; s20, reading back and judging whether the read value is the same as the write value, if so, turning to S30, otherwise, finishing self-checking; s30, write 0xAAA 5555; s40, reading back and judging whether the read value is the same as the write value, if so, turning to S50, otherwise, finishing self-checking; s50, judging whether the cycle times from S10 to S40 reach the preset times, if so, turning to S60, otherwise, turning to S10; s60, writing an immediate number with the lower 16 bits and the upper 16 bits as complementary numbers; s70, reading back and judging whether the read value is the same as the write value, if so, turning to S80, otherwise, finishing self-checking; s80, writing 0xFFFF 0000; s90, reading back and judging whether the read value and the write value are the same, if so, turning to S100, otherwise, finishing self-checking; s100, writing 0x0000 FFFF; and S110, reading back and judging whether the read value is the same as the write value, if so, judging that the self-checking is normal, and if not, finishing the self-checking. The invention can solve the technical problems of low fault coverage rate and low test efficiency of the existing self-checking method.)

1. A self-checking method of DDR SDRAM, the method comprising:

s10, writing an immediate 0x5555AAAA into the DDR SDRAM address;

s20, reading back, judging whether the read value is the same as the write value, if so, turning to S30, otherwise, finishing self-checking;

s30, writing an immediate 0xAAA 5555 into the DDR SDRAM address;

s40, reading back, judging whether the read value is the same as the write value, if so, turning to S50, otherwise, finishing self-checking;

s50, judging whether the cycle times from S10 to S40 reach the preset times, if so, turning to S60, otherwise, turning to S10;

s60, writing an immediate number with 16 low bits and 16 high bits as complementary numbers into the DDR SDRAM address;

s70, reading back, judging whether the read value is the same as the write value, if so, turning to S80, otherwise, finishing self-checking;

s80, writing an immediate 0xFFFF0000 into the DDR SDRAM address;

s90, reading back, judging whether the read value is the same as the write value, if so, turning to S100, otherwise, finishing self-checking;

s100, writing an immediate 0x0000FFFF into the DDR SDRAM address;

and S110, reading back, judging whether the read value is the same as the write value, if so, judging that the DDR SDRAM self-checking is normal, otherwise, finishing the self-checking.

2. The method according to claim 1, wherein the preset number of times is 4 times in S50.

3. The method of claim 1, wherein in S60, the immediate value with the 16 lower bits and the 16 upper bits being complementary numbers is 0 xffffe 0001.

4. The method of claim 1, wherein in S20, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

5. The method of claim 1, wherein in S40, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

6. The method of claim 1, wherein in S70, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

7. The method of claim 1, wherein in S90, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

8. The method of claim 1, wherein in S110, before finishing the self-test, an error flag is set to report a DDR SDRAM failure.

9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 8 when executing the computer program.

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a self-checking method of DDR SDRAM.

Background

DDR SDRAM has become the mainstream of external memory at present due to a series of advantages of high speed, large capacity, high cost performance and the like. There is an increasing demand for DDR SDRAM by current computers. Before the DDR SDRAM is used, effective self-checking must be carried out on the DDR SDRAM, the traditional detection method is long in time consumption and low in efficiency, and meanwhile, connection faults of devices and faults of the devices cannot be eliminated.

Therefore, the fault coverage rate and the test efficiency of the self-test are improved, and the problem that the test and verification of the current DDR SDRAM product needs to be solved urgently is solved.

Disclosure of Invention

The invention provides a DDR SDRAM self-checking method which can solve the technical problems of low fault coverage rate and low test efficiency of the conventional DDR SDRAM self-checking method.

According to an aspect of the present invention, there is provided a self-checking method of a DDR SDRAM, the method comprising:

s10, writing an immediate 0x5555AAAA into the DDR SDRAM address;

s20, reading back, judging whether the read value is the same as the write value, if so, turning to S30, otherwise, finishing self-checking;

s30, writing an immediate 0xAAA 5555 into the DDR SDRAM address;

s40, reading back, judging whether the read value is the same as the write value, if so, turning to S50, otherwise, finishing self-checking;

s50, judging whether the cycle times from S10 to S40 reach the preset times, if so, turning to S60, otherwise, turning to S10;

s60, writing an immediate number with 16 low bits and 16 high bits as complementary numbers into the DDR SDRAM address;

s70, reading back, judging whether the read value is the same as the write value, if so, turning to S80, otherwise, finishing self-checking;

s80, writing an immediate 0xFFFF0000 into the DDR SDRAM address;

s90, reading back, judging whether the read value is the same as the write value, if so, turning to S100, otherwise, finishing self-checking;

s100, writing an immediate 0x0000FFFF into the DDR SDRAM address;

and S110, reading back, judging whether the read value is the same as the write value, if so, judging that the DDR SDRAM self-checking is normal, otherwise, finishing the self-checking.

Preferably, in S50, the preset number of times is 4.

Preferably, in S60, the immediate value in which the lower 16 bits and the upper 16 bits are complementary numbers is 0xFFFE 0001.

Preferably, in S20, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

Preferably, in S40, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

Preferably, in S70, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

Preferably, in S90, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

Preferably, in S110, before finishing the self-test, an error flag is set to report a DDR SDRAM fault.

According to a further aspect of the present invention, there is provided a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing any of the methods described above when executing the computer program.

By applying the technical scheme of the invention, the connection fault test of the DDR SDRAM is completed by writing the preset number of times of immediate numbers 0x5555AAAA and 0xAAA 5555 into the DDR SDRAM address; writing an immediate number with 16 low bits and 16 high bits as complementary numbers into the DDR SDRAM address to complete the signal integrity test of the DDR SDRAM; and writing immediate numbers 0xFFFF0000 and 0x0000FFFF into the DDR SDRAM address to complete the power integrity and device defect test of the DDR SDRAM. The self-checking method has the advantages of ingenious conception, simple flow, convenient transplantation, easy popularization and the like, improves the fault coverage rate and the testing efficiency of the DDR SDRAM self-checking, and can be widely used for testing and verifying the current DDR SDRAM hardware products.

Drawings

The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

FIG. 1 illustrates a flow diagram of a method for self-checking a DDR SDRAM provided according to an embodiment of the present invention;

FIG. 2 illustrates a diagram of DDR SDRAM self-test coverage provided according to an embodiment of the present invention.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

The relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

As shown in fig. 1 and 2, the present invention provides a self-checking method for DDR SDRAM, the method comprising:

s10, writing an immediate 0x5555AAAA into the DDR SDRAM address;

s20, reading back, judging whether the read value is the same as the write value, if so, turning to S30, otherwise, finishing self-checking;

s30, writing an immediate 0xAAA 5555 into the DDR SDRAM address;

s40, reading back, judging whether the read value is the same as the write value, if so, turning to S50, otherwise, finishing self-checking;

s50, judging whether the cycle times from S10 to S40 reach the preset times, if so, turning to S60, otherwise, turning to S10;

s60, writing an immediate number with 16 low bits and 16 high bits as complementary numbers into the DDR SDRAM address;

s70, reading back, judging whether the read value is the same as the write value, if so, turning to S80, otherwise, finishing self-checking;

s80, writing an immediate 0xFFFF0000 into the DDR SDRAM address;

s90, reading back, judging whether the read value is the same as the write value, if so, turning to S100, otherwise, finishing self-checking;

s100, writing an immediate 0x0000FFFF into the DDR SDRAM address;

and S110, reading back, judging whether the read value is the same as the write value, if so, judging that the DDR SDRAM self-checking is normal, otherwise, finishing the self-checking.

According to the invention, the DDR SDRAM connection fault test is completed by writing the preset number of times of immediate numbers 0x5555AAAA and 0xAAA 5555 into the DDR SDRAM address; writing an immediate number with 16 low bits and 16 high bits as complementary numbers into the DDR SDRAM address to complete the signal integrity test of the DDR SDRAM; and writing immediate numbers 0xFFFF0000 and 0x0000FFFF into the DDR SDRAM address to complete the power integrity and device defect test of the DDR SDRAM. The self-checking method has the advantages of ingenious conception, simple flow, convenient transplantation, easy popularization and the like, improves the fault coverage rate and the testing efficiency of the DDR SDRAM self-checking, and can be widely used for testing and verifying the current DDR SDRAM hardware products.

In S20, before finishing the self-test, an error flag is set to signal a DDR SDRAM fault, according to an embodiment of the present invention.

In S40, before finishing the self-test, an error flag is set to signal a DDR SDRAM fault, according to an embodiment of the present invention.

In S50, the preset number of times is 4 times according to an embodiment of the present invention.

In the invention, the data lines traverse 0 and 1 by writing the immediate 0x5555AAAA into the DDR SDRAM address and reading back; the immediate 0xAAAA5555 is rewritten and read back, traversing each memory cell address line through 0 and 1. If a connection failure occurs, a phenomenon of a read-back data error occurs. Meanwhile, the test of the data written in the whole area is considered, the time is wasted, whether the data can be stably read and written under the condition that 1 group of data is written and the burst access cannot be verified, and by combining the characteristic of the read and write time sequence of the DDR SDRAM, the invention designs the test quantity to write 4 groups of same data into continuous addresses, namely, the immediate data of 0x5555AAAA and 0xAAA 5555 are continuously written for 4 times, thereby not only considering the test efficiency, but also ensuring the test coverage.

In S60, the immediate value with the 16 lower bits and the 16 upper bits being complementary numbers is 0 xffffe 0001 according to an embodiment of the present invention.

According to the invention, according to the characteristic that a double-edge trigger structure is adopted by the DDR SDRAM and two data are transmitted in each clock period, data with the maximum overturning characteristic are written in the rising edge and the falling edge of a clock, the integrity of a signal is tested, and the fault of a device of the DDR SDRAM is tested through the maximum overturning design of data transmission by a data line. Specifically, the data with the maximum flip characteristic may adopt 0xFFFE0001, and the immediate satisfies that the data line reads 0 and 1 respectively at the rising edge and the falling edge of the clock. By the method, the device can continuously read address data wrongly under the condition of not matching the initialization parameters, and the problems of controller setting and device matching can be tested.

In S70, before finishing the self-test, an error flag is set to signal a DDR SDRAM fault, according to an embodiment of the present invention.

In S90, before finishing the self-test, an error flag is set to signal a DDR SDRAM fault, according to an embodiment of the present invention.

In S110, before finishing the self-test, an error flag is set to report a DDR SDRAM fault according to an embodiment of the present invention.

In the invention, the maximum inversion of data line transmission is realized by writing the immediate values of 0xFFFF0000 and 0x0000FFFF, and the performance and the defects of the device power supply are ensured to be tested under the condition that the power consumption of the power supply is maximum.

The invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements any of the above methods when executing the computer program.

Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of the present invention should not be construed as being limited.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.