阅读说明：本技术 Ⅲ族氮化物增强型hemt器件及其制造方法 (III-nitride enhanced HEMT device and manufacturing method thereof ) 是由 宁殿华 蒋胜 柳永胜 程新 于 2021-08-05 设计创作，主要内容包括：本发明揭示了一种Ⅲ族氮化物增强型HEMT器件及其制造方法,所述制造方法包括：提供衬底；在衬底上外延生长沟道层；在沟道层上外延生长绝缘介质层；在绝缘介质层上的栅极区域中形成栅极；刻蚀栅极区域以外的绝缘介质层；基于选择区域生长工艺在绝缘介质层以外的沟道层上外延生长势垒层；刻蚀Ⅲ族氮化物异质结,形成源极区域和漏极区域；在源极区域和漏极区域中分别形成源极和漏极。本发明基于选择区域生长工艺优先在沟道层形成绝缘介质层和栅极,而后在绝缘介质层以外区域的沟道层生长势垒层,从而一次性形成断开的二维电子气通道；本发明无需传统工艺中对栅极或势垒层表面进行的刻蚀或离子注入处理,有效避免了传统工艺带来的刻蚀损伤或晶格损伤。(The invention discloses a III-nitride enhanced HEMT device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing a substrate; epitaxially growing a channel layer on a substrate; epitaxially growing an insulating medium layer on the channel layer; forming a gate in the gate region on the insulating dielectric layer; etching the insulating medium layer outside the gate region; epitaxially growing a barrier layer on the channel layer outside the insulating medium layer based on a selective area growth process; etching the III-nitride heterojunction to form a source region and a drain region; a source and a drain are formed in the source region and the drain region, respectively. The invention is based on the selection area growth process to preferentially form an insulating medium layer and a grid electrode on a channel layer, and then grow a barrier layer on the channel layer in an area outside the insulating medium layer, thereby forming a disconnected two-dimensional electron gas channel at one time; the invention does not need etching or ion implantation treatment on the surface of the grid or the barrier layer in the traditional process, and effectively avoids etching damage or lattice damage brought by the traditional process.)

1. A method of fabricating a group iii nitride enhanced HEMT device, the method comprising:

providing a substrate;

epitaxially growing a channel layer on a substrate, wherein the channel layer is a III-nitride channel layer;

epitaxially growing an insulating medium layer on the channel layer;

forming a gate in the gate region on the insulating dielectric layer;

etching the insulating medium layer outside the gate region;

epitaxially growing a barrier layer on the channel layer outside the insulating medium layer based on a selective area growth process, wherein the barrier layer is a III-nitride barrier layer, and the channel layer and the barrier layer form a III-nitride heterojunction;

etching the III-nitride heterojunction to form a source region and a drain region;

a source and a drain are formed in the source region and the drain region, respectively.

2. The method of manufacturing a group iii nitride enhanced HEMT device according to claim 1, wherein said substrate is any one of a silicon substrate, a sapphire substrate, a silicon carbide substrate; and/or the presence of a gas in the gas,

the insulating medium layer is one or a combination of multiple of a silicon nitride layer, a silicon oxide layer, an aluminum nitride layer and a gallium oxide layer, and the thickness of the insulating medium layer is 5-20 nm; and/or the presence of a gas in the gas,

a buffer layer is formed on the substrate, and the buffer layer is one or a combination of more of a gallium nitride buffer layer, an aluminum nitride buffer layer and an aluminum gallium nitrogen buffer layer; and/or the presence of a gas in the gas,

isolation layers are formed in the channel layer and the barrier layer and are aluminum nitride isolation layers; and/or the presence of a gas in the gas,

the III-group nitride heterojunction is an AlGaN/GaN heterojunction; and/or the presence of a gas in the gas,

the channel layer is a GaN channel layer, and the thickness of the channel layer is 50 nm-2 mu m; and/or the presence of a gas in the gas,

the barrier layer is Al_xGaN_1-xThe barrier layer has a thickness of 10nm to 30nm, wherein x is 0.1 to 0.3.

3. The method of manufacturing a group iii nitride enhanced HEMT device according to claim 1, further comprising:

epitaxially growing a plurality of passivation layers on the barrier layer; and a process for the preparation of a coating,

electrode field plates are formed on the passivation layer.

4. The method of manufacturing a group iii nitride enhanced HEMT device according to claim 1, further comprising:

epitaxially growing a first passivation layer on the barrier layer, the gate, the source and the drain;

etching the first passivation layer to expose the gate;

forming a gate field plate electrically connected with the gate electrode on the first passivation layer;

epitaxially growing a second dielectric layer on the first passivation layer and the gate field plate;

etching the second passivation layer to expose the source and drain electrodes;

forming a source field plate electrically connected with the source electrode and/or a drain field plate electrically connected with the drain electrode on the second passivation layer;

epitaxially growing a third dielectric layer on the second passivation layer and the source field plate and/or the drain field plate;

and etching the third dielectric layer to expose all or part of the source field plate and/or the drain field plate.

5. The method for manufacturing the group iii nitride enhanced HEMT device according to claim 4, wherein the gate, the source electrode, the drain electrode, the gate field plate, the source field plate and/or the drain field plate is made of a metal and/or a metal compound, wherein the metal comprises one or more of gold, platinum, nickel, titanium, aluminum, palladium, tantalum and tungsten, and the metal compound comprises one or more of titanium nitride and tantalum nitride; and/or the presence of a gas in the gas,

the first passivation layer is one or the combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; and/or the presence of a gas in the gas,

the second passivation layer is one or the combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; and/or the presence of a gas in the gas,

the third passivation layer is one or the combination of a plurality of silicon nitride passivation layers, silicon oxide passivation layers and polyimide passivation layers.

6. The method for manufacturing the group iii nitride enhanced HEMT device of claim 4, wherein in the method for manufacturing, the first passivation layer, and/or the second passivation layer, and/or the third passivation layer is etched by a dry etching process and/or a wet etching process;

the dry etching process adopts plasma for etching, and the wet etching process adopts acidic solution or alkaline solution for etching.

7. The method of manufacturing a group iii nitride enhanced HEMT device according to claim 1, wherein in said method of manufacturing, "etching the group iii nitride heterojunction to form the source region and the drain region" specifically is:

etching all or part of the barrier layer to form a source electrode region and a drain electrode region; or the like, or, alternatively,

and etching all the barrier layer and part of the channel layer to form a source electrode area and a drain electrode area.

8. The method of manufacturing a group iii nitride enhanced HEMT device according to claim 1, further comprising:

performing passive region isolation in the III-nitride heterojunction beside the source electrode and/or the drain electrode by adopting an ion implantation process or an etching process to form an isolation region;

wherein, the ion in the ion implantation process is O ion or F ion, and the etching gas in the etching process is BCl₃Or Cl₂。

9. A group iii nitride enhanced HEMT device manufactured by the manufacturing method according to any one of claims 1 to 8, the group iii nitride enhanced HEMT device comprising:

a substrate;

a channel layer on the substrate, the channel layer being a group III-nitride channel layer;

the insulating medium layer is positioned in the gate region on the channel layer;

the grid is positioned on the insulating medium layer;

the barrier layer is positioned on the channel layer outside the insulating medium layer, the barrier layer is a III-group nitride barrier layer, and the channel layer and the barrier layer form a III-group nitride heterojunction;

a source region and a drain region formed in the group III nitride heterojunction;

and a source and a drain in the source region and the drain region.

10. The group iii-nitride-enhanced HEMT device of claim 9, further comprising passivation layers and electrode field plates.

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor device and a manufacturing method thereof.

Background

Gallium nitride (GaN) -based High Electron Mobility Transistors (HEMTs) have been widely used in the field of power electronic devices such as high temperature, high frequency, high voltage, and high power because gallium nitride materials have the advantages of large forbidden bandwidth, large breakdown field intensity, high carrier saturation mobility, and the like. The channel modulation mechanism of the high electron mobility transistor formed based on the AlGaN/GaN heterostructure belongs to a depletion mode (D-mode), and the channel modulation mechanism has strong spontaneous polarization and piezoelectric polarization effects and can generate high-concentration carriers, namely two-dimensional electron gas (2DEG), at an interface. However, from the viewpoint of safe operation and low power consumption of the application, an enhanced (E-mode) power transistor is preferred by circuit designers, and the use of the enhanced power transistor can avoid the use of a negative voltage power supply to simplify the design of the gate driving circuit.

Currently, several mainstream techniques for fabricating gan enhancement devices include gate recess, fluorine ion implantation, and p-type gan gate. An etching process is needed in the gate groove technology, and damage caused by the etching process can cause increase of gate leakage and uneven threshold voltage; the problem of poor stability of threshold voltage under high field and high temperature stress can occur by adopting the fluorine ion implantation technology; the p-type gallium nitride gate technology needs to additionally grow a layer of p-type gallium nitride epitaxy, the technology is high in cost, growth uniformity and magnesium (Mg) activation of the p-type gallium nitride are difficulties of the technology, etching is needed to remove the p-type gallium nitride outside a gate region, etching damage is also brought to the process, interface characteristics of a transistor are poor, meanwhile, the p-type gallium nitride gate is low in withstand voltage and usually smaller than +7V, and difficulty in circuit design is increased.

Selective-area growth (SAG) has been used for the growth of p-type gan, and enhancement transistors fabricated by this technique have been reported in succession, which mainly uses Metal-Organic Chemical vapor Deposition (MOCVD) system to selectively grow p-type gan on the gate region of the algan/gan heterostructure using silicon oxide as a hard mask. The technology has the advantages that the etching step in the technical route of manufacturing the enhancement transistor by using the conventional p-type gallium nitride is not needed, the etching damage of the aluminum gallium nitride surface is avoided, and the current collapse effect caused by the surface defect can be effectively reduced. In addition, it has been reported that AlGaN is grown by selective area growth, but it is rarely applied to the fabrication of enhancement transistors.

Therefore, in view of the above technical problems, it is necessary to provide a group iii nitride enhanced HEMT device and a method for manufacturing the same.

Disclosure of Invention

In view of the above, the present invention provides a group iii nitride enhanced HEMT device and a method of manufacturing the same.

In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:

a method of fabricating a group iii nitride enhanced HEMT device, the method of fabricating comprising:

providing a substrate;

epitaxially growing a channel layer on a substrate, wherein the channel layer is a III-nitride channel layer;

epitaxially growing an insulating medium layer on the channel layer;

forming a gate in the gate region on the insulating dielectric layer;

etching the insulating medium layer outside the gate region;

epitaxially growing a barrier layer on the channel layer outside the insulating medium layer based on a selective area growth process, wherein the barrier layer is a III-nitride barrier layer, and the channel layer and the barrier layer form a III-nitride heterojunction;

etching the III-nitride heterojunction to form a source region and a drain region;

a source and a drain are formed in the source region and the drain region, respectively.

In one embodiment, the substrate is any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate; and/or the presence of a gas in the gas,

the insulating medium layer is one or a combination of multiple of a silicon nitride layer, a silicon oxide layer, an aluminum nitride layer and a gallium oxide layer, and the thickness of the insulating medium layer is 5-20 nm; and/or the presence of a gas in the gas,

a buffer layer is formed on the substrate, and the buffer layer is one or a combination of more of a gallium nitride buffer layer, an aluminum nitride buffer layer and an aluminum gallium nitrogen buffer layer; and/or the presence of a gas in the gas,

isolation layers are formed in the channel layer and the barrier layer and are aluminum nitride isolation layers; and/or the presence of a gas in the gas,

the III-group nitride heterojunction is an AlGaN/GaN heterojunction; and/or the presence of a gas in the gas,

the channel layer is a GaN channel layer, and the thickness of the channel layer is 50 nm-2 mu m; and/or the presence of a gas in the gas,

the barrier layer is Al_xGaN_1-xThe barrier layer has a thickness of 10nm to 30nm, wherein x is 0.1 to 0.3.

In one embodiment, the method of manufacturing further comprises:

epitaxially growing a plurality of passivation layers on the barrier layer; and a process for the preparation of a coating,

electrode field plates are formed on the passivation layer.

In one embodiment, the method of manufacturing further comprises:

epitaxially growing a first passivation layer on the barrier layer, the gate, the source and the drain;

etching the first passivation layer to expose the gate;

forming a gate field plate electrically connected with the gate electrode on the first passivation layer;

epitaxially growing a second dielectric layer on the first passivation layer and the gate field plate;

etching the second passivation layer to expose the source and drain electrodes;

forming a source field plate electrically connected with the source electrode and/or a drain field plate electrically connected with the drain electrode on the second passivation layer;

epitaxially growing a third dielectric layer on the second passivation layer and the source field plate and/or the drain field plate;

and etching the third dielectric layer to expose all or part of the source field plate and/or the drain field plate.

In one embodiment, the gate, the source electrode, the drain electrode, the gate field plate, the source field plate and/or the drain field plate are made of metal and/or metal compound, the metal includes one or more of gold, platinum, nickel, titanium, aluminum, palladium, tantalum and tungsten, and the metal compound includes one or more of titanium nitride and tantalum nitride; and/or the presence of a gas in the gas,

the first passivation layer is one or the combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; and/or the presence of a gas in the gas,

the second passivation layer is one or the combination of more of a silicon nitride passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer; and/or the presence of a gas in the gas,

the third passivation layer is one or the combination of a plurality of silicon nitride passivation layers, silicon oxide passivation layers and polyimide passivation layers.

In one embodiment, in the manufacturing method, the first passivation layer, and/or the second passivation layer, and/or the third passivation layer are etched by a dry etching process and/or a wet etching process;

the dry etching process adopts plasma for etching, and the wet etching process adopts acidic solution or alkaline solution for etching.

In one embodiment, in the manufacturing method, "etching the group iii nitride heterojunction to form the source region and the drain region" specifically includes:

etching all or part of the barrier layer to form a source electrode region and a drain electrode region; or the like, or, alternatively,

and etching all the barrier layer and part of the channel layer to form a source electrode area and a drain electrode area.

In one embodiment, the method of manufacturing further comprises:

performing passive region isolation in the III-nitride heterojunction beside the source electrode and/or the drain electrode by adopting an ion implantation process or an etching process to form an isolation region;

therein, get awayThe ion in the sub-implantation process is O ion or F ion, and the etching gas in the etching process is BCl₃Or Cl₂。

The technical scheme provided by another embodiment of the invention is as follows:

a group iii nitride-enhanced HEMT device manufactured by the manufacturing method described above, the group iii nitride-enhanced HEMT device comprising:

a substrate;

a channel layer on the substrate, the channel layer being a group III-nitride channel layer;

the insulating medium layer is positioned in the gate region on the channel layer;

the grid is positioned on the insulating medium layer;

the barrier layer is positioned on the channel layer outside the insulating medium layer, the barrier layer is a III-group nitride barrier layer, and the channel layer and the barrier layer form a III-group nitride heterojunction;

a source region and a drain region formed in the group III nitride heterojunction;

and a source and a drain in the source region and the drain region.

In one embodiment, the group iii nitride enhanced HEMT device further comprises passivation layers and electrode field plates.

The invention has the following beneficial effects:

the invention is based on the selection area growth process to preferentially form an insulating medium layer and a grid electrode on a channel layer, and then grow a barrier layer on the channel layer in an area outside the insulating medium layer, thereby forming a disconnected two-dimensional electron gas channel at one time;

the invention does not need etching or ion implantation treatment on the surface of the grid or the barrier layer in the traditional process, and effectively avoids etching damage or lattice damage brought by the traditional process.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural view of a group iii nitride enhanced HEMT device in an embodiment of the present invention;

fig. 2 to 15 are process flow diagrams of a method for manufacturing a group iii nitride enhanced HEMT device in an embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, a group iii nitride enhanced HEMT device in an embodiment of the present invention comprises:

a substrate 10;

a buffer layer 20 on the substrate 10;

a channel layer 30 on the buffer layer 20, the channel layer 30 being a group iii nitride channel layer;

an insulating dielectric layer 70 located on the channel layer 30 in the gate region;

a gate electrode 63 on the insulating dielectric layer;

a barrier layer 40 on the channel layer 30 outside the dielectric layer 70, the barrier layer 40 being a group iii nitride barrier layer, the channel layer 30 and the barrier layer 40 forming a group iii nitride heterojunction, the channel layer 30 having a two-dimensional electron gas 2DEG formed therein;

a source region and a drain region formed in the group iii nitride heterojunction, the source region and the drain region in the present embodiment being formed in a portion of the barrier layer 40, and in other embodiments being formed in all of the barrier layer 40 and a portion of the channel layer 30;

a source electrode 61 and a drain electrode 62 in the source region and the drain region;

a first passivation layer 51 over the barrier layer 40 and the source, drain and gate electrodes 61, 62, 63;

a gate field plate 631 positioned above the first passivation layer 51 and electrically connected to the gate electrode 63;

a second passivation layer 52 over the gate field plate 631 and the first passivation layer 51;

a source field plate 611 located above the second passivation layer 52 and electrically connected to the source electrode 61;

and a third passivation layer 53 over the source field plate 611 and the second passivation layer 52.

The group iii nitride enhanced HEMT device and the method of manufacturing the same in this embodiment will be described in detail below with reference to the accompanying drawings.

Referring to fig. 2, first, a buffer layer 20 and a channel layer 30 are epitaxially grown on a substrate 10.

Wherein the substrate 10 is a silicon (Si) substrate or sapphire (Al)₂O₃) Any one of a substrate, a silicon carbide (SiC) substrate, and the like; the buffer layer 20 is one or a combination of plural kinds of a GaN buffer layer, an AlN buffer layer, an AlGaN buffer layer, and the like; the channel layer 30 is a group iii nitride, GaN channel layer in this embodiment, and has a thickness of 50nm to 2 μm.

Preferably, a spacer layer (not shown) may be further grown on the channel layer 30, and the spacer layer may be a nitride spacer layer, such as an aluminum nitride spacer (AlN spacer).

Referring to fig. 3, an insulating dielectric layer 70 is epitaxially grown on the channel layer 30.

The insulating medium layer can be silicon nitride (SiN) layer or silicon oxide (SiO)₂) Layer, alumina (Al)₂O₃) Layer, aluminum nitride (AlN) layer, gallium oxide (Ga)₂O₃) The composite dielectric layer is composed of one or more insulating media in the layers and the like, and the thickness of the insulating dielectric layer is 5-20 nm.

Referring to fig. 4, a gate 63 is formed in the gate region on an insulating dielectric layer 70.

The gate may be made of a high melting point metal such as platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), or a metal compound or alloy such as titanium nitride (TiN), tantalum nitride (TaN), tungsten titanium (WTi). The gate forming method may be evaporation or sputtering, and after formation, the photoresist and the excess metal may be removed by stripping, or the metal outside the gate region may be removed by metal etching.

At this time, the gate electrode, the insulating dielectric layer and the Semiconductor layer thereunder form a Metal-Insulator-Semiconductor (MIS) structure.

Referring to fig. 5, the insulating dielectric layer 70 outside the gate region is etched.

The etching mode preferably considers that acid or alkaline solution is selected for wet etching according to the material of the insulating medium layer, and dry low-damage plasma etching can also be selected.

Referring to fig. 6, a barrier layer 40 is epitaxially grown on the channel layer 30 outside the insulating dielectric layer 70 based on a selective area growth process.

The barrier layer 40 in this embodiment is Al_xGaN_1-xThe barrier layer has a thickness of 10nm to 30nm, wherein x is 0.1 to 0.3. The channel layer 30 and the barrier layer 40 form an AlGaN/GaN heterojunction.

At this time, Al grows in the region other than the insulating dielectric layer 70_xGaN_1-xThe barrier layer is directly contacted with the GaN channel layer, the AlGaN/GaN heterojunction structure can generate two-dimensional electron gas 2DEG in the channel layer 30 due to spontaneous polarization and piezoelectric polarization effects, the insulating medium layer 70 and the grid electrode 63 are difficult to form or a small amount of irregular-shaped AlGaN is difficult to form, two-dimensional electron gas cannot be generated below the AlGaN/GaN heterojunction structure, and the effect of naturally forming an enhancement mode (E-mode) on a depletion mode (D-mode) epitaxy is achieved on the whole. Compared with the traditional methods for manufacturing the enhanced mode (E-mode) by using a grid groove, fluorine ion injection, a p-type gallium nitride grid and the like, the method avoids etching damage or lattice damage caused by a production process.

Referring to fig. 7, the group iii nitride heterojunction is etched to form a source region and a drain region. The method specifically comprises the following steps:

etching all or part of the barrier layer 40 to form a source region and a drain region; or the like, or, alternatively,

all of the barrier layer 40 and a portion of the channel layer 30 are etched to form a source region and a drain region.

In this embodiment, a plasma pre-etching process is used to etch a portion of barrier layer 40 to form a source region 601 and a drain region 602, where the etching plasma may be BCl₃、Cl₂、SiCl₄And mixed plasmas thereof. The pre-etching process can remove AlGaN possibly existing on the insulating medium and the gate metal, and is beneficial to reducing the annealing temperature or the annealing time of the ohmic metal, so that the ohmic metal and the semiconductor layer can form ohmic contact better.

Of course, the remaining barrier layer 40 and a portion of the channel layer 30 may be ohmic etched in other embodiments.

Referring to fig. 8, a source electrode 61 and a drain electrode 62 are formed in a source region 601 and a drain region 602, respectively.

The source-drain metal material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), and the like, or may include metal compounds such as titanium nitride (TiN), tantalum nitride (TaN), and the like. The metal forming mode can be evaporation or sputtering, and after the metal forming mode is formed, the photoresist and the redundant metal can be removed in a stripping mode, and the metal of the area outside the source drain can also be removed in a metal etching mode.

Referring to fig. 9, a first passivation layer 51 is epitaxially grown over the barrier layer 40 and the gate electrode 63, the source electrode 61, and the drain electrode 62.

The first passivation layer may be made of insulating media such as silicon nitride, silicon oxide, aluminum oxide, or the like, or a composite medium composed of different insulating media. The first passivation layer may be planarized by Chemical Mechanical Polishing (CMP) after it has been grown.

Referring to fig. 10, an ion implantation process or an etching process is used to perform passive region isolation in the iii-nitride heterojunction beside the source electrode 61 and the drain electrode 62, thereby forming an isolation region 80.

The isolation step is carried out on the passive region, the isolation can adopt an ion implantation process to implant strong electronegative O ions or F ions and the like,or etching process with BCl as etching gas₃、Cl₂And the like.

If the isolation mode adopts an etching process, the step can also be carried out before the formation of the source and drain metal, and at the moment, the first passivation layer is not formed, so that the etching depth can be reduced and the etching time can be shortened.

Referring to fig. 11, the first passivation layer 51 is etched to form source, drain and gate windows over the source, drain and gate electrodes, respectively.

The window forming mode can be dry plasma etching, or wet etching by using acid or alkaline solution, or a mode of combining dry etching and wet etching.

Preferably, the dielectric near the surface of the AlGaN barrier layer can be removed by wet etching or low-damage etching, so as to reduce the damage to the AlGaN surface.

Referring to fig. 12, a gate field plate 631 electrically connected to the gate electrode 63 is formed over the first passivation layer 51.

The gate field plate material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., or may include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal forming mode can be evaporation or sputtering, and the photoresist and the redundant metal can be removed in a stripping mode after the metal forming mode is formed, or the redundant metal can be removed in a metal etching mode.

Referring to fig. 13, a second dielectric layer 52 is epitaxially grown on the first passivation layer 51 and the gate field plate 631, and the second passivation layer 52 is etched to expose the source electrode 61 and the drain electrode 62.

The second passivation layer may be made of insulating medium such as silicon nitride and silicon oxide, or composite medium composed of different insulating media. The second passivation layer may be planarized by Chemical Mechanical Polishing (CMP) after it has been grown.

And forming windows in the source electrode region and the drain electrode region, wherein the window forming mode can be dry plasma etching, or wet etching by using an acid solution, or a mode of combining the dry etching and the wet etching.

Referring to fig. 14, a source field plate 611 electrically connected to the source electrode 61 is formed on the second passivation layer 52.

The source field plate material may include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), etc., or may include metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The source field plate metal can be formed by evaporation or sputtering, and the photoresist and the redundant metal can be removed by stripping after the source field plate metal is formed, or the metal in the region except the source field plate and the drain electrode can be removed by metal etching.

Referring to fig. 15, a third dielectric layer 53 is epitaxially grown on the second passivation layer 52 and the source field plate, and the third dielectric layer is etched to expose the source field plate and the drain electrode.

The third passivation layer may be made of insulating media such as silicon nitride, silicon oxide, Polyimide (PI), or a composite medium made of different insulating media. The third passivation layer may be planarized by Chemical Mechanical Polishing (CMP) after it has been grown.

And then, forming windows in the source electrode area and the drain electrode area, wherein the window forming mode can be dry plasma etching, or wet etching by selecting acid solution according to the material of the dielectric layer, or a mode combining the dry etching and the wet etching.

It should be understood that, in the above embodiments, the gate field plate and the source field plate are taken as examples for description, and correspondingly, the second passivation layer and the third passivation layer need to be continued to be extended on the first passivation layer, in other embodiments, the gate field plate and the source field plate may not be provided, or the drain field plate is added, which all belong to the protection scope of the present invention.

According to the technical scheme, the invention has the following advantages:

the invention is based on the selection area growth process to preferentially form an insulating medium layer and a grid electrode on a channel layer, and then grow a barrier layer on the channel layer in an area outside the insulating medium layer, thereby forming a disconnected two-dimensional electron gas channel at one time;

the invention does not need etching or ion implantation treatment on the surface of the grid or the barrier layer in the traditional process, and effectively avoids etching damage or lattice damage brought by the traditional process.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.