阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 张钦彤 石峰 刘源 贾楠 刘自瑞 于 2020-05-06 设计创作，主要内容包括：本申请提供半导体结构及其形成方法,所述半导体结构包括：半导体衬底；依次位于所述半导体衬底上的栅介电层、金属栅极；位于所述金属栅极底部和两侧的氧化铝阻挡层；位于所述氧化铝阻挡层底部和侧壁的铝膜；以及位于所述栅介电层和所述铝膜两侧的侧墙。本申请所述的半导体结构及其形成方法,制备方法简单,可以提高生产效率,减少产品颗粒缺陷,并且可以通过控制所述铝膜的厚度来控制栅极阈值电压。(The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: a semiconductor substrate; a gate dielectric layer and a metal gate sequentially on the semiconductor substrate; the aluminum oxide barrier layers are positioned at the bottom and two sides of the metal grid; the aluminum films are positioned at the bottom and the side wall of the aluminum oxide barrier layer; and the side walls are positioned on the two sides of the gate dielectric layer and the aluminum film. The semiconductor structure and the forming method thereof have the advantages that the preparation method is simple, the production efficiency can be improved, the particle defects of products are reduced, and the gate threshold voltage can be controlled by controlling the thickness of the aluminum film.)

1. A method of forming a semiconductor structure, comprising:

providing a semiconductor substrate, wherein a gate dielectric layer, a pseudo gate layer and side walls positioned on two sides of the gate dielectric layer and the pseudo gate layer are sequentially formed on the semiconductor substrate;

removing the dummy gate layer to form an opening;

forming an aluminum film on the bottom and the side wall of the opening;

forming an aluminum oxide barrier layer on the surface of the aluminum film;

and forming a metal grid on the surface of the alumina barrier layer, wherein the metal grid fills the opening.

2. The method of forming a semiconductor structure of claim 1, wherein the aluminum film has a thickness of 25 to 35 angstroms.

3. The method of forming a semiconductor structure of claim 1, wherein the forming a barrier layer of aluminum oxide on the surface of the aluminum film comprises: and exposing the semiconductor structure in the air to oxidize the surface of the aluminum film to form the aluminum oxide barrier layer.

4. The method of forming a semiconductor structure of claim 1, wherein the forming a barrier layer of aluminum oxide on the surface of the aluminum film comprises: disposing the semiconductor structure in a reaction chamber; and introducing oxygen into the reaction cavity to oxidize the surface of the aluminum film to form the aluminum oxide barrier layer.

5. The method of forming a semiconductor structure of claim 1, wherein the aluminum oxide barrier layer has a thickness of 10 to 20 angstroms.

6. The method of claim 1, wherein the metal gate comprises a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer.

7. The method of forming a semiconductor structure of claim 1, further comprising: and forming a cap layer on the surface of the gate dielectric layer, wherein the cap layer comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a nitrogen-rich titanium nitride layer positioned on the surface of the titanium metal layer.

8. A semiconductor structure, comprising:

a semiconductor substrate;

a gate dielectric layer and a metal gate sequentially on the semiconductor substrate;

the aluminum oxide barrier layers are positioned at the bottom and two sides of the metal grid;

the aluminum films are positioned at the bottom and the side wall of the aluminum oxide barrier layer; and

and the side walls are positioned on the two sides of the gate dielectric layer and the aluminum film.

9. The semiconductor structure of claim 8, wherein the metal gate comprises a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer.

10. The semiconductor structure of claim 8, wherein the aluminum film has a thickness of 5 to 25 angstroms.

11. The semiconductor structure of claim 8, wherein the aluminum oxide barrier layer has a thickness of 10 to 20 angstroms.

12. The semiconductor structure of claim 8, further comprising: and the cap layer is positioned on the surface of the gate dielectric layer and comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a nitrogen-rich titanium nitride layer positioned on the surface of the titanium metal layer.

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the continuous development of semiconductor technology, semiconductor technology has penetrated into various fields in life, such as aerospace, medical device rings, and mobile phone communication, which are all independent of chips prepared by semiconductor technology. An important component of a semiconductor device is a metal gate, however, metal atoms in the metal gate can diffuse into a gate dielectric layer to affect the threshold voltage of the device, so a barrier layer is required to control the diffusion of the metal atoms to control the threshold voltage.

However, the barrier layer forming process in the gate structure of the semiconductor device still has the problem of difficult control, and a more effective or reliable technical solution is needed.

Disclosure of Invention

The application provides a semiconductor structure and a forming method thereof, which can control the threshold voltage of a grid electrode and improve the production efficiency.

One aspect of the present application provides a method of forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a gate dielectric layer, a pseudo gate layer and side walls positioned on two sides of the gate dielectric layer and the pseudo gate layer are sequentially formed on the semiconductor substrate; removing the dummy gate layer to form an opening; forming an aluminum film on the bottom and the side wall of the opening; forming an aluminum oxide barrier layer on the surface of the aluminum film; and forming a metal grid on the surface of the alumina barrier layer, wherein the metal grid fills the opening.

In some embodiments of the present application, the aluminum film has a thickness of 25 to 35 angstroms.

In some embodiments of the present application, the method of forming an aluminum oxide barrier layer on the surface of the aluminum film includes: and exposing the semiconductor structure in the air to oxidize the surface of the aluminum film to form the aluminum oxide barrier layer.

In some embodiments of the present application, the method of forming an aluminum oxide barrier layer on the surface of the aluminum film includes: disposing the semiconductor structure in a reaction chamber; and introducing oxygen into the reaction cavity to oxidize the surface of the aluminum film to form the aluminum oxide barrier layer.

In some embodiments of the present application, the alumina barrier layer has a thickness of 10 to 20 angstroms.

In some embodiments of the present application, the metal gate includes a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer.

In some embodiments of the present application, the method of forming a semiconductor structure further comprises: and forming a cap layer on the surface of the gate dielectric layer, wherein the cap layer comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a nitrogen-rich titanium nitride layer positioned on the surface of the titanium metal layer.

Another aspect of the present application also provides a semiconductor structure comprising: a semiconductor substrate; a gate dielectric layer and a metal gate sequentially on the semiconductor substrate; the aluminum oxide barrier layers are positioned at the bottom and two sides of the metal grid; the aluminum films are positioned at the bottom and the side wall of the aluminum oxide barrier layer; and the side walls are positioned on the two sides of the gate dielectric layer and the aluminum film.

In some embodiments of the present application, the metal gate includes a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer.

In some embodiments of the present application, the aluminum film has a thickness of 5 to 25 angstroms.

In some embodiments of the present application, the alumina barrier layer has a thickness of 10 to 20 angstroms.

In some embodiments of the present application, the semiconductor structure further comprises: and the cap layer is positioned on the surface of the gate dielectric layer and comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a nitrogen-rich titanium nitride layer positioned on the surface of the titanium metal layer.

The semiconductor structure and the forming method thereof have the advantages that the preparation method is simple, the production efficiency can be improved, the particle defects of products are reduced, and the gate threshold voltage can be controlled by controlling the thickness of the aluminum film.

Drawings

The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:

fig. 1 to 10 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.

Detailed Description

The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

Currently, in some metal gate structures, tantalum nitride is commonly used as a barrier layer, and the tantalum nitride barrier layer is commonly prepared by using an atomic layer deposition method. However, due to the properties of tantalum nitride materials and the technical characteristics of the atomic layer deposition method, the tantalum nitride barrier layer prepared by the method is easy to generate particle defects, and the method for monitoring the preparation process in the production process is few, is not easy to control, and has low production efficiency and high preparation cost.

In view of the above problems, the present application provides a method for forming a semiconductor structure using an aluminum oxide material as a barrier layer, the aluminum oxide being formed by oxidation of an aluminum film, the manufacturing method being simple, low in cost, high in production efficiency, easy to control, and capable of reducing particle defects.

An embodiment of the present application provides a method for forming a semiconductor structure, including: referring to fig. 4, a semiconductor substrate 100 is provided, wherein a gate dielectric layer 110, a dummy gate layer 120, and spacers 130 located at two sides of the gate dielectric layer 110 and the dummy gate layer 120 are sequentially formed on the semiconductor substrate 100; referring to fig. 6, the dummy gate layer 120 is removed to form an opening 121; referring to fig. 7, an aluminum film 150 is formed on the bottom and sidewalls of the opening 121; referring to fig. 8, an aluminum oxide barrier layer 160 is formed on the surface of the aluminum film 150; referring to fig. 9, a metal gate 170 is formed on the surface of the alumina barrier layer 160, and the metal gate 170 fills the opening 121.

Fig. 1 to 10 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. The semiconductor structure is, for example, an NMOS device.

Referring to fig. 1, a semiconductor substrate 100 is provided. The material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 100 may also be a structure grown with an epitaxial layer.

Referring to fig. 2, a gate dielectric material layer 110a and a dummy gate material layer 120a are sequentially formed on the semiconductor substrate 100. In some embodiments of the present application, the method of forming the gate dielectric material layer 110a and the dummy gate material layer 120a includes a chemical vapor deposition process or a physical vapor deposition process.

Referring to fig. 3, the gate dielectric material layer 110a and the dummy gate material layer 120a are etched to form a gate dielectric layer 110 and a dummy gate layer 120.

In some embodiments of the present application, the method for etching the gate dielectric material layer 110a and the dummy gate material layer 120a includes dry etching or wet etching.

In some embodiments of the present application, the gate dielectric layer 110 may be a composite structure formed by multiple dielectric layers, for example, including a first dielectric layer and a second dielectric layer sequentially disposed on the semiconductor substrate 100. Wherein the material of the first dielectric layer is silicon oxide, for example; the material of the second dielectric layer is hafnium oxide, for example.

In some embodiments of the present application, the material of the gate dielectric layer 110 may include silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, aluminum oxide, and the like.

In some embodiments of the present application, the material of the dummy gate layer 120 may include polysilicon.

In some embodiments of the present application, the method of forming a semiconductor structure further comprises: and forming a cap layer (not shown in the figure) on the surface of the gate dielectric layer 120, wherein the cap layer comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a nitrogen-rich titanium nitride layer positioned on the surface of the titanium metal layer. The double-layer structure of the titanium metal layer and the nitrogen-rich titanium nitride layer is used as the cap layer, so that the problems of high electric leakage, poor thermal stability, low breakdown voltage and the like can be avoided under the condition of not influencing the thickness of an equivalent oxide layer.

Referring to fig. 4, spacers 130 are formed on both sides of the gate dielectric layer 110 and the dummy gate layer 120. The sidewall spacers 130 may protect the gate dielectric layer 110 and the dummy gate layer 120.

In some embodiments of the present application, the material of the sidewall spacers 130 includes silicon nitride or silicon oxide.

In some embodiments of the present application, the sidewall spacer 130 may have a single-layer structure. In other embodiments of the present application, the sidewall spacer 130 may also be a multi-layer composite structure, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride structure.

In some embodiments of the present application, the method for forming the sidewall spacers 130 on both sides of the gate dielectric layer 110 and the dummy gate layer 120 includes: forming a side wall material layer on the semiconductor substrate 100 and the dummy gate layer 120; and etching the side wall material layer to form the side wall 130.

In some embodiments of the present disclosure, the method for forming the sidewall material layer on the semiconductor substrate 100 and the dummy gate layer 120 includes a chemical vapor deposition process or a physical vapor deposition process.

In some embodiments of the present application, the method for etching the spacer material layer to form the spacer 130 includes wet etching.

Referring to fig. 5, a dielectric layer 140 is formed on the semiconductor substrate 100, and the top of the dielectric layer 140 is flush with the upper surface of the dummy gate layer 120. The dielectric layer 140 can flatten the surface of the semiconductor structure, thereby improving the accuracy of etching the dummy gate layer 120 in the subsequent process.

In some embodiments of the present application, the method of forming a dielectric layer 140 on the semiconductor substrate 100, wherein the method of forming the dielectric layer 140 to be flush with the upper surface of the dummy gate layer 120 includes: dielectric layer 140 is formed on semiconductor substrate 100 and on dummy gate layer 120, and dielectric layer 140 above the upper surface of dummy gate layer 120 is removed by a chemical mechanical polishing process. The material of the dielectric layer 140 is, for example, silicon oxide.

Referring to fig. 6, the dummy gate layer 120 is removed to form an opening 121. The opening 121 is used to fill a metal gate.

In some embodiments of the present application, the method for removing the dummy gate layer 120 includes wet etching or dry etching.

Referring to fig. 7, an aluminum film 150 is formed on the bottom and sidewalls of the opening 121. On one hand, the surface of the aluminum film 150 may be oxidized to generate aluminum oxide as a barrier layer to prevent the metal of the metal gate from diffusing into the gate dielectric layer 110; on the other hand, aluminum atoms of the aluminum film 150 may diffuse into the gate dielectric layer 110 to adjust a device threshold voltage. The reason for choosing to use an aluminum film includes: the work function of the metal aluminum meets the requirement of a metal gate in an NMOS device on the work function; the oxide of metallic aluminum, alumina, is readily formed; and can be used as a material for blocking the diffusion of metal atoms; the price of metallic aluminum is relatively cheap.

Compared with the conventional semiconductor structure process in which the diffusion of metal gate metal atoms is difficult to control, the method for forming a semiconductor structure provided by the present application can control the amount of aluminum atoms diffused into the gate dielectric layer 110 by controlling the thickness of the aluminum film 150, thereby controlling the threshold voltage. Specifically, the lower the thickness of the aluminum film 150, the less aluminum atoms can diffuse into the gate dielectric layer 110, and the higher the threshold voltage; conversely, the higher the thickness of the aluminum film 150, the more aluminum atoms can diffuse into the gate dielectric layer 110, and the lower the threshold voltage.

In some embodiments of the present application, the thickness of the aluminum film 150 is 25 to 35 angstroms, such as 25 angstroms, 30 angstroms, 35 angstroms, or the like. Since a portion of the aluminum film 150 is oxidized, the thickness of the aluminum film 150 is slightly thicker than the actual requirement, and a certain thickness is reserved for the subsequent oxidation.

In some embodiments of the present application, the method of forming the aluminum film 150 on the bottom and both sides of the opening 121 includes a physical vapor deposition method. Compared with an atomic layer deposition method for forming a barrier layer in a conventional process, the physical vapor deposition method is easy to control and has higher deposition efficiency. The process parameters of the physical vapor deposition method comprise: the sputtering power is 1500W to 2500W, and the larger the sputtering power is, the faster the deposition rate is, and the larger the grain size is; the reaction pressure is 1mTorr to 5mTorr, and the larger the reaction pressure is, the smaller the grain size is, and the higher the film hardness is; the reaction temperature is 200 to 400 ℃, and the higher the reaction temperature is, the larger the crystal grain size is. In the actual process, specific process parameters can be set according to needs.

Referring to fig. 8, an alumina barrier layer 160 is formed on the surface of the aluminum film 150. Alumina possesses very stable properties and can prevent diffusion of metal atoms in metal gates. It should be noted that the dimensional ratio in the drawings does not represent a real dimensional ratio, and is merely for the sake of brevity and convenience to describe the position relationship, shape structure, and the like between the structures in the semiconductor structure, for example, the alumina barrier layer 160 is a thin film formed by oxidizing the surface of the aluminum film 150, and the alumina barrier layer 160 is enlarged in the drawings to more clearly describe the alumina barrier layer 160.

In some embodiments of the present application, the method of forming the alumina barrier layer 160 on the surface of the aluminum film 150 includes: exposing the semiconductor structure to air oxidizes the surface of the aluminum film 150 to form the aluminum oxide barrier layer 160. The natural oxidation time is more than 30 minutes. The method utilizes the characteristic that aluminum metal can be naturally oxidized in the air to oxidize and form aluminum oxide, has simple process and does not need additional cost, but has slower natural oxidation speed and lower production efficiency.

In other embodiments of the present application, the method for forming the aluminum oxide barrier layer 160 on the surface of the aluminum film 150 includes: disposing the semiconductor structure in a reaction chamber; and introducing oxygen into the reaction cavity to oxidize the surface of the aluminum film 150 to form the aluminum oxide barrier layer 160. The method oxidizes the aluminum film 150 to form aluminum oxide by actively supplying oxygen, has higher oxidation speed and higher production efficiency, and has no worry about any accidental damage to a semiconductor structure but certain additional cost because a reaction site is in a reaction cavity and is not exposed to air.

In some embodiments of the present application, the alumina barrier layer 160 has a thickness of 10 to 20 angstroms, such as 10 angstroms, 15 angstroms, or 20 angstroms. Since a part of the aluminum film was oxidized, the thickness of the remaining aluminum film was 5 to 25 angstroms.

In the method for forming a semiconductor structure provided by the present application, the amount of metal atoms diffused from the metal gate into the gate dielectric layer 110 can be controlled by controlling the thickness of the aluminum oxide barrier layer 160, so as to control the threshold voltage. Specifically, the higher the thickness of the alumina barrier layer 160, the stronger the ability to block diffusion of metal gate metal atoms; conversely, the higher the thickness of the alumina barrier layer 160, the lower the ability to block diffusion of metal gate metal atoms. In actual production, the oxidation time can be controlled according to requirements to control the thickness of the alumina barrier layer.

Compared with the conventional process in which a barrier layer for blocking the diffusion of metal gate metal atoms is formed by an atomic layer deposition method, the method for forming a semiconductor structure provided by the application only needs to deposit the aluminum film 150 by using a physical vapor deposition method and then oxidize the aluminum film 150 to generate the aluminum oxide barrier layer 160 capable of blocking the diffusion of metal gate metal atoms. On one hand, compared with the atomic layer deposition method, the physical vapor deposition and oxidation process is simpler, higher in production efficiency and lower in cost; on the other hand, the physical vapor deposition method can reduce the particle defects of the product and improve the reliability of the device; in addition, the thicknesses of the aluminum film 150 and the aluminum oxide barrier layer 160 can be well controlled in the physical vapor deposition process, so that the amount of metal atoms diffused into the gate dielectric layer 110 can be controlled, and thus the threshold voltage of the device can be controlled.

Referring to fig. 9, a metal gate 170 is formed on the surface of the alumina barrier layer 160, and the metal gate 170 fills the opening 121.

In some embodiments of the present application, the metal gate 170 may be a multi-layer composite structure, and the metal gate 170 may include a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer 170. The titanium aluminum layer and the titanium nitride layer can adjust the work function of the metal gate 170, the titanium metal layer is used as an adhesion layer of the aluminum metal layer and the titanium nitride layer, and the aluminum metal layer is a main structure of the gate. In some embodiments of the present application, the method of forming the titanium aluminum layer, the titanium nitride layer, the titanium metal layer, and the aluminum metal layer comprises a physical vapor deposition method.

Referring to fig. 10, an interlayer dielectric layer 180 is formed on the dielectric layer 140, the sidewall spacers 130 and the metal gate 170, and a contact structure 190 penetrating through the interlayer dielectric layer 180 and electrically connected to the metal gate 170 is formed in the interlayer dielectric layer 180.

In some embodiments of the present application, the material of the interlayer dielectric layer 180 includes silicon oxide.

In some embodiments of the present application, the material of the contact structure 190 is a metal, such as tungsten or copper or aluminum.

In some embodiments of the present application, the method of forming the interlayer dielectric layer 190 includes a chemical vapor deposition process or a physical vapor deposition process, etc.

According to the forming method of the semiconductor structure, on one hand, compared with an atomic layer deposition method, a physical vapor deposition and oxidation process is simpler, higher in production efficiency and lower in cost; on the other hand, the physical vapor deposition method can reduce the particle defects of the product and improve the reliability of the device; in addition, the thicknesses of the aluminum film 150 and the aluminum oxide barrier layer 160 can be well controlled in the physical vapor deposition process, so that the amount of metal atoms diffused into the gate dielectric layer 110 can be controlled, and thus the threshold voltage of the device can be controlled.

Embodiments of the present application also provide a semiconductor structure, referring to fig. 10, comprising: a semiconductor substrate 100; a gate dielectric layer 110 and a metal gate 170 sequentially disposed on the semiconductor substrate 100; an alumina barrier layer 160 located at the bottom and both sides of the metal gate 170; an aluminum film 150 on the bottom and sidewalls of the alumina barrier layer 160; and a sidewall spacer 130 positioned on both sides of the gate dielectric layer 110 and the aluminum film 150.

Referring to fig. 10, the material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The semiconductor substrate 100 may also be a structure grown with an epitaxial layer.

With continued reference to fig. 10, the gate dielectric layer 110 may be a composite structure formed by multiple dielectric layers, for example, including a first dielectric layer and a second dielectric layer sequentially disposed on the semiconductor substrate 100. Wherein the material of the first dielectric layer is silicon oxide, for example; the material of the second dielectric layer is hafnium oxide, for example.

In some embodiments of the present application, the material of the gate dielectric layer 110 may include silicon oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, aluminum oxide, and the like.

In some embodiments of the present application, the semiconductor structure further comprises: and the cap layer (not shown in the figure) is positioned on the surface of the gate dielectric layer 120 and comprises a titanium metal layer positioned on the surface of the gate dielectric layer and a nitrogen-rich titanium nitride layer positioned on the surface of the titanium metal layer. The double-layer structure of the titanium metal layer and the nitrogen-rich titanium nitride layer is used as the cap layer, so that the problems of high electric leakage, poor thermal stability, low breakdown voltage and the like can be avoided under the condition of not influencing the thickness of an equivalent oxide layer.

With continued reference to fig. 10, spacers 130 are formed on both sides of the gate dielectric layer 110 and the gate structure. The sidewall spacers 130 may protect the gate dielectric layer 110 and the gate structure.

In some embodiments of the present application, the material of the sidewall spacers 130 includes silicon nitride or silicon oxide.

In some embodiments of the present application, the sidewall spacer 130 may have a single-layer structure. In other embodiments of the present application, the sidewall spacer 130 may also be a multi-layer composite structure, such as a silicon oxide-silicon nitride-silicon oxide-silicon nitride structure.

With continued reference to fig. 10, a dielectric layer 140 is formed on the semiconductor substrate 100, wherein the top of the dielectric layer 140 is flush with the upper surface of the gate structure.

With continued reference to fig. 10, aluminum atoms of the aluminum film 150 may diffuse into the gate dielectric layer 110 to adjust the device threshold voltage. Compared with the conventional semiconductor structure which is difficult to control the diffusion of metal gate metal atoms, the semiconductor structure provided by the present application can control the amount of aluminum atoms diffused into the gate dielectric layer 110 by controlling the thickness of the aluminum film 150, thereby controlling the threshold voltage. Specifically, the lower the thickness of the aluminum film 150, the less aluminum atoms can diffuse into the gate dielectric layer 110, and the higher the threshold voltage; conversely, the higher the thickness of the aluminum film 150, the more aluminum atoms can diffuse into the gate dielectric layer 110, and the lower the threshold voltage. The reason for choosing to use an aluminum film includes: the work function of the metal aluminum meets the requirement of a metal gate in an NMOS device on the work function; the oxide of metallic aluminum, alumina, is readily formed; and can be used as a material for blocking the diffusion of metal atoms; the price of metallic aluminum is relatively cheap.

In some embodiments of the present application, the thickness of the aluminum film 150 is 25 to 35 angstroms, such as 25 angstroms, 30 angstroms, 35 angstroms, or the like. Since a portion of the aluminum film 150 is oxidized, the thickness of the aluminum film 150 is slightly thicker than the actual requirement, and a certain thickness is reserved for the subsequent oxidation.

With continued reference to fig. 10, an aluminum oxide barrier layer 160 is formed on the surface of the aluminum film 150. Alumina possesses very stable properties and can prevent diffusion of metal atoms in metal gates. It should be noted that the dimensional ratio in the drawings does not represent a real dimensional ratio, and is merely for the sake of brevity and convenience to describe the position relationship, shape structure, and the like between the structures in the semiconductor structure, for example, the alumina barrier layer 160 is a thin film formed by oxidizing the surface of the aluminum film 150, and the alumina barrier layer 160 is enlarged in the drawings to more clearly describe the alumina barrier layer 160.

In some embodiments of the present application, the alumina barrier layer 160 has a thickness of 5 to 25 angstroms, such as 5 angstroms, 10 angstroms, 15 angstroms, 20 angstroms, or 25 angstroms. The semiconductor structure provided by the present application can control the amount of metal atoms diffused from the metal gate into the gate dielectric layer 110 by controlling the thickness of the aluminum oxide barrier layer 160, thereby controlling the threshold voltage. Specifically, the higher the thickness of the alumina barrier layer 160, the stronger the ability to block diffusion of metal gate metal atoms; conversely, the higher the thickness of the alumina barrier layer 160, the lower the ability to block diffusion of metal gate metal atoms. In actual production, the oxidation time can be controlled according to requirements to control the thickness of the alumina barrier layer.

In the semiconductor structure provided by the present application, the thicknesses of the aluminum film 150 and the aluminum oxide barrier layer 160 can be well controlled, so as to control the amount of metal atoms diffused into the gate dielectric layer 110, and thus control the threshold voltage of the device.

With continued reference to fig. 10, a metal gate 170 is formed on the surface of the alumina barrier layer 160.

In some embodiments of the present application, the metal gate 170 may be a multi-layer composite structure, and the metal gate 170 may include a titanium aluminum layer, a titanium nitride layer, a titanium metal layer, and an aluminum metal layer sequentially on the surface of the aluminum oxide barrier layer 170. The titanium aluminum layer and the titanium nitride layer can adjust the work function of the metal gate 170, the titanium metal layer is used as an adhesion layer of the aluminum metal layer and the titanium nitride layer, and the aluminum metal layer is a main structure of the gate.

With reference to fig. 10, an interlayer dielectric layer 180 is formed on the dielectric layer 140, the sidewall spacers 130 and the metal gate 170, and a contact structure 190 penetrating through the interlayer dielectric layer 180 and electrically connected to the metal gate 170 is formed in the interlayer dielectric layer 180.

In some embodiments of the present application, the material of the interlayer dielectric layer 180 includes silicon oxide.

In some embodiments of the present application, the material of the contact structure 190 is a metal, such as tungsten or copper or aluminum.

In the semiconductor structure described herein, the thicknesses of the aluminum film 150 and the aluminum oxide barrier layer 160 can be well controlled, so as to control the amount of metal atoms diffused into the gate dielectric layer 110, and thus control the threshold voltage of the device.

In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.

It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.

Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.