阅读说明：本技术 复合衬底及其制备方法 (Composite substrate and method for manufacturing same ) 是由 徐琳 金超 赵毛毛 于 2021-07-28 设计创作，主要内容包括：本发明提供了一种复合衬底及其制备方法,包括：III-V族衬底,所述III-V族衬底具有III族极性面和V族极性面；欧姆接触层,所述欧姆接触层位于所述III-V族衬底的V族极性面上。制备方法包括：提供一III-V族衬底,所述III-V族衬底具有III族极性面和V族极性面；在所述III-V族衬底的V族极性面上形成欧姆接触层。本发明提供的另一种制备方法包括：提供一支撑衬底；在所述支撑衬底的表面形成欧姆接触层；在所述欧姆接触层表面形成III-V族衬底,所述III-V族衬底具有III族极性面和V族极性面,且所述V族极性面与所述欧姆接触层直接接触；去除所述支撑衬底。本发明通过设置欧姆接触层,提高了复合衬底的载流子浓度,降低了接触电阻,提高了欧姆接触的热稳定性以及器件的性能。(The invention provides a composite substrate and a preparation method thereof, comprising the following steps: a III-V substrate having a III-polar face and a V-polar face; an ohmic contact layer on a group V polar face of the III-V substrate. The preparation method comprises the following steps: providing a III-V substrate, wherein the III-V substrate is provided with a III-V polar plane and a V-V polar plane; and forming an ohmic contact layer on the V-group polar surface of the III-V substrate. The invention provides another preparation method which comprises the following steps: providing a support substrate; forming an ohmic contact layer on the surface of the support substrate; forming a III-V group substrate on the surface of the ohmic contact layer, wherein the III-V group substrate is provided with a III group polar surface and a V group polar surface, and the V group polar surface is in direct contact with the ohmic contact layer; and removing the supporting substrate. By arranging the ohmic contact layer, the carrier concentration of the composite substrate is improved, the contact resistance is reduced, and the thermal stability of ohmic contact and the performance of a device are improved.)

1. A composite substrate, comprising:

a III-V substrate having a III-polar face and a V-polar face;

an ohmic contact layer on a group V polar face of the III-V substrate.

2. The composite substrate of claim 1, wherein the III-V substrate is an undoped GaN material or a semi-insulating GaN material with a thickness of 1 μ ι η to 1000 μ ι η.

3. The composite substrate of claim 1, wherein the ohmic contact layer is made of a high carrier concentration GaN material and has a thickness of 10nm-1000 μm.

4. The composite substrate of claim 1, wherein the ohmic contact layer is made of high conductivity GaN single crystal material and has a thickness of 1 μm-1000 μm.

5. The composite substrate of claim 1, wherein the III-V substrate employs a low impurity concentration epitaxial layer having a thickness of 1 μm to 1000 μm and a carrier concentration of less than 1 x 10¹⁷cm^-3。

6. The composite substrate of claim 1, wherein the group III-V substrate and the ohmic contact layer are made of a binary group III-V semiconductor material, a ternary, quaternary, and multiple group III-V semiconductor material formed by a plurality of group III elements and a plurality of group V elements, or a binary, ternary, and multiple group III-V semiconductor material formed by a group III element and a group V element with different forbidden bandwidths, respectively.

7. A method of making a composite substrate, comprising:

providing a III-V substrate, wherein the III-V substrate is provided with a III-V polar plane and a V-V polar plane; and forming an ohmic contact layer on the V-group polar surface of the III-V substrate.

8. The method of claim 7, wherein the group III-V substrate is an undoped GaN material or a semi-insulating GaN material with a thickness of 1 μm to 1000 μm.

9. The method of claim 7, wherein the ohmic contact layer is made of a high carrier concentration GaN material and has a thickness of 10nm-1000 μm.

10. The method of claim 7, wherein the group III-V substrate and the ohmic contact layer are made of a binary group III-V semiconductor material, a ternary, quaternary, and multiple group III-V semiconductor material formed of a plurality of group III elements and a plurality of group V elements, or a binary, ternary, and multiple group III-V semiconductor material formed of a group III element and a group V element with different forbidden bandwidths, respectively.

11. The method of claim 7, wherein the ohmic contact layer is formed by one or more methods selected from hydride vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

12. A method of making a composite substrate, comprising:

providing a support substrate;

forming an ohmic contact layer on the surface of the support substrate;

forming a III-V group substrate on the surface of the ohmic contact layer, wherein the III-V group substrate is provided with a III group polar surface and a V group polar surface, and the V group polar surface is in direct contact with the ohmic contact layer;

and removing the supporting substrate.

13. The method of claim 12, wherein the III-V substrate is an undoped GaN material or a semi-insulating GaN material with a thickness of 1 μ ι η to 1000 μ ι η.

14. The method of claim 12, wherein the ohmic contact layer is made of a high carrier concentration GaN material and has a thickness of 10nm-1000 μm.

15. The method of claim 12, wherein the III-V substrate and the ohmic contact layer are made of a binary III-V semiconductor material, a ternary III-V semiconductor material formed by a plurality of group III elements and a plurality of group V elements, a quaternary III-V semiconductor material, a quaternary V-V semiconductor material, or a binary III-V semiconductor material formed by a group III element and a group V element with different forbidden bandwidths.

16. The method of claim 12, wherein the ohmic contact layer and the group III-V substrate are formed by one or more methods selected from hydride vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, ammonothermal methods, and Na flux methods.

17. The method of claim 12, wherein the support substrate comprises a substrate material such as a GaN single crystal substrate, a sapphire substrate, a Si substrate, a SiC substrate, or the like.

18. The method of claim 12, wherein removing the support substrate is by laser lift-off or grinding.

19. A method of making a composite substrate, comprising:

providing an ohmic contact layer, wherein the ohmic contact layer is made of III-V materials and has a III-V polar surface and a V-V polar surface;

and forming a III-V substrate on the III-V polar surface of the ohmic contact layer.

20. The method of claim 19, wherein the ohmic contact layer is formed of a high conductivity GaN single crystal material having a thickness of 1 μm to 1000 μm.

21. The method of claim 19, wherein the III-V substrate is a low impurity concentration epitaxial layer having a thickness of 1 μm to 1000 μm and a carrier concentration of less than 1 x 10¹⁷cm^-3。

22. The method of claim 19, wherein the group III-V substrate is formed by a method selected from hydride vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, ammonothermal methods, Na flux methods, or a combination thereof.

Technical Field

The invention relates to the field of semiconductors, in particular to a composite substrate and a preparation method thereof.

Background

Gallium nitride (GaN) is a direct band gap semiconductor material, and has the advantages of large forbidden band width, strong breakdown electric field, good chemical stability, etc，Is an ideal substrate material for preparing GaN-based photoelectronic and microelectronic devices. At present, GaN-based devices with Ga polarity are rapidly developed and widely applied to the fields of semiconductor illumination, laser display, power electronics and microwave radio frequency.

Ohmic contact to the N-polar face is an important issue for GaN-based devices, mainly because: (1) in recent years, GaN-based vertical structure devices have gained wide attention, because the vertical structure devices can avoid the problems of edge electric field concentration and the like faced by the conventional planar devices, and reduce the influence of surface states on the device performance, which is an important direction for the development of GaN-based devices. One electrode of the vertical structure device must be prepared on the N-polar plane of the gallium nitride single crystal substrate. (2) Compared with Ga polar GaN, N polar GaN has different polarity, surface dangling bond and surface reconstruction mode, can realize a plurality of novel device structures, and obtains the performance which Ga polar devices do not have. An N-polarity High Electron Mobility Transistor (HEMT) device can reduce a short channel effect and improve the high-frequency characteristics of the device. The doping efficiency of impurities such as In, Al and the like In the growth process of the N-polar material is higher, and the components of the GaN-based ternary and quaternary compounds are easier to regulate and control. In the solar cell, the polarized electric field in the N-polarity device can promote the separation of photo-generated electrons and holes, and the efficiency of the solar cell is improved. One electrode of the N-polar device must also be prepared on the N-polar face of the gallium nitride single crystal substrate.

However, N-polar ohmic contact has problems of high contact resistance, poor thermal stability, and the like, and generally, the N-polar ohmic contact is deteriorated or even failed by annealing at a high temperature of 300 ℃. This is mainly because Al in the electrode material easily diffuses into GaN at the interface to form AlN, and further two-dimensional hole gas is formed near the interface due to the piezoelectric polarization effect, resulting in deterioration of ohmic characteristics. The device is often subjected to high-temperature processes such as annealing, routing and the like in the preparation process, so that the problem of performance reduction and the like of the device caused by high temperature can be avoided only by improving the thermal stability of the N-polar surface ohmic contact.

Disclosure of Invention

The technical problem to be solved by the invention is to solve the problem of poor ohmic contact of an N-polar surface of a GaN-based device, improve the thermal stability of ohmic contact of the N-polar surface, reduce the contact resistance, effectively inhibit the formation of two-dimensional cavity gas on an interface, improve the reliability of the device and provide a composite substrate and a preparation method thereof.

In order to solve the above problems, the present invention provides a composite substrate comprising: a III-V substrate having a III-polar face and a V-polar face; an ohmic contact layer on a group V polar face of the III-V substrate.

In order to solve the above problems, the present invention provides a method for manufacturing a composite substrate, comprising: providing a III-V substrate, wherein the III-V substrate is provided with a III-V polar plane and a V-V polar plane; and forming an ohmic contact layer on the V-group polar surface of the III-V substrate.

The invention provides another preparation method of a composite substrate, which comprises the following steps: providing a support substrate; forming an ohmic contact layer on the surface of the support substrate; forming a III-V group substrate on the surface of the ohmic contact layer, wherein the III-V group substrate is provided with a III group polar surface and a V group polar surface, and the V group polar surface is in direct contact with the ohmic contact layer; and removing the supporting substrate.

The invention also provides another preparation method of the composite substrate, which comprises the following steps: providing an ohmic contact layer, wherein the ohmic contact layer is made of III-V materials and has a III-V polar surface and a V-V polar surface; and forming a III-V substrate on the III-V polar surface of the ohmic contact layer.

According to the invention, the ohmic contact layer is formed on the V-group polar surface of the III-V-group substrate, so that the carrier concentration of the composite substrate is improved, the contact resistance is reduced, the problem of poor ohmic contact of the N-polar surface of the GaN substrate is effectively solved, and the thermal stability of ohmic contact and the performance of a device are improved.

Drawings

FIG. 1 is a schematic diagram illustrating one embodiment of the present invention.

FIGS. 2A-2B are schematic views of the process of steps S10-S11 shown in FIG. 1.

Figure 3 is a schematic representation of one embodiment of the present invention.

FIGS. 4A-4D are schematic views of the process of steps S30-S33 shown in FIG. 3.

Figure 5 is a schematic representation of one embodiment of the present invention.

FIGS. 6A-6B are schematic views of the process of steps S50-S51 shown in FIG. 5.

Detailed Description

The following describes in detail embodiments of the composite substrate and the method for manufacturing the same according to the present invention with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention, including: step S10, providing a III-V substrate, wherein the III-V substrate is provided with a III-V polar plane and a V-V polar plane; and step S11, forming an ohmic contact layer on the V-group polar surface of the III-V substrate.

FIGS. 2A-2B are schematic views of the process of steps S10-S11 shown in FIG. 1.

Referring to step S10 of fig. 2A, a III-V substrate 201 is provided, the III-V substrate 201 having a III-polar plane and a V-polar plane. In one embodiment of the present invention, the III-V substrate 201 is made of non-doped GaN material or semi-insulating GaN material and has a thickness of 1 μm to 1000 μm.

Referring to step S11, in fig. 2B, an ohmic contact layer 202 is formed on the group V polar plane of the III-V substrate 201. In one embodiment of the present invention, the ohmic contact layer 202 is made of a high carrier concentration GaN material and has a thickness of 10nm to 1000 μm. The high carrier concentration GaN material is doped with shallow level donor impurities such as Si, Ge, O and the like, and the carrier concentration is higher than 1 multiplied by 10¹⁹cm^-3The GaN material of (1). In this embodiment, the ohmic contact layer 202 is a 1 μm GaN material layer with high carrier concentration, and the carrier concentration is higher than 1 × 10¹⁹cm^-3Formed by metal organic chemical vapor deposition. In other embodiments of the present invention, the method for forming the ohmic contact layer 202 may be selected from one or a combination of hydride vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

The III-V substrate 201 and the ohmic contact layer 202 are made of a binary III-V semiconductor material, a ternary, quaternary and multiple III-V semiconductor material formed by a plurality of III-V elements and a plurality of V-V elements, such as GaN, AlN, InN, GaAs, InP, or the like, or a binary, ternary and multiple III-V semiconductor material formed by a group III element and a group V element with different forbidden bandwidths. And the materials of the III-V substrate 201 and the ohmic contact layer 202 can adopt the same III-V compound or different III-V compounds.

After the above technical solution is completed, the composite substrate shown in fig. 2B is obtained, which includes: a III-V substrate 201, the III-V substrate 201 having a III-polar plane and a V-polar plane; an ohmic contact layer 202, the ohmic contact layer 202 being located on a group V polar plane of the III-V substrate 201. In one embodiment of the present invention, the III-V substrate 201 is made of non-doped GaN material or semi-insulating GaN material and has a thickness of 1 μm to 1000 μm. The ohmic contact layer 202 is made of a GaN material with high carrier concentration and has a thickness of 10nm-1000 μm. The high carrier concentration GaN material is doped with shallow level donor impurities such as Si, Ge, O and the like, and the carrier concentration is higher than 1 multiplied by 10¹⁹cm^-3The GaN material of (1). When the annealing temperature does not exceed the critical temperature, the contact resistance becomes lower as the carrier concentration becomes higher at the same annealing temperature. Because the carrier concentration in the ohmic contact layer 202 is high, a large number of electrons neutralize the two-dimensional hole gas near the interface, the contact resistance of the ohmic contact is reduced, and the thermal stability of the ohmic contact is improved.

The III-V substrate 201 and the ohmic contact layer 202 are made of a binary III-V semiconductor material, a ternary, quaternary and multiple III-V semiconductor material formed by a plurality of III-V elements and a plurality of V-V elements, such as GaN, AlN, InN, GaAs, InP, or the like, or a binary, ternary and multiple III-V semiconductor material formed by a group III element and a group V element with different forbidden bandwidths. And the materials of the III-V substrate 201 and the ohmic contact layer 202 can adopt the same III-V compound or different III-V compounds.

The semiconductor material with larger forbidden band width has the characteristics of high breakdown electric field intensity, high saturated electron drift velocity, large thermal conductivity, small dielectric constant, good chemical stability and the like due to larger transition energy, is suitable for manufacturing high-frequency, high-power and high-density integrated electronic devices, and has good high-temperature and high-pressure resistance and radiation resistance. The heterojunction and the two-dimensional electron gas with high mobility in the heterojunction are adopted for working, so that the device and the integrated circuit thereof can work in the fields of ultrahigh frequency (millimeter wave) and ultrahigh speed.

FIG. 3 is a schematic diagram of another embodiment of the present invention, including: step S30, providing a supporting substrate; step S31, forming an ohmic contact layer on the surface of the supporting substrate; step S32, forming a III-V group substrate on the surface of the ohmic contact layer, wherein the III-V group substrate is provided with a III group polar surface and a V group polar surface, and the V group polar surface is in direct contact with the ohmic contact layer; step S33, removing the support substrate.

FIGS. 4A-4D are schematic views of the process of steps S30-S33 shown in FIG. 3.

Referring to step S30 of fig. 4A, a support substrate 40 is provided. In one embodiment of the present invention, the support substrate includes a substrate material such as a GaN single crystal substrate, a sapphire substrate, a Si substrate, or a SiC substrate.

Referring to step S31 in fig. 4B, an ohmic contact layer 402 is formed on the surface of the supporting substrate 40. In one embodiment of the present invention, the ohmic contact layer 402 is made of GaN material with high carrier concentration and has a thickness of 10nm-1000 μm. The high carrier concentration GaN material is doped with shallow level donor impurities such as Si, Ge, O and the like, and the carrier concentration is higher than 1 multiplied by 10¹⁹cm^-3The GaN material of (1). In this embodimentIn one embodiment, the ohmic contact layer 402 is a 10 μm GaN material layer with high carrier concentration, and the carrier concentration is higher than 1 × 10¹⁹cm^-3And the film is formed by a hydride vapor phase epitaxy method. In other embodiments of the present invention, the method for forming the ohmic contact layer 402 may be selected from one or a combination of hydride vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, and Na flux method.

Referring to step S32 in fig. 4C, a III-V substrate 401 is formed on the surface of the ohmic contact layer 402, the III-V substrate 401 has a III-group polarity plane and a V-group polarity plane, and the V-group polarity plane is in direct contact with the ohmic contact layer 402. In one embodiment of the present invention, the III-V substrate 401 is made of non-doped GaN material and has a thickness of 1 μm to 1000 μm. In this embodiment, the III-V substrate 401 is a 300 μm layer of undoped GaN material formed by hydride vapor phase epitaxy. In other embodiments of the present invention, the method for forming the III-V substrate 401 is selected from one or more of hydride vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method, Na flux method.

Referring to step S33, fig. 4D, the support substrate 40 is removed. In one embodiment of the present invention, the support substrate is removed by laser lift-off or grinding.

After the above technical solution is completed, the composite substrate shown in fig. 4D is obtained, which includes: a III-V substrate 401, the III-V substrate 401 having a group III polar face and a group V polar face; an ohmic contact layer 402, the ohmic contact layer 402 being located on a group V polar face of the III-V substrate 401. In one embodiment of the present invention, the III-V substrate 401 is made of non-doped GaN material or semi-insulating GaN material and has a thickness of 1 μm to 1000 μm. The ohmic contact layer 402 is made of a GaN material with high carrier concentration and has a thickness of 10nm-1000 μm. The high carrier concentration GaN material is doped with shallow level donor impurities such as Si, Ge, O and the like, and the carrier concentration is higher than 1 multiplied by 10¹⁹cm^-3The GaN material of (1). When the annealing temperature is not higher thanAt the over-critical temperature, the higher the carrier concentration, the lower the contact resistance at the same annealing temperature. Because the carrier concentration in the ohmic contact layer 402 is high, a large number of electrons neutralize the two-dimensional hole gas near the interface, the contact resistance of the ohmic contact is reduced, and the thermal stability of the ohmic contact is improved.

The materials of the III-V substrate 401 and the ohmic contact layer 402 are binary III-V semiconductor material, ternary, quaternary and multi-element III-V semiconductor material formed by a plurality of III-V elements and a plurality of V-V elements, such as GaN, AlN, InN, GaAs, InP, or the like, or binary, ternary and multi-element III-V semiconductor material formed by III-V elements and V-V elements with different forbidden bandwidths. And the materials of the III-V substrate 401 and the ohmic contact layer 402 can adopt the same III-V compound or different III-V compounds.

FIG. 5 is a schematic diagram of another embodiment of the present invention, including: step S50, providing an ohmic contact layer, wherein the ohmic contact layer is made of III-V material and has a III-V polar surface and a V-V polar surface; and step S51, forming a III-V substrate on the III-V polar surface of the ohmic contact layer.

FIGS. 6A-6B are schematic views of the process of steps S50-S51 shown in FIG. 5.

Referring to step S50 in fig. 6A, an ohmic contact layer 602 is provided, where the ohmic contact layer 602 is made of III-V material and has a III-polar plane and a V-polar plane. In one embodiment of the present invention, the ohmic contact layer 602 is made of high conductivity GaN single crystal material and has a thickness of 1 μm to 1000 μm. In the present embodiment, the ohmic contact layer 602 has a carrier concentration higher than 1 × 10¹⁸cm^-3The conductivity of the high-conductivity GaN single crystal material is higher than 5 x 10³S/m。

Referring to step S51, in fig. 6B, a III-V substrate 601 is formed on the III-polar plane of the ohmic contact layer 602. I.e., the ohmic contact layer 602 is located on the group V polar plane of the III-V substrate 601. In one embodiment of the present invention, the III-V substrate 601 is a low impurity concentration epitaxial layer with a thickness of 1 μm-1000 μm and a carrier concentrationLess than 1X 10¹⁷cm^-3. In this embodiment mode, a low impurity concentration GaN material is used for the low impurity concentration epitaxial layer. The method for forming the III-V substrate 601 is selected from one or a combination of hydride vapor phase epitaxy, metal organic chemical vapor deposition, molecular beam epitaxy, ammonothermal method and Na fluxing agent method.

After the above technical solution is completed, the composite substrate shown in fig. 6B is obtained, which includes: a III-V substrate 601, the III-V substrate 601 having a group III polar plane and a group V polar plane; an ohmic contact layer 602, the ohmic contact layer 602 being located on a group V polar plane of the III-V substrate 601. In one embodiment of the present invention, the ohmic contact layer 602 is made of III-V material and has III-V polar plane and V-V polar plane. In one embodiment of the present invention, the ohmic contact layer 602 is made of high conductivity GaN single crystal material and has a thickness of 1 μm to 1000 μm. In the present embodiment, the ohmic contact layer 602 has a carrier concentration higher than 1 × 10¹⁸cm^-3The conductivity of the high-conductivity GaN single crystal material is higher than 5 x 10³And (5) S/m. The III-V group substrate 601 adopts a low impurity concentration epitaxial layer with the thickness of 1-1000 μm and the carrier concentration lower than 1 x 10¹⁷cm^-3. In this embodiment mode, a low impurity concentration GaN material is used for the low impurity concentration epitaxial layer. When the annealing temperature does not exceed the critical temperature, the contact resistance becomes lower as the carrier concentration becomes higher at the same annealing temperature. Due to the fact that the carrier concentration in the ohmic contact layer 602 is high, a large number of electrons can neutralize two-dimensional hole gas near an interface, contact resistance of ohmic contact is reduced, and thermal stability of the ohmic contact is improved.

According to the technical scheme, the ohmic contact layer is formed on the V-group polar surface of the III-V-group substrate, so that the carrier concentration of the composite substrate is improved, the contact resistance is reduced, the problem of poor ohmic contact of the N-polar surface of the GaN substrate is effectively solved, and the thermal stability of ohmic contact and the performance of a device are improved.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.