阅读说明：本技术 由共栅互补场效应晶体管构建的d锁存器 (D latch constructed by common gate complementary field effect transistor ) 是由 丁荣正 俞少峰 朱小娜 于 2021-08-31 设计创作，主要内容包括：本发明提供了一种由共栅互补场效应晶体管构建的D锁存器,包括第一互补场效应晶体管、第二互补场效应晶体管、第三互补场效应晶体管、第四互补场效应晶体管以及第五互补场效应晶体管,增加了D锁存器的电路集成度。(The invention provides a D latch constructed by common-gate complementary field effect transistors, which comprises a first complementary field effect transistor, a second complementary field effect transistor, a third complementary field effect transistor, a fourth complementary field effect transistor and a fifth complementary field effect transistor, and the circuit integration level of the D latch is increased.)

1. A D-latch constructed from common-gate complementary field effect transistors, comprising:

the CG terminal of the first complementary field effect transistor is used for receiving external input data, the PS terminal of the first complementary field effect transistor is connected with a high potential, and the NS terminal of the first complementary field effect transistor is connected with a low potential;

a CG terminal of the second complementary field effect transistor is configured to receive a timing-controlled low-potential signal cn or a timing-controlled high-potential signal c, and an NS terminal of the second complementary field effect transistor is connected to an ND terminal of the first complementary field effect transistor;

a CG terminal of the third complementary field effect transistor is configured to receive a high potential signal c or a low potential signal cn controlled by a timing sequence, a PS terminal of the third complementary field effect transistor is connected to the PD terminal of the first complementary field effect transistor, and both the PD terminal and the ND terminal of the third complementary field effect transistor are connected to the PD terminal and the ND terminal of the second complementary field effect transistor;

a fourth complementary field effect transistor, a PS terminal of the fourth complementary field effect transistor being connected to a high potential, a PD terminal of the fourth complementary field effect transistor being connected to a PS terminal of the second complementary field effect transistor, an ND terminal of the fourth complementary field effect transistor being connected to an NS terminal of the third complementary field effect transistor, and the NS terminal of the fourth complementary field effect transistor being connected to a low potential; and

a CG terminal of the fifth complementary field effect transistor is connected with an ND terminal of the third complementary field effect transistor, a PD terminal and an ND terminal of the fifth complementary field effect transistor are both connected with a CG terminal of the fourth complementary field effect transistor, a PS terminal of the fifth complementary field effect transistor is connected with a high potential, and an NS terminal of the fifth complementary field effect transistor is connected with a low potential.

2. The D-latch defined by claim 1 wherein the first complementary field effect transistor is identical in structure to the second complementary field effect transistor, the third complementary field effect transistor, the fourth complementary field effect transistor and the fifth complementary field effect transistor.

3. The D latch constructed by the common-gate complementary field effect transistor according to claim 2, wherein the first complementary FET is a five-port device, and five ports of the first complementary FET are the CG terminal, the PS terminal, the PD terminal, the ND terminal and the NS terminal respectively, the first complementary field effect transistor is internally integrated with a PFET tube and an NFET tube, the grid electrode of the PFET tube and the grid electrode of the NFET tube are connected together to form the CG end of the first complementary field effect transistor, the source of the PFET tube is the PS terminal of the first complementary field effect transistor, the drain of the PFET tube is the PD terminal of the first complementary field effect transistor, the drain electrode of the NFET tube is the ND end of the first complementary field effect transistor, and the source electrode of the NFET tube is the NS end of the first complementary field effect transistor.

Technical Field

The invention relates to the technical field of latches, in particular to a D latch constructed by common-gate complementary field effect transistors.

Background

Complementary field-Effect-transistors (CFETs) are three-dimensional electronic devices formed by vertically stacking field-Effect transistors (FETs) of complementary polarity. One CFET device is provided with an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) in the longitudinal direction, and the CFET is used for building a circuit, so that the circuit integration level can be greatly increased, and the possibility is provided for realizing further miniaturization of an integrated circuit.

A D latch (datalatcherdelaylatch) is a memory cell circuit that is sensitive to pulse circuits, and can change storage state under a certain input pulse level. D latches are widely used in integrated circuits, are often used as storage elements of sequential circuits in digital circuits, and are important components of various D flip-flops, and some arithmetic circuits sometimes use latches as data registers.

The gate metal of the CFET internal FET is vertically stacked, so that the NFET and the PFET can share the same gate metal easily, and the NFET and the PFET are controlled by one gate simultaneously to form a common gate structure. In the vertical direction, the gate metals of the NFET and the PFET are physically separated, which is difficult in process and design, so that the CFET structure is preferably a common gate structure. However, due to the nature of the timing circuit, the gates of a set of NFETs and PFETs must be tied to opposite timing control signals, which results in the set of NFETs and PFETs not forming a common gate.

Therefore, there is a need to provide a new type of D latch constructed by common gate complementary field effect transistors to solve the above-mentioned problems in the prior art.

Disclosure of Invention

The invention aims to provide a D latch constructed by common-gate complementary field effect transistors, which increases the circuit integration level of the D latch.

In order to achieve the above object, the D latch constructed by common-gate complementary field effect transistors according to the present invention includes:

the CG terminal of the first complementary field effect transistor is used for receiving external input data, the PS terminal of the first complementary field effect transistor is connected with a high potential, and the NS terminal of the first complementary field effect transistor is connected with a low potential;

a CG terminal of the second complementary field effect transistor is configured to receive a timing-controlled low-potential signal cn or a timing-controlled high-potential signal c, and an NS terminal of the second complementary field effect transistor is connected to an ND terminal of the first complementary field effect transistor;

a CG terminal of the third complementary field effect transistor is configured to receive a high potential signal c or a low potential signal cn controlled by a timing sequence, a PS terminal of the third complementary field effect transistor is connected to the PD terminal of the first complementary field effect transistor, and both the PD terminal and the ND terminal of the third complementary field effect transistor are connected to the PD terminal and the ND terminal of the second complementary field effect transistor;

a fourth complementary field effect transistor, a PS terminal of the fourth complementary field effect transistor being connected to a high potential, a PD terminal of the fourth complementary field effect transistor being connected to a PS terminal of the second complementary field effect transistor, an ND terminal of the fourth complementary field effect transistor being connected to an NS terminal of the third complementary field effect transistor, and the NS terminal of the fourth complementary field effect transistor being connected to a low potential; and

a CG terminal of the fifth complementary field effect transistor is connected with an ND terminal of the third complementary field effect transistor, a PD terminal and an ND terminal of the fifth complementary field effect transistor are both connected with a CG terminal of the fourth complementary field effect transistor, a PS terminal of the fifth complementary field effect transistor is connected with a high potential, and an NS terminal of the fifth complementary field effect transistor is connected with a low potential.

The invention has the beneficial effects that: the D latch constructed by the common-gate complementary field effect transistors comprises a first complementary field effect transistor, a second complementary field effect transistor, a third complementary field effect transistor, a fourth complementary field effect transistor and a fifth complementary field effect transistor, and the circuit integration level of the D latch is increased.

Preferably, the first complementary field effect transistor and the second complementary field effect transistor, the third complementary field effect transistor, the fourth complementary field effect transistor, and the fifth complementary field effect transistor are all identical in structure.

Further preferably, the first complementary field effect transistor is a five-port device, the five ports of the first complementary field effect transistor are the CG terminal, the PS terminal, the PD terminal, the ND terminal and the NS terminal, respectively, a PFET tube and an NFET tube are integrated in the first complementary field effect transistor, a gate of the PFET tube and a gate of the NFET tube are connected together to form the CG terminal of the first complementary field effect transistor, a source of the PFET tube is the PS terminal of the first complementary field effect transistor, a drain of the PFET tube is the PD terminal of the first complementary field effect transistor, a drain of the NFET tube is the ND terminal of the first complementary field effect transistor, and a source of the NFET tube is the NS terminal of the first complementary field effect transistor.

Drawings

FIG. 1 is a circuit diagram of a D latch constructed from common gate complementary field effect transistors according to the present invention;

FIG. 2 is an equivalent circuit diagram of a first complementary field effect transistor;

FIG. 3 is a circuit diagram of a first D latch of the prior art;

FIG. 4 is a CMOS transistor circuit diagram of the first D-latch of FIG. 3;

fig. 5 is a circuit diagram of the equivalent CMOS transistor of fig. 1.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.

To solve the problems in the prior art, embodiments of the present invention provide a D latch constructed by common-gate complementary field effect transistors. Referring to fig. 1, the D latch 100 constructed by the common gate complementary field effect transistor includes:

a first complementary field effect transistor 101, a CG terminal of the first complementary field effect transistor 101 is used for receiving data, a PS terminal of the first complementary field effect transistor 101 is connected with a high potential, and an NS terminal of the first complementary field effect transistor 101 is connected with a low potential;

a second complementary field effect transistor 102, a CG terminal of the second complementary field effect transistor 102 being configured to receive a timing-controlled low-potential signal cn or a timing-controlled high-potential signal c, an NS terminal of the second complementary field effect transistor 102 being connected to an ND terminal of the first complementary field effect transistor 101;

a third complementary field effect transistor 103, a CG terminal of the third complementary field effect transistor 103 is configured to receive a timing-controlled high-potential signal c or a timing-controlled low-potential signal cn, a PS terminal of the third complementary field effect transistor 103 is connected to the PD terminal of the first complementary field effect transistor 101, and a PD terminal and an ND terminal of the third complementary field effect transistor 103 are both connected to the PD terminal and the ND terminal of the second complementary field effect transistor 102;

a fourth complementary fet 104, a PS terminal of the fourth complementary fet 104 being connected to a high voltage, a PD terminal of the fourth complementary fet 104 being connected to the PS terminal of the second complementary fet 102, an ND terminal of the fourth complementary fet 104 being connected to the NS terminal of the third complementary fet 103, and an NS terminal of the fourth complementary fet 104 being connected to a low voltage; and

a fifth complementary fet 105, a CG terminal of the fifth complementary fet 105 is connected to the ND terminal of the third complementary fet 103, a PD terminal and an ND terminal of the fifth complementary fet 105 are both connected to the CG terminal of the fourth complementary fet 104, a PS terminal of the fifth complementary fet 105 is connected to a high potential, and an NS terminal of the fifth complementary fet 105 is connected to a low potential.

In some embodiments, when the CG of the second complementary field effect transistor 102 receives the low-potential signal cn for timing control, the CG of the third complementary field effect transistor 103 receives the high-potential signal c for timing control; when the CG of the second complementary fet 102 receives the timing-controlled high-potential signal c, the CG of the third complementary fet 103 receives the timing-controlled low-potential signal cn.

Referring to fig. 1, a CG terminal of the first complementary fet 101 is an external data input terminal of the D-latch 100 constructed by the common-gate complementary fets, an ND terminal of the third complementary fet 103 is connected to one terminal of a first transmission line 1031, a PD terminal of the third complementary fet 103 is connected to one terminal of a second transmission line 1032, the other terminal of the second transmission line 1032 is connected to the first transmission line 1031 at a first sub-node 1033, a CG terminal of the fifth complementary fet 105 is connected to one terminal of a third transmission line 1051, the other terminal of the third transmission line 1051 is connected to the first transmission line 1031 at a second sub-node 1034, the second sub-node 1034 is located between the first sub-node 1033 and the ND terminal of the third complementary fet 103, a third sub-node 1035 is provided on the third transmission line 1051, the third sub-node 1035 is the QN output of the D latch 100 constructed from common gate complementary field effect transistors. Specifically, the first transmission line 1031 and the second transmission line 1032 may be different transmission lines or the same transmission line, and the first sub-node 1033 and the second sub-node 1034 may be different nodes or the same node, and only the PD terminal and the ND terminal of the second complementary fet 102 need to be connected to the PD terminal and the ND terminal of the third complementary fet 103, and the other end of the third transmission line 1051 needs to be connected to the PD terminal and the ND terminal of the second complementary fet 102, the PD terminal and the ND terminal of the third complementary fet 103.

Referring to fig. 1, the ND terminal of the fifth complementary fet 105 is connected to one terminal of a fourth transmission line 1052, the PD terminal of the fifth complementary fet 105 is connected to one terminal of a fifth transmission line 1053, the CG terminal of the fourth complementary fet 104 is connected to one terminal of a sixth transmission line 1054, the other terminal of the fifth transmission line 1053 and the sixth transmission line 1054 are connected to a fourth sub-node 10531, the other terminal of the sixth transmission line 1054 and the fourth transmission line 1052 are connected to a fifth sub-node 10532, and the other terminal of the fourth transmission line 1052 serves as the Q output terminal of the D latch 100 constructed by the common gate complementary fets.

Specifically, the first complementary field Effect Transistor, the second complementary field Effect Transistor, the third complementary field Effect Transistor, the fourth complementary field Effect Transistor and the fifth complementary field Effect Transistor have the same structure, and are Complementary Field Effect Transistors (CFET).

Referring to fig. 2, a PFET 1011 and an NFET 1012 are integrated in the first complementary fet, a gate of the PFET 1011 and a gate of the NFET 1012 are connected to form a CG (common gate) terminal of the first complementary fet, a source of the PFET 1011 is a PS (PFETSource) terminal of the first complementary fet, a drain of the PFET 1011 is a PD (PFETDrain) terminal of the first complementary fet, a drain of the NFET 1012 is an ND (NFETDrain) terminal of the first complementary fet, and a source of the NFET 1012 is an NS (NFETSource) terminal of the first complementary fet, wherein the CG terminal of the first complementary fet is a common gate terminal of the PFET 1011 and the NFET 1012.

Fig. 3 is a circuit diagram of a first D latch in the prior art. Referring to fig. 3, the first D-latch 200 comprises a first tri-state inverter 201, an inverter 202 and a second tri-state inverter 203, a first input terminal of the first tri-state inverter 201 is used as a D-input terminal of the first D-latch for receiving data, a second input terminal of the first tri-state inverter 201 is used for receiving a low-potential signal cn, a third input terminal of the first tri-state inverter 201 is used for receiving a high-potential signal c, an output terminal of the first tri-state inverter 201 is connected with the first input terminal of the inverter 202 through a first line 204, an output terminal of the inverter 202 is connected with one end of a second line 205, the other end of the second line 205 is used as a Q-output terminal of the first D-latch, a first node 2051 is arranged on the second line 205, the first node 2051 is connected with the first input terminal of the second tri-state inverter 203 through a third line 206, the second input end of the second tri-state inverter 203 is configured to receive a high-potential signal c, the third input end of the second tri-state inverter 203 is configured to receive a low-potential signal cn, the output end of the second tri-state inverter 203 is connected to one end of a fourth line 207, the other end of the fourth line 207 is used as the QN output end of the first D latch, the fourth line 207 is provided with a second node 2071, the first line 204 is provided with a third node 2041, and the second node 2071 and the third node 2041 are connected by a fifth line 208.

In some embodiments, referring to fig. 3, the second input terminal of the first tri-state inverter 201 receives a low-potential signal cn, the third input terminal of the first tri-state inverter 201 receives a high-potential signal c, the second input terminal of the second tri-state inverter 203 receives a high-potential signal c, the third input terminal of the second tri-state inverter 203 receives a low-potential signal cn, or the second input terminal of the first tri-state inverter 201 receives a high-potential signal c, the third input terminal of the first tri-state inverter 201 receives a low-potential signal cn, the second input terminal of the second tri-state inverter 203 receives a low-potential signal cn, the third input terminal of the second tri-state inverter 203 receives a high-potential signal c, when the first input terminal of the first tri-state inverter does not receive data, the Q output terminal and the QN output terminal of the first D latch are unchanged, the stored data content of the D-latch remains unchanged.

In some embodiments, referring to fig. 3, the second input terminal of the first tri-state inverter 201 receives a low-potential signal cn, the third input terminal of the first tri-state inverter 201 receives a high-potential signal c, the second input terminal of the second tri-state inverter 203 receives a high-potential signal c, the third input terminal of the second tri-state inverter 203 receives a low-potential signal cn, when the first input terminal of the first tri-state inverter receives a low-potential signal, the Q output terminal of the first D latch outputs a low-potential signal, the QN output terminal of the first D latch outputs a high-potential signal, and the first D latch functions as a low-potential.

In some embodiments, referring to fig. 3, the second input terminal of the first tri-state inverter 201 receives a low-potential signal cn, the third input terminal of the first tri-state inverter 201 receives a high-potential signal c, the second input terminal of the second tri-state inverter 203 receives a high-potential signal c, the third input terminal of the second tri-state inverter 203 receives a low-potential signal cn, when the first input terminal of the first tri-state inverter receives a high-potential signal, the Q output terminal of the first D latch outputs a high-potential signal, the QN output terminal of the first D latch outputs a low-potential signal, and the first D latch functions as a high-potential.

In some embodiments, the second D-latch comprises a first tri-state inverter, an inverter and a second tri-state inverter, a first input terminal of the first tri-state inverter is used as the D-input terminal of the first D-latch for receiving data, a second input terminal of the first tri-state inverter is used for receiving a high potential signal c, a third input terminal of the first tri-state inverter is used for receiving a low potential signal cn, an output terminal of the first tri-state inverter is connected with the first input terminal of the inverter through a first line, an output terminal of the inverter is connected with one end of a second line, the other end of the second line is used as the Q-output terminal of the first D-latch, a first node is arranged on the second line, the first node is connected with the first input terminal of the second tri-state inverter through a third line, and a second input terminal of the second tri-state inverter is used for receiving a low potential signal cn, the third input end of the second tri-state inverter is used for receiving a high-potential signal c, the output end of the second tri-state inverter is connected with one end of a fourth line, the other end of the fourth line is used as the QN output end of the first D latch, a second node is arranged on the fourth line, a third node is arranged on the first line, and the second node and the third node are connected through a fifth line.

In some embodiments, the second input terminal of the first tri-state inverter receives a high-potential signal c, the third input terminal of the first tri-state inverter receives a low-potential signal cn, the second input terminal of the second tri-state inverter receives a low-potential signal cn, the third input terminal of the second tri-state inverter receives a high-potential signal c, when the first input terminal of the first tri-state inverter receives a low-potential signal, the Q output terminal of the first D latch outputs a low-potential signal, the QN output terminal of the first D latch outputs a high-potential signal, and the first D latch functions as a low-potential setting.

In some embodiments, the second input terminal of the first tri-state inverter receives a high-potential signal c, the third input terminal of the first tri-state inverter receives a low-potential signal cn, the second input terminal of the second tri-state inverter receives a low-potential signal cn, the third input terminal of the second tri-state inverter receives a high-potential signal c, when the first input terminal of the first tri-state inverter receives a high-potential signal, the Q output terminal of the first D latch outputs a high-potential signal, the QN output terminal of the first D latch outputs a low-potential signal, and the first D latch functions as a high-potential.

Fig. 4 is a circuit diagram of a CMOS transistor of the first D latch of fig. 3. Referring to fig. 4, the CMOS transistor circuit of the first D-latch 200 includes a first tri-state inverter 201, an inverter 202, and a second tri-state inverter 203.

Referring to fig. 3, the first inverter 201 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2, wherein a source of the first PMOS transistor P1 is connected to a high potential VDD, a gate of the first PMOS transistor P1 and a gate of the first NMOS transistor N1 are connected together to serve as a D input terminal, a drain of the first PMOS transistor P1 is connected to a source of the second PMOS transistor P2, a gate of the second PMOS transistor P2 is used to receive a low potential signal cn or a high potential signal c, a drain of the second PMOS transistor P2 is connected to a source of the second NMOS transistor N2 through a first connection line, a gate of the second NMOS transistor N2 is used to receive a high potential signal c or a low potential signal cn, a drain of the second NMOS transistor N2 is connected to a source of the first NMOS transistor N1, and a drain of the first NMOS transistor N1 is connected to a low potential VSS.

Referring to fig. 4, the third inverter 203 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, and a fourth NMOS transistor N4, a source of the third PMOS transistor P3 is connected to a high potential VDD, a drain of the third PMOS transistor P3 is connected to a source of the fourth PMOS transistor P4, a gate of the fourth PMOS transistor P4 is configured to receive a high potential signal c or a low potential signal cn, a drain of the fourth PMOS transistor P4 is connected to a source of the fourth NMOS transistor N4 through a second connection line, a first node on the first connection line and a second node on the second connection line are connected through a third connection line, a gate of the fourth NMOS transistor N4 is configured to receive a low potential signal cn or a high potential signal c, a drain of the fourth NMOS transistor N4 is connected to the source of the third NMOS transistor N3, and a drain of the third NMOS transistor N3 is connected to a ground voltage VSS.

Referring to fig. 4, the second inverter 202 includes a fifth PMOS transistor P5 and a fifth NMOS transistor N5, a source of the fifth PMOS transistor P5 is connected to a high potential VDD, the fifth PMOS transistor P5 is connected to a source of the fifth NMOS transistor N5 through a fourth connection line, a third node is disposed on the fourth connection line, the third node is connected to one end of the fifth connection line, the other end of the fifth connection line is a Q output end, a fourth node is disposed on the fifth connection line, the fourth node is connected to a gate of the third PMOS transistor P3 and a gate of the third NMOS transistor N3, a fifth node is disposed on the third connection line, a gate of the fifth PMOS transistor P5 and a gate of the fifth NMOS transistor N5 are connected to the fifth node, and the fifth node is used as a QN output end.

Fig. 5 is an equivalent CMOS circuit diagram of fig. 1. Comparing fig. 5 with fig. 4, it can be seen that the D latch is implemented by the common gate CFET in the present application, and the problem that the PMOS transistor and the NMOS transistor in fig. 4 do not share a gate is solved.

Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.