阅读说明：本技术 开关泄漏补偿电路 (Switch leakage compensation circuit ) 是由 R·弗朗西斯 C·埃德曼 于 2020-03-26 设计创作，主要内容包括：与开关泄漏补偿延迟电路(405a)相关的装置和相关方法包括补偿晶体管(T-(0)),该补偿晶体管(T-(0))被配置为被动地绕过与控制晶体管(M-(0))串联连接的电容器(C-(0))周围的泄漏电流。在说明性示例中,电容器(C-(0))和补偿晶体管(T-(0))可以并联连接在第一节点(a-(0))和第二节点(b-(0))之间。补偿晶体管(T-(0))的栅极可以例如直接连接到其源极和第二节点(b-(0))。控制晶体管(M-(0))可以将其漏极连接到第二节点(b-(0))。当控制信号关断控制晶体管(M-(0))时,控制晶体管(M-(0))的漏电流可以由补偿晶体管(T-(0))的漏电流提供,使得跨过电容器(C-(0))两端的电压可以保持不变基本恒定。延迟电路(405a)可以有利地减轻电容器(C-(0))的电压下降以减小时钟时间偏差,例如,在低速交错ADC操作中的时钟时间偏差。(Apparatus and associated methods associated with a switching leakage compensated delay circuit (405a) include a compensation transistor (T) 0 ) The compensation transistor (T) 0 ) Configured to passively bypass and control the transistor (M) 0 ) Capacitors (C) connected in series 0 ) Ambient leakage current. In the illustrative example, a capacitor (C) 0 ) And a compensation transistor (T) 0 ) May be connected in parallel at the first node (a) 0 ) And a second node (b) 0 ) In the meantime. Compensation transistor (T) 0 ) May for example be directly connected to its source and second node (b) 0 ). Control transistor(M 0 ) May have its drain connected to the second node (b) 0 ). When the control signal turns off the control transistor (M) 0 ) While controlling the transistor (M) 0 ) Can be compensated by a compensation transistor (T) 0 ) So as to cross the capacitor (C) 0 ) The voltage across the terminals may remain constant and substantially constant. The delay circuit (405a) may advantageously mitigate the capacitor (C) 0 ) To reduce clock skew, e.g., in low speed interleaved ADC operation.)

1. A delay circuit, characterized in that the delay circuit comprises:

a capacitor coupled between a first node and a second node;

a first transistor having a first drain connected to the second node, a first source connected to a reference node, and a first gate coupled to a first gate control signal, wherein the first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal; and

a second transistor having a second drain and a second source, the second transistor coupled in parallel with the capacitor, the second transistor further comprising a second gate coupled to apply a voltage to the second gate that is less than a second threshold voltage of the second transistor;

wherein in a first mode, when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the first transistor, a voltage across the capacitor is substantially constant.

2. Delay circuit according to claim 1, characterized in that in said first mode said first transistor provides a first leakage current I_leak1The first leakage current I_leak1And a second leakage current I provided by the second transistor_leak2Substantially matching.

3. The delay circuit of claim 1, wherein the second drain is connected to the first node, and the second source is connected to the second gate and the second node.

4. The delay circuit of claim 1, wherein the potential of the reference node comprises a circuit ground potential.

5. The delay circuit of claim 1, wherein the second gate is connected to the second node.

6. The delay circuit of claim 1, wherein the second transistor is on a same die and has substantially the same size as the first transistor.

7. The delay circuit of claim 1, wherein said first transistor comprises an n-channel metal-oxide-semiconductor field effect transistor (NMOSFET).

8. The delay circuit of claim 1, wherein said first transistor comprises a p-channel metal oxide semiconductor field effect transistor (PMOSFET).

9. The delay circuit of claim 1, wherein the first transistor comprises a transmission gate.

10. The delay circuit of claim 1, wherein the capacitor comprises a metal oxide semiconductor transistor.

11. A system, characterized in that the system comprises:

a buffer output coupled to drive a first node that provides a predetermined delay on an input clock signal; and

at least one delay circuit configured to obtain the predetermined delay, each of the at least one delay circuit comprising:

a capacitor coupled between the first node and a corresponding second node;

a first transistor having a first drain connected to a respective one of the second nodes, a first source connected to a reference node, and a first gate coupled to a corresponding first gate control signal, wherein the first transistor modulates connectivity between the corresponding first drain and the corresponding first source in response to the corresponding first gate control signal; and

a second transistor having a second drain and a second source, the second transistor coupled in parallel with a corresponding capacitor, the second transistor further having a corresponding second gate coupled to apply a voltage to the second gate that is less than a second threshold voltage of the second transistor;

wherein in a first mode, when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the corresponding first transistor, a voltage across the corresponding capacitor is substantially constant.

12. The system of claim 11, wherein in the first mode, for each of the at least one delay circuit, each of the first transistors provides a corresponding first leakage current I_leak1The corresponding first leakage current I_leak1Corresponding second leakage current I provided by corresponding second transistor_leak2Substantially matching.

13. A method, characterized in that the method comprises:

providing a capacitor coupled between a first node and a second node;

providing a first transistor having a first drain connected to the second node, a first source connected to a reference node, and a first gate coupled to a first gate control signal, wherein the first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal;

providing a second transistor having a second drain and a second source, the second transistor coupled in parallel with the capacitor, and the second transistor having a second gate coupled to apply a voltage to the second gate that is less than a second threshold voltage of the second transistor; and

in a first mode, when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the first transistorProviding a first leakage current I substantially drawn by the first transistor using said second transistor_leak1So that the voltage across the capacitor remains substantially constant.

14. The method of claim 13, wherein in the first mode, the second transistor substantially matches the first leakage current I_leak1。

15. The method of claim 13, wherein the second drain is connected to the first node, and the second source is connected to the second gate and the second node.

Technical Field

Various embodiments are generally directed to switch leakage compensation.

Technical Field

Data represents information of useful value. The data may be in the form of stored information. The data store may be in analog form. The data store may also be in digital form.

Data in digital format may be communicated between two nodes. At a receiver in a digital communication system, a digitally encoded data stream may be received as an analog signal and converted to a digital format by an analog-to-digital converter (ADC). The analog-to-digital converter interprets the data stream as a function of time. For example, some ADCs may be synchronized with a clock signal that determines when to sample the voltage signal. For example, accurate recovery of a digital data stream may depend on accurate clock timing. In some implementations, the timing of the clock signal may determine whether a symbol in the data stream is interpreted as, for example, a 1 or a 0. Sometimes, a clock signal is received, but its phase information may not be determined. To improve data accuracy and data integrity, various clock signal phase alignment operations may sometimes be performed prior to starting up data or while receiving data so that accurate clock phase information may be provided to the ADC.

In integrated circuit applications, an ADC may typically use one or more transistor-implemented circuit stages to perform critical timing functions. In various ADC circuits, some transistors may operate in a linear mode to process analog signals. In some ADC circuits, certain transistors may be designed to operate as ideal switches (e.g., digital signals). An ideal transistor switch may operate in an on state or an off state in response to a control signal. In practice, however, transistors in real integrated circuits may exhibit non-ideal behavior with respect to intrinsic device characteristics and/or external parameters (e.g., device process parameters, applied voltages, and device temperature).

Disclosure of Invention

Apparatus and associated methods related to a switching leakage compensated delay circuit include a compensation transistor configured to passively bypass leakage current around a capacitor connected in series with a control transistor. In an illustrative example, the capacitor and the compensation transistor may be connected in parallel between the first node and the second node. For example, the compensation transistor gate may be directly connected to its source and second node. The control transistor may have its drain connected to the second node. When the control signal turns off the control transistor, the leakage current of the control transistor may be provided from the leakage current of the compensation transistor, such that the voltage across the capacitor may be kept substantially constant. The delay circuit may advantageously mitigate voltage droop of the capacitor to reduce clock timing skew, for example, in low speed interleaved ADC operation.

Various embodiments may realize one or more advantages. For example, the MOS capacitor can advantageously reduce the manufacturing steps and area of the delay circuit. Transistors of the same size and type as the switches can compensate for leakage caused by switching across process, voltage and temperature. In some embodiments, the transistors may be spatially positioned slightly above the switches to reduce negative impact on area. By introducing a switching leakage compensation delay circuit, some embodiments may enable the use of a time-offset DAC over a large clock frequency range, as the leakage problem is a large limitation of large clock frequency range applications. Some embodiments may enable the ADC to operate across frequency, process, voltage, temperature (PVT), and mismatch without any disadvantages. Some embodiments may be flexibly used, for example, in programmable logic, such as a Field Programmable Gate Array (FPGA), which may allow the delay circuit to be reconfigurable for the field. In some embodiments, cost, size, or power may be reduced, for example, when implemented on a fixed hardware platform such as an Application Specific Integrated Circuit (ASIC).

In one exemplary aspect, the delay circuit is configured to obtain a predetermined delay. The delay circuit includes a capacitor coupled between the first node and the second node. The delay circuit further includes a first transistor. The drain of the first transistor is connected to the second node, the source of the first transistor is connected to the reference node, and the gate of the first transistor is coupled to the first gate control signal. The first transistor modulates connectivity between the first drain and the first source in response to a first gate control signal. The delay circuit also includes a second transistor having a drain and a source and coupled in parallel with the capacitor, a gate of which is coupled to apply a voltage to the second gate that is less than a second threshold voltage of the second transistor. When in the first mode, the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the first transistor, the voltage across the capacitor being substantially constant.

In some embodiments, in the first mode, the first transistor may provide a first leakage current I_leak1First leakage current I_leak1And a second leakage current I provided by the second transistor_leak2Substantially matching. The second drain may be connected to the first node, and the second source may be connected to the second gate and the second node. The second transistor may be on the same die and have substantially the same dimensions as the first transistor. The first transistor may be an n-channel metal oxide semiconductor field effect transistor (NMOSFET) or a p-channel metal oxide semiconductor field effect transistor (PMOSFET). The first transistor may also be a transmission gate. In some embodiments, the second transistor may be an n-channel metal oxide semiconductor field effect transistor (NMOSFET). The capacitor may be a metal oxide semiconductor transistor. In some embodiments, the potential of the reference node may be a circuit ground potential. The second gate of the second transistor may be connected to the second node.

In another exemplary aspect, a system includes a buffer output coupled to drive a first node to make a predetermined delay on an input clock signal. The system also includes at least one delay circuit configured to obtain a predetermined delay. Each of the at least one delay circuit includes a capacitor coupled between a first node and a second node. Each of the at least one delay circuit further includes a first transistor having a drain connected to the second node, a source connected to the reference node, and a gate coupled to the first gate control signal. The first transistor modulates connectivity between the first drain and the first source in response to a first gate control signal. Each of the at least one delay circuit further includes a second transistor having a drain and a source and coupled in parallel with the capacitor, and a gate coupled to apply a voltage less than a second threshold voltage of the second transistor to the gate of the second transistor. In the first mode, when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the first transistor, the voltage across the capacitor is substantially constant.

In some embodiments, in the first mode, the first transistor may provide a first leakage current I_leak1First leakage current I_leak1And a second leakage current I provided by the second transistor_leak2Substantially matching. The second transistor may be on the same die and have the same dimensions as the first transistor. The first transistor may be an NMOSFET or a PMOSFET. The first transistor may also be a transmission gate. The second transistor may be an NMOSFET. The capacitor may be a metal oxide semiconductor transistor. In some embodiments, the potential of the reference node may be a circuit ground potential. In some embodiments, the gate of the second transistor may be connected to the second node.

In another exemplary aspect, a method includes providing a capacitor coupled between a first node and a second node, and providing a capacitor coupled between the first node and the second node. The method also includes providing a first transistor having a first drain connected to the second node, connected to a reference nodeAnd a first gate coupled to a first gate control signal, wherein the first transistor modulates connectivity between the first drain and the first source in response to the first gate control signal. The method also includes providing a second transistor having a second drain and a second source, the second transistor coupled in parallel with the capacitor, and having a second gate coupled to apply a voltage to the second gate that is less than a second threshold voltage of the second transistor. In addition, the method further includes, in the first mode, providing, with the second transistor, a first leakage current I drawn substantially by the first transistor to the first transistor when the first gate control signal applies a voltage to the first gate that is less than a first threshold voltage of the first transistor_leak1So that the voltage across the capacitor remains substantially constant.

In some embodiments, in the first mode, the second transistor may substantially match the first leakage current I_leak1. The second drain may be connected to the first node, and the second source may be connected to the second gate and the second node. The potential of the reference node may be a circuit ground potential. The second gate may be connected to a second node.

The details of various embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.

Brief Description of Drawings

FIG. 1 depicts an exemplary programmable Integrated Circuit (IC) on which the disclosed circuits and processes may be implemented.

Fig. 2 depicts an exemplary staggered analog-to-digital converter (ADC) with a switching leakage compensated delay system.

Fig. 3A depicts a delay system for an interleaved ADC.

Fig. 3B depicts the prior art delay circuit when the switches in the delay circuit are open in an idealized model.

Fig. 3C depicts an exemplary timing diagram of the delay circuit when a switch in the delay circuit is open and has a leakage current associated with the switch.

Fig. 4A depicts an exemplary switching leakage compensation delay circuit.

Fig. 4B depicts another example switching leakage compensation delay circuit.

Fig. 4C depicts an exemplary switching leakage compensated delay system implemented in fig. 2.

Fig. 5A depicts an exemplary experimental result, which shows a timing diagram of the delay circuit in fig. 3C.

Fig. 5B depicts example experimental results showing a timing diagram for the switching leakage compensation delay circuit in fig. 4C.

Fig. 6A depicts an exemplary simulation result of the delay circuit in fig. 3C.

Fig. 6B depicts exemplary simulation results of the switch leakage compensation delay circuit in fig. 4C.

FIG. 7 depicts a flow diagram of an exemplary method of performing switch leakage compensation.

Like reference symbols in the various drawings indicate like elements.

Detailed Description

Apparatus and associated methods related to a switching leakage compensated delay circuit include a compensation transistor configured to passively bypass leakage current around a capacitor connected in series with a control transistor. In an illustrative example, the capacitor and the compensation transistor may be connected in parallel between the first node and the second node. For example, the compensation transistor gate may be directly connected to its source and second node. The control transistor may have its drain connected to the second node. When the control signal turns off the control transistor, the leakage current of the control transistor may be provided from the leakage current of the compensation transistor, so that the voltage across the capacitor may be kept substantially constant. A delay circuit, such as the exemplary delay circuit 405a described with reference to fig. 4A, may advantageously mitigate voltage droop of the capacitor to reduce clock skew, such as in low speed interleaved ADC operation.

To facilitate understanding, the present disclosure is organized into the following structures. First, an exemplary platform (e.g., FPGA) suitable for performing analog-to-digital conversion is briefly described with reference to fig. 1. 2-4C, a discussion is turned to introduce how the exemplary circuit is used to introduce a predetermined delay and compensate for leakage current provided by the switch. Then, referring to fig. 5A and 6B, exemplary experimental results and simulation results disclosing exemplary circuits are discussed. Finally, with reference to fig. 7, an exemplary method of performing switching leakage compensation is discussed. By using a delay circuit, leakage current can be compensated and time offset digital-to-analog converter (DAC) functionality at low speed can be advantageously addressed.

FIG. 1 depicts an exemplary programmable Integrated Circuit (IC) on which the disclosed circuits and processes may be implemented. Programmable integrated circuit 100 includes FPGA logic. The programmable integrated circuit 100 may be implemented with various programmable resources and may be referred to as a system on a chip (SOC). Various examples of FPGA logic may include several different types of programmable logic blocks in an array.

For example, fig. 1 illustrates a programmable integrated circuit 100 including a large number of different programmable tiles (tiles), including a multi-gigabit transceiver (MGT)101, a Configurable Logic Block (CLB)102, a random access memory Block (BRAM)103, an input/output block (IOB)104, configuration and clock logic (CONFIG/CLOCKS)105, a digital signal processing block (DSP)106, a dedicated input/output block (I/O)107 (e.g., clock port), and other programmable logic 108 (e.g., digital clock manager, analog-to-digital converter, system monitoring logic). The programmable integrated circuit 100 includes a dedicated processor block (PROC) 110. Programmable integrated circuit 100 may include internal and external reconfiguration ports (not shown).

In various examples, the serializer/deserializer may be implemented using MGT 101. MGT 101 may include various data serializers and deserializers. The data serializer may include various multiplexer embodiments. The data deserializer may include various demultiplexer embodiments.

In some examples of FPGA logic, each programmable tile includes a programmable interconnect element (INT)111 having standardized interconnects 124 to and from corresponding interconnect elements in each adjacent tile. Thus, the programmable interconnect elements together implement the programmable interconnect structure of the FPGA logic shown. The programmable interconnect element INT 111 includes internal connections 120 to and from the programmable logic element within the same die, as shown in the example included in fig. 1. The programmable interconnect element INT 111 includes an internal INT connection 122 to and from the programmable interconnect element INT 111 within the same die, as shown in the example included in fig. 1.

For example, the CLB 102 may include a Configurable Logic Element (CLE)112, which may be programmed to implement user logic, plus a single programmable interconnect element INT 111. BRAM 103 may include a BRAM logic element (BRL)113 and one or more programmable interconnect elements. In some examples, the number of interconnect elements included in a sheet may depend on the height of the sheet. In the illustrated embodiment, one BRAM tile has the same height as five CLBs, but other numbers (e.g., four) are possible. DSP tile 106 may include DSP logic elements (DSPL)114 and one or more programmable interconnect elements. The IOB 104 may include, for example, two instances of an input/output logic element (IOL)115 and one instance of a programmable interconnect element INT 111. For example, the actual I/O bond pads connected to the I/O logic element 115 may be fabricated using metal layered above the various illustrated logic blocks and may not be limited to the area of the input/output logic element 115.

In the illustrated embodiment, columnar areas (shown shaded in fig. 1) near the center of the die (die) are used for configuration, clock, and other control logic. Horizontal regions 109 extending from the columns distribute clock and configuration signals across the width of the programmable integrated circuit 100. Note that the terms "columnar" and "horizontal" regions are relative to viewing the illustration in a longitudinal direction.

Some programmable integrated circuits utilizing the architecture shown in fig. 1 may include additional logic blocks that would disrupt the conventional columnar structure making up a large portion of the programmable integrated circuit. The additional logic blocks may be programmable blocks and/or dedicated logic. For example, processor block PROC 110 shown in fig. 1 spans multiple columns of CLBs 102 and BRAMs 103.

Fig. 1 illustrates an exemplary programmable IC architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementation are provided purely as examples. For example, in an actual programmable IC, more than one adjacent column of CLBs 102 may be included wherever CLBs 102 appear to facilitate efficient implementation of user logic.

At least one transceiver may be embedded in the FPGA for data transmission and data reception during communication. Analog-to-digital conversion is the process of converting a continuous range of analog signal levels into digital codes. The analog signal level may be converted to a digital voltage, digital current, or digital charge signal using an ADC. ADCs are useful in many applications, such as communication systems. Switches and capacitors may be used in the ADC to control the sampling of the ADC. The switch leakage compensation circuit may be used to compensate for leakage current introduced by the switch and advantageously maintain switching accuracy.

Fig. 2 depicts an exemplary interleaved analog-to-digital converter (ADC) with a switching leakage compensated delay system. The communication system 200 includes a base station 205. The base station 205 may be used to transmit data to and receive data from some data communication devices. In this illustrative example, the base station 205 receives an analog signal from a cellular telephone 210. The base station 205 includes an FPGA 215 to perform data communications through an antenna 220 between the base station 205 and the cellular telephone 210. The antenna 220 transmits the received analog signal 225 to the filter 230. The filter 230 filters errors and/or noise in the analog signal 225. The filtered analog signal is amplified by amplifier 235 to generate processed analog signal 240. The processed analog signal 240 is converted to a digital signal 250 by an analog-to-digital converter (ADC) system 245. The digital signal 250 is then processed, for example, by a Digital Signal Processor (DSP) 255.

High speed electronics (e.g., 5G technology) may require a high sampling rate ADC. For example, the receiver may use a 5 Gigasamples per second (GSPS) ADC with a 1GHz, dc-coupled, fully differential amplifier front-end. Each signal may be sampled at 200 ps. Time-interleaved ADCs can be used to achieve high sampling rates. For example, by using a time-interleaved ADC comprising four sub-ADCs, each of the four sub-ADCs may only need to have a sampling rate of, for example, 1.25 GSPS.

In the depicted example, the processed analog signal 240 is received by a buffer 260 and then sampled by four sub-ADCs 265a, 265b, 265c, 265 d. For example, the first sample may be sampled by the first ADC 265 a. Each of the four sub-ADCs 265a, 265b, 265c, 265d is driven by a sampling driver circuit. Each sampling driver circuit generates a different sampling clock signal. For example, the first sampling clock signal used by the first sub-ADC 265a may have a phase difference of 0 degrees compared to the reference clock signal. The second sampling clock signal used by the second sub-ADC 265b may have a phase difference of 90 degrees compared to the reference clock signal. The third sampling clock signal used by the third sub-ADC 265c may have a phase difference of 180 degrees compared to the reference clock signal. The fourth sampling clock signal used by the fourth sub-ADC 265d may have a phase difference of 270 degrees compared to the reference clock signal.

Each of the sub-ADCs 265a, 265b, 265c, 265d may sample at precise times (e.g., a first sub-ADC 265a may sample at 0s, a second sub-ADC 265b may sample at 800ps, a third sub-ADC 265c may sample at 1600ps, and a fourth sub-ADC 265d may sample at 2400 ps). The electrical characteristics of each sub-ADC may vary due to manufacturing or technical limitations. The mismatch of the sub-ADCs may generate harmonic spurs and interlace spurs. For example, the first sub-ADC 265a may sample at 800ps ± 10 fs. Even for small quantities like 10fs, time offsets may result, especially when the highest intermediate frequency of interest is in the GHz range and there is a strict specification for alternating tones (tones). In the depicted example, each sampling driver circuit includes a first buffer (e.g., inverter) 270 and a second buffer (e.g., inverter) 275 to hold the phase of the sampled signal. Between the first buffer 270 and the second buffer 275, a switching leakage compensation delay system 280 is arranged to introduce a predetermined delay on the analog signal processed in reverse to solve the time offset problem. Referring to fig. 4A-4C, an example of the switching leakage compensation delay system 280 will be described in more detail.

Each of the sub-ADCs 265a, 265b, 265c, 265d is connected to a selection circuit 285 (e.g., a multiplexer). The selection circuit 285 selectively outputs signals sampled by the four sub-ADCs 265a, 265b, 265c, 265d to form the digital signal 250.

Fig. 3A depicts a prior art delay system for an interleaved ADC. In the prior art, the delay system 300 is disposed between the first buffer 270 and the second buffer 275. The delay system 300 includes one or more delay circuits 305 connected in parallel. For example, the first delay circuit 305 includes a first capacitor C₀Arranged to introduce a delay on the incoming sampling clock signal. In some embodiments, capacitor C₀May be a MOS capacitor. Capacitor C₀Another end of (b) through node b₀And a first switch M₀Are connected. First switch M₀By a control signal D₀And (5) controlling. In the depicted example, switch M₀Including N-channel metal oxide semiconductor field effect transistors (NMOSFETs). The drain of the NMOSFET is connected to the node b₀. The source of the NMOSFET is grounded. Gate driven signal D of NMOSFET₀And (5) controlling.

The capacitance in the delay circuit may or may not be added to the circuit by closing or opening the switches of the respective delay circuits. Then can pass through the control signal D₀、D₁…D_N-1To program the delay. Depicts a node b₀The corresponding waveform of (a). During the rising edge of the start of sampling CLK _ BAR, node b₀Is raised to V_dda。V_dda(e.g., 0.9v) is the power supply for buffer 270 and the high level of the clock signal through buffer 270 and buffer 275.

Fig. 3B depicts the prior art delay circuit when the switches in the delay circuit are open in an idealized model. In the depicted example, the first transistor M₀No leakage current and parasitic capacitance C_b0Can be omitted. A second node b is depicted₀The corresponding waveform of (a). When the transistor M₀In the absence of leakage current, the waveform of the sampling clock signal appears to remain good.

FIG. 3C depicts an example of a delay circuit when a switch in the delay circuit is open and has a leakage current associated with the switchAn exemplary timing diagram. In practice, the first transistor M₀With leakage currents. When the transistor M₀When there is leakage current and the speed of the ADC is low, the waveform of the sampling clock signal is not an ideal sampling clock signal because the leakage current may cause the transistor M to leak₀Is no longer turned off, even though transistor M₀The gate voltage of (e.g., N-channel MOSFET) is 0V. The timing diagram reveals the capacitor and the transistor M₀The adverse effect of the capacitor voltage drop at the junction therebetween.

Showing a second node b₀The corresponding waveform of (a). During the rising edge of the sample start CLK _ BAR, due to C_b0Of a second node b₀Does not rise to V_dda. Second node b₀The voltage at is raised to V_b0H。

V_b0H＝(V_dda*C₀)/(C₀+C_b0). The leakage current may cause the second node b₀The voltage at (a) leaks to zero. As shown in fig. 3C, the transistor M₀Not turned off during the end of the sampling, which may affect the time-offset DAC function at low speed. Due to negative voltage, M₀Becomes M₀Source electrode of, M₀Becomes M₀Of the substrate. Thus, the transistor M₀The saturation state can be entered from the cut-off state. E.g. b₀The impedance to ground may be M₀1/g of_mThis is in conjunction with M₀May be a lower value than the on-resistance of (a).

Fig. 4A depicts an exemplary switching leakage compensation delay circuit. The delay circuit 405a includes a first capacitor C₀. A first capacitor C₀Arranged at a first node a₀And a second node b₀In the meantime. A first capacitor C₀For passing through the first node a₀A predetermined delay is introduced on the incoming sampling clock signal. In some embodiments, capacitor C is used for precision and small area₀May be a MOS capacitor.

Capacitor C₀Via a second node b₀And a first transistor M₀Are connected. Examples of the type describedIn, the transistor M₀Is an N-channel metal oxide semiconductor field effect transistor (NMOSFET). Transistor M₀Is connected to a second node b₀. Transistor M₀Is connected to a reference node (e.g., ground). Transistor M₀Is controlled by a signal D₀And (5) controlling. In response to a controlled signal D₀Transistor M₀The connectivity between the drain and source is modulated. When the transistor M₀Is less than the voltage applied between the gate and the source of the transistor M₀Threshold voltage V of_T1Then, due to the sub-threshold effect, the transistor M₀Providing a first leakage current I_leak1. As discussed in FIG. 3C, the first leakage current I_leak1A time offset may result.

The delay circuit 405a further comprises a second transistor T₀. In the depicted example, the second transistor T₀Is an NMOSFET. Second transistor T₀And a capacitor C₀Are connected in parallel. Second transistor T₀Is coupled to the first node a₀. Second transistor T₀Is coupled to the second node b₀. Second transistor T₀The gate of the transistor is coupled to a voltage. When a voltage is applied to the gate electrode, the second transistor T is enabled₀Voltage difference V between the gate and the source of_gsSmaller than the second transistor T₀Threshold voltage V of_T2While the second transistor T₀There is no conductive path between the second source and the second drain. Due to sub-threshold effect, the second transistor T₀A second leakage current I is also introduced_leak2. Second leakage current I_leak2Counteracts and compensates the first leakage current I_leak1This may be the second node b₀The voltage at (a) is substantially constant over time.

In the example described here, the second transistor T₀Both the gate and the source are coupled to a second node b₀. By connecting the source electrode and the grid electrode, the voltage difference V between the source electrode and the grid electrode_gsIs 0 and is smaller than the second transistor T₀Threshold voltage V of_T2. By connecting the source and the gate, wiring complexity and delay can be reducedArea of the vias and steps of the manufacturing process.

In some embodiments, the second transistor T₀Can be designed to substantially replicate the transistor M₀And/or may be on the same die (die) and have the same transistor M₀The same type and substantially the same size. Transistor M₀Can be substantially precisely matched (e.g., dimensionally) across process, voltage, and temperature. In some embodiments, the second transistor T₀May be arranged higher than the transistor M₀The position of (a). In some embodiments, C may be reduced by₀To compensate the second transistor T₀Increased capacitance of (a).

By introducing a second transistor T in the delay circuit 405a₀Make the second node b₀Voltage V of_b0HAnd remain constant. V_b0H＝(V_dda*C₀)/(C₀+C_b0) In which Cb₀Is a transistor M₀The parasitic capacitance of (1).

Fig. 4B depicts another example switching leakage compensation delay circuit. The delay circuit 405b includes a first capacitor C₀'. A first capacitor C₀' arranged at a reference node (e.g. ground potential) and a second node b₀' in the meantime. A first capacitor C₀' for transmitting to a first node a₀' introduces a predetermined delay on the incoming sampling clock signal. In some embodiments, capacitor C is used for precision and small area₀' may be a MOS capacitor.

Capacitor C₀The other end of' goes through a second node b₀' with the first transistor M₀' connected to each other. In this depicted example, the first transistor M₀' is a P-channel metal oxide semiconductor field effect transistor (PMOSFET). In some embodiments, the first transistor M₀' may be a transmission gate. The delay circuit 405b further includes a second transistor T₀'. In the example described here, the second transistor T₀' is a PMOSFET. In some embodiments, the second transistor T₀' may be a transmission gate or a transmission gate,since both power and ground need to be delivered to the capacitor on the rising and falling edges, respectively. In effect, the second transistor T in the delay circuit 405b is due to the sub-threshold effect₀' leakage current is introduced, which can be used to compensate the first transistor M₀' leakage current provided. Thus, the second node b₀Voltage at V_b0HAnd remain constant.

Fig. 4C depicts an exemplary switching leakage compensated delay system implemented in fig. 2. The switching leakage compensation delay system 280 includes at least one delay circuit 405a connected in parallel. In each delay circuit 405a, a switch M₀、M₁…M_N-1Respectively by binary voltage signals D₀、D₁…D_N-1And (5) controlling. By controlling the application to switches M respectively₀、M₁…M_N-1Binary voltage signal D of the grid₀、D₁…D_N-1A programmable delay can be obtained. Switch M₀、M₁…M_N-1The introduced leakage current can pass through the transistors T respectively₀、T₁…T_N-1Compensation is performed. When M is₀、M₁…M_N-1May be turned on by a corresponding off transistor (T)₀、T₁…T_N-1) And (4) loading. The on-resistance of buffer 270 may be low because it needs to meet jitter specifications or transition times in all systems implementing time-offset DACs.

In some embodiments, the switch leakage compensation delay system 280 may include at least one delay circuit 405b connected in parallel. Switch M₀’、M₁’…M_N-1' can be respectively composed of binary voltage signals D₀、D₁…D_N-1And (5) controlling. By controlling the application to switches M respectively₀’、M₁’…M_N-1' binary voltage signal D of gate₀’、D₁’…D_N-1', a programmable delay can be obtained. Switch M₀’、M₁’…M_N-1' the induced leakage current can be passed through the transistors T respectively₀’、T₁’…T_N-1' compensation is performed.

Fig. 5A shows an exemplary experimental result of a timing diagram of the delay circuit in fig. 3C. In this experiment, an ADC with a 125MSPS sampling rate was tested at a fast fast process corner (FF corner). The duration of the sampling pulse is about 2 ns. The falling edge of the sampling clock is important. Switch M is detected at 110 ℃₀The leakage current of (1). Switch M₀The threshold value of (2) is 0.25V. As shown in FIG. 5A, there is a significant drop after 2ns, which results in node b at the end of 2ns₀The voltage at which the transistor M is turned off shows a negative spike₀The transconductance of (a) appears to be positive. M₀Rises to 205uS (about 5k Ohm), while a₀The voltage at (a) drops from 0.9V to 0V. Due to the transistor M₀Of the transistor M₀Is turned on and the capacitor C₀Connected at a through a 5k resistor₀And the ground.

Fig. 5B illustrates an exemplary experimental result of a timing diagram of the switching leakage compensation delay circuit in fig. 4C. In this experiment, an ADC with a 125MSPS sampling rate was tested at a fast fast process corner (FF corner). The duration of the sampling pulse is about 2 ns. The falling edge of the sampling clock is important here. Switch M is detected at 110 ℃₀Leakage current and switch T₀The leakage current of (1). Switch M₀The threshold voltage of (2) is 0.25V. As shown in fig. 5B, even with a slight drop after 2ns, the drop is barely visible and there is no negative spike at the end of 2 ns. Switch M₀Leakage current and switch T₀The leakage currents of (a) are almost the same. So that the switch M₀Can be switched by a switch T₀The leakage current of (2) is cancelled.

Fig. 6A shows an exemplary simulation result of the delay circuit in fig. 3C. In this simulation, the basic unit of the time-offset DAC is designed to provide a step size of 8fs at the end of the sampling. Each sub-ADC operates at 625MSPS (the overall ADC at 5GSPS, interval 8) with a sampling period of 200 ps. The 100-point Monte Carlo (Monte-Carlo) simulation was performed at 125MSPS (1/5 at full speed). As shown in the table, the maximum sampling starts at 10.08fs and the maximum sampling ends at 21.79 fs. MiningThe sample ending point may be subject to switch M₀The significant effect of leakage current. Since many of the closing units are opened, the maximum step size increases more than twice, which may result in lost time steps.

Fig. 6B shows an exemplary simulation result of the switching leakage compensation delay circuit in fig. 4C. Under the same simulation environment, by using the delay system as shown in fig. 4C, the maximum end-of-sample is 11.43fs, which is significantly smaller than 21.79fs in fig. 6A. Thus, the mismatch problem caused by switch leakage can be solved.

Fig. 7 shows a flow diagram of an exemplary method of performing switch leakage compensation. The method 700 of compensating for switching leakage includes, at 705, providing a coupling at a first node (e.g., a)₀) And a second node (e.g., b)₀) Capacitor in between (e.g. C)₀). The method 700 further includes, at 710, providing a first transistor (e.g., M)₀) Wherein the first transistor M₀Is connected to a second node (b)₀) First transistor M₀Is connected to a reference node, and a first transistor M₀Is coupled to a first gate control signal (e.g., D)₀). First transistor M₀In response to the first gate control signal D₀To modulate the first transistor M₀The drain and source of (a).

The method 700 further includes, at 715, providing a second transistor (e.g., T)₀) A second transistor T₀Drain and source of (C) and capacitor (C)₀) Are coupled in parallel and a second transistor T₀Is coupled to the second transistor T₀Is less than the second transistor (T)₀) Of the second threshold voltage. At 720, the first transistor M is dynamically monitored₀Whether or not enabled. If the first transistor M₀Is controlled by a first gate control signal D₀Enabled, then the method 700 further includes, at 725, passing the second transistor (T)₀) Providing a voltage substantially consisting of the first transistor M₀A first leakage current I drawn_leak1So as to cross over the capacitor C₀The voltage across the terminals remains substantially constant.

Although various embodiments have been described with reference to the accompanying drawings, other embodiments are possible. E.g. the second node b₀Can be connected to V through a resistor_dda. In some embodiments, switch M₀、M₁…M_N-1May be replaced by a transistor having a high threshold voltage. In some embodiments, M₀、M₁…M_N-1May be increased.

In some embodiments, the delay circuit may be used in other systems. For example, in a Voltage Controlled Delay Line (VCDL), a transistor may be used as a switch. Another transistor may be introduced to compensate for leakage current provided by the transistor in the VCDL.

While various embodiments may be implemented using reconfigurable programmable logic blocks (e.g., FPGAs), other embodiments may be implemented in fixed implementations (e.g., ASICs). While dedicated hard block circuitry in an ASIC implementation may not be reconfigurable once instantiated in an integrated circuit, for example, in some embodiments, an ASIC implementation may provide a minimized platform for, for example, power consumption and/or die area.

Various examples of delay circuits may be implemented using circuitry, including various electronic hardware. By way of example, and not limitation, hardware may include transistors, resistors, capacitors, switches, integrated circuits, and/or other circuitry. In various examples, the delay circuit may include analog and/or digital logic, discrete components, traces, and/or memory circuits, which may be fabricated on a silicon substrate including various integrated circuits (e.g., FPGA, ASIC, SoC). In some embodiments, the delay circuit may involve the execution of pre-programmed instructions and/or software executed by the control circuit. For example, a control circuit may be used to generate a predetermined control signal to control a switch in the delay circuit.

In various embodiments, the communication system may communicate using suitable communication methods, devices, and techniques. For example, a system may communicate with compatible devices (e.g., devices capable of transmitting data to and/or receiving data from the system) using point-to-point communication, where messages are transmitted directly from a source to a receiver over a dedicated physical link (e.g., fiber optic link, infrared link, ultrasonic link, point-to-point wiring, daisy chain). The components of the system may exchange information via any form or medium of analog or digital data communication, including packet-based messages over a communication network. Examples of communication networks include, for example, LANs (local area networks), WANs (wide area networks), MANs (metropolitan area networks), wireless and/or optical networks, and the computers and networks forming the internet. Other embodiments may transmit the message by broadcasting to all or substantially all devices coupled together by the communication network, for example by using an omnidirectional Radio Frequency (RF) signal. Other embodiments may transmit messages with high directivity characteristics, such as radio frequency signals transmitted using a directional (i.e., narrow beam) antenna or infrared signals optionally used with focusing optics. Other embodiments are possible using appropriate interfaces and protocols, such as, by way of example and not limitation, USB2.0, FireWire, ATA/IDE, RS-232, RS-422, RS-485, 802.11a/b/g/n, Wi-Fi, WiFi-Direct, Li-Fi, Bluetooth, Ethernet, IrDA, FDDI (fiber distributed data interface), token Ring network, or multiplexing based on frequency, time, or code division. Some embodiments may optionally include functionality such as Error Checking and Correction (ECC) for data integrity, or security measures such as encryption (e.g., WEP) and password protection.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications may be made. For example, advantageous results may be achieved if the steps of the disclosed techniques were performed in a different order, or if components of the disclosed systems were combined in a different manner, or if the components were supplemented by other components. Accordingly, other implementations are within the scope of the following claims.