阅读说明：本技术 半导体结构的形成方法 (Method for forming semiconductor structure ) 是由 郑二虎 于 2020-05-12 设计创作，主要内容包括：一种半导体结构的形成方法,其特征在于,包括：提供初始衬底,所述初始衬底包括若干无效区,以及包围所述无效区的有效区；在所述无效区的初始衬底内形成切割层；在所述初始衬底表面形成若干第一掩膜结构,至少1个第一掩膜结构横跨所述切割层；以所述第一掩膜结构为掩膜,刻蚀所述切割层和初始衬底,直至形成衬底、若干位于衬底上的第一鳍部结构、以及若干位于衬底上的第一伪鳍结构；在形成所述第一鳍部结构和第一伪鳍结构后,去除若干所述第一伪鳍结构。从而,提高了半导体结构的性能。(A method of forming a semiconductor structure, comprising: providing an initial substrate, wherein the initial substrate comprises a plurality of invalid regions and an active region surrounding the invalid regions; forming a cutting layer in the initial substrate of the invalid region; forming a plurality of first mask structures on the surface of the initial substrate, wherein at least 1 first mask structure spans the cutting layer; etching the cutting layer and the initial substrate by taking the first mask structure as a mask until a substrate, a plurality of first fin structures located on the substrate and a plurality of first pseudo fin structures located on the substrate are formed; and after the first fin part structure and the first pseudo fin structure are formed, removing a plurality of first pseudo fin structures. Thus, the performance of the semiconductor structure is improved.)

1. A method of forming a semiconductor structure, comprising:

providing an initial substrate, wherein the initial substrate comprises a plurality of invalid regions and an active region surrounding the invalid regions;

forming a cutting layer in the initial substrate of the invalid region, wherein the surface of the initial substrate is exposed out of the surface of the cutting layer;

forming a plurality of first mask structures on the surfaces of the invalid area and the effective area, wherein at least 1 first mask structure spans the cutting layer;

etching the cutting layer and the initial substrate by taking the first mask structure as a mask until a substrate, a plurality of first fin structures located on the substrate and a plurality of first pseudo fin structures located on the substrate are formed, wherein the first fin structures are mutually separated and located in the active area, and the first pseudo fin structures are located in the inactive area;

and after the first fin part structure and the first pseudo fin structure are formed, removing a plurality of first pseudo fin structures.

2. The method of forming a semiconductor structure of claim 1, wherein the method of forming the cleave layer comprises: and forming a second mask structure on the initial substrate surface, wherein the second mask structure exposes the initial substrate surface of the invalid region.

3. The method of forming a semiconductor structure of claim 2, wherein the second mask structure comprises a second mask layer; the method for forming the second mask layer comprises the following steps: forming a second mask material layer on the surfaces of the active area and the inactive area; forming a second photoresist layer on the surface of the second mask material layer, wherein the second photoresist layer exposes the surface of the second mask material layer on the invalid region; and etching the second mask material layer by taking the second photoresist layer as a mask until the surface of the initial substrate is exposed.

4. The method of claim 3, wherein a material of the second mask layer comprises spin-on carbon.

5. The method of forming a semiconductor structure of claim 3, wherein the second mask structure further comprises a second hard mask layer, the second mask layer being located on a surface of the second hard mask layer; the method for forming the second hard mask layer comprises the following steps: forming a second hard mask material layer on the surfaces of the active area and the inactive area before forming the second mask material layer; and after the second mask material layer is etched, continuously etching the second hard mask material layer until the initial substrate surface is exposed.

6. The method of claim 5, wherein the material of the second hard mask layer comprises one or more of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon, or silicon nitride in combination.

7. The method of forming a semiconductor structure of claim 3, further comprising: before forming the second photoresist layer, forming an anti-reflection layer on the surface of the second mask material layer.

8. The method of forming a semiconductor structure of claim 3, wherein the method of forming the cleave layer further comprises: etching the initial substrate by taking the second mask structure as a mask so as to form a first opening in the invalid region; and forming the cutting layer in the first opening.

9. The method for forming a semiconductor structure according to claim 8, wherein an etching selection ratio of the material of the initial substrate to the material of the second mask layer in the etching process for forming the first opening is greater than 5: 1.

10. The method of forming a semiconductor structure of claim 8, wherein forming the dicing layer within the first opening comprises: forming a cutting material layer in the initial substrate surface and the first opening, wherein the process for forming the cutting material layer comprises one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or an epitaxial growth process; planarizing the dicing material layer until the initial substrate surface is exposed.

11. The method of forming a semiconductor structure of claim 2, wherein the method of forming the cleave layer further comprises: and carrying out ion doping process on the initial substrate of the invalid region by taking the second mask structure as a mask.

12. The method of forming a semiconductor structure of claim 11, wherein the ion doping process comprises an ion implantation process.

13. The method of claim 12, wherein the process parameters of the ion implantation process comprise: the dose range of implantation is 1.0e16atom/cm³～1.0e20atom/cm³(ii) a The implantation energy is in the range of 10KeV to 200 KeV.

14. The method of claim 1, wherein the material of the cleave layer comprises a combination of one or more of silicon nitride, silicon oxide, silicon germanium, and silicon phosphide.

15. The method of claim 1, wherein the material of the first mask structure comprises one or a combination of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon nitride.

16. The method for forming a semiconductor structure according to claim 1, wherein the etching process for etching the cutting layer and the initial substrate has an etching selection ratio of the material of the cutting layer to the material of the first mask structure of 3:1 or more.

17. The method of claim 1, wherein the process of forming the plurality of first mask structures comprises a multiple self-aligned patterning process.

18. The method of forming a semiconductor structure of claim 17, wherein forming a plurality of the first mask structures comprises: forming a first mask material layer on the initial substrate of the active area and the surface of the cutting layer of the inactive area; forming a plurality of first core mold structures which are separated from each other on the surface of the first mask material layer; forming a first side wall on the side wall surface of each first core mold structure; and etching the first mask material layer by taking the first side wall as a mask until the surface of the cutting layer and the surface of the initial substrate are exposed.

19. The method for forming the semiconductor structure according to claim 18, wherein the method for forming the first sidewall spacers comprises: forming a first side wall material layer on the surface of the first mask material layer and the surface of the first core mold structure; and etching the first side wall material layer back until the surface of the first mask material layer and the top surface of the first core mold structure are exposed.

20. The method of forming a semiconductor structure of claim 18, wherein forming the first core mold structure comprises: forming a first core mold material layer on the surface of the first mask material layer; forming a first photoresist layer on the surface of the first core mold material layer, wherein part of the surface of the first core mold material layer is exposed out of the first photoresist layer; and etching the first mandrel material layer by taking the first photoresist layer as a mask until the surface of the first mask material layer is exposed.

21. The method of forming a semiconductor structure of claim 18, wherein forming the first core mold structure comprises: forming a first core mold material layer on the surface of the first mask material layer; forming a plurality of second core mold structures which are mutually separated on the surface of the first core mold material layer; forming a second side wall on the side wall surface of the second core mold structure; and etching the first mandrel material layer by taking the second side wall as a mask until the surface of the first mask material layer is exposed.

22. The method of forming a semiconductor structure of claim 18, wherein the material of the first core mold structure comprises a combination of one or more of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, and photoresist.

23. The method for forming the semiconductor structure according to claim 18, wherein the material of the first side wall comprises: silicon oxide, silicon nitride, a combination of one or more of silicon and titanium oxide.

24. The method of forming a semiconductor structure of claim 18, further comprising: before forming the first mask material layer, forming a first protective material layer on the initial substrate of the active region and the surface of the cutting layer of the inactive region; and after the first mask material layer is etched, continuously etching the first protective material layer until the surface of the cutting layer and the surface of the initial substrate are exposed to form a first protective layer.

25. The method of forming a semiconductor structure of claim 24, wherein a material of the first protective layer comprises silicon oxide.

26. The method of forming a semiconductor structure of claim 1, wherein the process of removing the first dummy fin structure comprises an etching process in which an etch selectivity ratio of a material of the first dummy fin structure to a material of the substrate is above 5: 1.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.

Background

With the high integration of Semiconductor devices, the length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) channel is continuously shortened, a series of negligible effects in a MOSFET long channel model become more significant, and even become a leading factor affecting the device performance, and the phenomena are collectively called as short channel effects. Short channel effects can degrade the electrical performance of the device, such as causing problems of reduced gate threshold voltage, increased power consumption, and reduced signal-to-noise ratio.

In order to overcome the short channel effect, a three-dimensional device structure of a fin field effect transistor is provided, the fin field effect transistor is a transistor with a fin-type channel structure, and the fin field effect transistor utilizes a plurality of surfaces of a thin fin as a channel, so that the short channel effect in the traditional transistor can be prevented, and meanwhile, the working current can be increased. In the fin field effect transistor manufacturing process, the fabrication of the fin is a very important part.

However, the performance of the existing semiconductor structures is still poor.

Disclosure of Invention

The invention provides a method for forming a semiconductor structure, which improves the pattern precision of a cutting layer and a first fin portion structure, reduces the defects of the semiconductor structure and improves the performance of the semiconductor structure.

In order to solve the above technical problem, an aspect of the present invention provides a method for forming a semiconductor structure, including: providing an initial substrate, wherein the initial substrate comprises a plurality of invalid regions and an active region surrounding the invalid regions; forming a cutting layer in the initial substrate of the invalid region, wherein the surface of the initial substrate is exposed out of the surface of the cutting layer; forming a plurality of first mask structures on the surfaces of the invalid area and the effective area, wherein at least 1 first mask structure spans the cutting layer; etching the cutting layer and the initial substrate by taking the first mask structure as a mask until a substrate, a plurality of first fin structures located on the substrate and a plurality of first pseudo fin structures located on the substrate are formed, wherein the first fin structures are mutually separated and located in the active area, and the first pseudo fin structures are located in the inactive area; and after the first fin part structure and the first pseudo fin structure are formed, removing a plurality of first pseudo fin structures.

Optionally, the method for forming the cutting layer includes: and forming a second mask structure on the initial substrate surface, wherein the second mask structure exposes the initial substrate surface of the invalid region.

Optionally, the second mask structure includes a second mask layer; the method for forming the second mask layer comprises the following steps: forming a second mask material layer on the surfaces of the active area and the inactive area; forming a second photoresist layer on the surface of the second mask material layer, wherein the second photoresist layer exposes the surface of the second mask material layer on the invalid region; and etching the second mask material layer by taking the second photoresist layer as a mask until the surface of the initial substrate is exposed.

Optionally, the material of the second mask layer includes spin-on carbon.

Optionally, the second mask structure further includes a second hard mask layer, and the second mask layer is located on the surface of the second hard mask layer; the method for forming the second hard mask layer comprises the following steps: forming a second hard mask material layer on the surfaces of the active area and the inactive area before forming the second mask material layer; and after the second mask material layer is etched, continuously etching the second hard mask material layer until the initial substrate surface is exposed.

Optionally, the material of the second hard mask layer includes one or more of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon, and silicon nitride.

Optionally, the method further includes: before forming the second photoresist layer, forming an anti-reflection layer on the surface of the second mask material layer.

Optionally, the method for forming the cutting layer further includes: etching the initial substrate by taking the second mask structure as a mask so as to form a first opening in the invalid region; and forming the cutting layer in the first opening.

Optionally, in the etching process for forming the first opening, an etching selection ratio of the material of the initial substrate to the material of the second mask layer is greater than 5: 1.

Optionally, the method for forming the cutting layer in the first opening includes: forming a cutting material layer in the initial substrate surface and the first opening, wherein the process for forming the cutting material layer comprises one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or an epitaxial growth process; planarizing the dicing material layer until the initial substrate surface is exposed.

Optionally, the method for forming the cutting layer further includes: and carrying out ion doping process on the initial substrate of the invalid region by taking the second mask structure as a mask.

Optionally, the ion doping process includes an ion implantation process.

Optionally, the process parameters of the ion implantation process include: the dose range of implantation is 1.0e16atom/cm³～1.0e20atom/cm³(ii) a The implantation energy is in the range of 10KeV to 200 KeV.

Optionally, the material of the cutting layer includes one or more of silicon nitride, silicon oxide, silicon germanium and silicon phosphide.

Optionally, the material of the first mask structure includes one or more of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon nitride.

Optionally, in the etching process for etching the cutting layer and the initial substrate, the etching selection ratio of the material of the cutting layer to the material of the first mask structure is more than 3: 1.

Optionally, the process of forming a plurality of first mask structures includes a multiple self-aligned patterning process.

Optionally, the method for forming a plurality of first mask structures includes: forming a first mask material layer on the initial substrate of the active area and the surface of the cutting layer of the inactive area; forming a plurality of first core mold structures which are separated from each other on the surface of the first mask material layer; forming a first side wall on the side wall surface of each first core mold structure; and etching the first mask material layer by taking the first side wall as a mask until the surface of the cutting layer and the surface of the initial substrate are exposed.

Optionally, the method for forming the first sidewall includes: forming a first side wall material layer on the surface of the first mask material layer and the surface of the first core mold structure; and etching the first side wall material layer back until the surface of the first mask material layer and the top surface of the first core mold structure are exposed.

Optionally, the method for forming the first core mold structure includes: forming a first core mold material layer on the surface of the first mask material layer; forming a first photoresist layer on the surface of the first core mold material layer, wherein part of the surface of the first core mold material layer is exposed out of the first photoresist layer; and etching the first mandrel material layer by taking the first photoresist layer as a mask until the surface of the first mask material layer is exposed.

Optionally, the method for forming the first core mold structure includes: forming a first core mold material layer on the surface of the first mask material layer; forming a plurality of second core mold structures which are mutually separated on the surface of the first core mold material layer; forming a second side wall on the side wall surface of the second core mold structure; and etching the first mandrel material layer by taking the second side wall as a mask until the surface of the first mask material layer is exposed.

Optionally, the material of the first core mold structure includes one or more of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, and photoresist.

Optionally, the first side wall is made of a material including: silicon oxide, silicon nitride, a combination of one or more of silicon and titanium oxide.

Optionally, the method further includes: before forming the first mask material layer, forming a first protective material layer on the initial substrate of the active region and the surface of the cutting layer of the inactive region; and after the first mask material layer is etched, continuously etching the first protective material layer until the surface of the cutting layer and the surface of the initial substrate are exposed to form a first protective layer.

Optionally, the material of the first protective layer includes silicon oxide.

Optionally, the etching process includes a wet etching process or a plasma etching process.

Optionally, the process for removing the first dummy fin structure includes an etching process, and in the etching process, an etching selection ratio of a material of the first dummy fin structure to a material of the substrate is greater than 5: 1.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, the initial substrate comprises a plurality of invalid regions and an effective region surrounding the invalid regions, and the first fin structures which are mutually separated and are positioned in the effective region and the first dummy fin structures positioned in the invalid regions are formed, namely, the first dummy fin structures are connected with the first fin structures in the extension direction of the first fin structures, and after the first fin structures and the first dummy fin structures are formed, a plurality of first dummy fin structures are removed, so that the first fin structures on two sides of the invalid regions can be spaced by the first dummy fin structures in the extension direction of the first fin structures, and the first fin structures with shorter lengths are formed, thereby improving the integration level of the semiconductor structure. On the basis, a cutting layer is formed in the initial substrate of the invalid region before the first mask structure is formed, so that on the one hand, the influence of subsequent etching and cleaning processes on the cutting layer is reduced to improve the pattern precision of the cutting layer, and the influence of the precision of other subsequent patterning layers and the subsequent etching and cleaning processes on the alignment precision of a photoresist layer pattern for forming the cutting layer pattern is reduced, the size of a process window of the process for forming the cutting layer is increased, and the performance of the semiconductor structure is improved; in the second aspect, the first mask structure can be directly formed through one patterning layer, so that the first fin portion structure is formed through the first mask structure, the number of patterning layers for forming the first mask structure is reduced, and the patterning process for forming the first mask structure is simplified, so that the pattern precision of the first mask structure is improved, the pattern precision of the first fin portion structure is improved, and the performance of the semiconductor structure is improved; in a third aspect, the patterning process for forming the first mask structure is simplified, and the etching and cleaning times for a patterning layer for forming the first mask structure in the patterning process can be reduced, so that the residue pollution generated in the etching and cleaning processes is reduced, the defects of the semiconductor structure can be reduced, and the over-etching caused by the etching is also reduced, so that the downward transmission of the over-etching is reduced, further, the pattern precision of the first fin structure is improved, and the performance of the semiconductor structure is improved; in the fourth aspect, when removing a plurality of the first dummy fin structures, the material of the cutting layer, that is, the material of the first dummy fin structure, may be selected to increase the etching process for removing the first dummy fin structure, and the etching selectivity of the first fin portion structure material to the first dummy fin structure material may be reduced, so as to reduce the damage of the etching process to the surface of the first fin portion structure, to improve the pattern accuracy of the first fin portion structure, and to reduce the residue contamination of the first dummy fin structure during the etching process, so as to reduce the defects of the semiconductor structure, thereby improving the performance of the semiconductor structure.

Drawings

Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.

Fig. 4 to fig. 22 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As described in the background, the performance of semiconductor structures is still poor. The analysis will now be described with reference to specific examples.

It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 10 is provided, the substrate 10 includes a plurality of inactive areas I; forming a first mask material layer 20 on the surface of the substrate 10; forming an initial second mask layer 30 on the surface of the first mask material layer 20; forming a cutting material layer 50 on the surface of the initial second mask layer 30 and the surface of the first mask material layer 20; a photoresist layer 51 is formed on the surface of the dicing material layer 50, and the photoresist layer 51 exposes the surface of the dicing material layer 50 in the inactive area I.

The process of forming the initial second mask layer 30 includes a self-aligned multiple pattern forming process.

Referring to fig. 2, the photoresist layer 51 is used as a mask to etch the dicing material layer 50 and the initial second mask layer 30 until the surface of the first mask material layer 20 is exposed, so as to form a second mask layer 40 and a dicing layer (not shown); after the second mask layer 40 is formed, the dicing layer and the photoresist layer 51 are removed.

Referring to fig. 3, after removing the cutting layer and the photoresist layer 51, the second mask layer 40 is used as a mask to etch the first mask material layer 20 until the surface of the substrate 10 is exposed, so as to form a first mask layer 21; after the first mask layer 21 is formed, the substrate 10 is etched by taking the first mask layer 21 as a mask, so that a plurality of fin structures 11 which are mutually separated are formed on the substrate 10.

However, in the above method, the deviation of the etching process for forming the initial second mask layer 30 not only causes the pattern of the initial second mask layer 30 to be easily deviated, but also is affected by the deviation, the pattern accuracy of the photoresist layer 51 is also affected, and not only is the pattern accuracy of the photoresist layer 51 affected by the deviation of the pattern accuracy of the photoresist layer for forming the initial second mask layer 30, so on one hand, the pattern accuracy (including the overlay accuracy) of the photoresist layer 51 is poor, on the other hand, the photoresist layer 51 is formed with more restrictions, which results in a smaller process window for forming the photoresist layer 51, and thus, the pattern accuracy of the finally formed fin structure 11 is low, and the performance of the semiconductor structure is poor.

In addition, in the process of etching the cutting material layer 50 and the initial second mask layer 30 by using the photoresist layer 51 as a mask, the etching process is prone to over-etching the surface of the first mask material layer 20, which not only causes damage to the surface of the first mask material layer 20 and reduces the pattern precision of the first mask layer 21, but also is prone to downward transmission, which causes the pattern precision of the fin structure 11 to be affected, thereby causing poor performance of the semiconductor structure. Moreover, in the process of removing the dicing layer and the photoresist layer 51, in order to reduce the damage of the cleaning process to the second mask layer 40, the cleaning process has low intensity, and therefore, after the dicing layer and the photoresist layer 51 are removed, the surface of the first mask material layer 20 is easily contaminated by the residues of the dicing layer and the photoresist layer 51, thereby increasing the defects of the semiconductor structure, and leading to poor performance of the semiconductor structure. In summary, the performance of the semiconductor structure is still poor.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, in which a cutting layer is formed in an invalid region before a first fin structure is formed, and a plurality of first dummy fin structures are removed after the first fin structure and the first dummy fin structure are formed, so that performance of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 4 to fig. 22 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 4 and 5, fig. 4 is a schematic top view of a semiconductor structure according to an embodiment of the present invention, fig. 5 is a schematic cross-sectional view of fig. 4 along the direction X-X1, providing an initial substrate 100, wherein the initial substrate 100 includes a plurality of inactive areas B and an active area a surrounding the inactive areas B.

The material of the initial substrate 100 is a semiconductor material.

In this embodiment, the material of the initial substrate 100 is silicon.

In other embodiments, the material of the initial substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

Subsequently, a cutting layer is formed in the initial substrate 100 of the invalid region B, and the surface of the initial substrate 100 is exposed out of the surface of the cutting layer. Please refer to fig. 6 to 12 for a process of forming the cutting layer.

Referring to fig. 6 and 7, fig. 6 is a schematic top view based on fig. 4, fig. 7 is a schematic cross-sectional view taken along the direction X-X1 in fig. 6, wherein a second hard mask material layer 111 is formed on the surfaces of the active area a and the inactive area B; forming a second mask material layer 112 on the surface of the second hard mask material layer 111; a second photoresist layer 120 is formed on the surface of the second masking material layer 112, and the second photoresist layer 120 exposes the surface of the second masking material layer 112 in the inactive area B.

The second hard mask material layer 111 is used to provide material for a subsequent formation of a second hard mask layer.

The material of the second hard mask material layer 111 includes one or more of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon, or silicon nitride. Correspondingly, the material of the second hard mask layer comprises one or more of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon or silicon nitride.

The material of the second hard mask layer has higher hardness, so that the material of the second hard mask layer has smaller loss in the pattern transfer process, and the pattern precision is favorably improved in the pattern transfer process. In conclusion, the second hard mask layer can improve the pattern precision of the subsequently formed cutting layer.

The second mask material layer 112 is used to provide a material for forming a second mask layer, and is also used to increase an anti-reflection effect during a photolithography process for forming the second photoresist layer 120, thereby improving the pattern accuracy of the second photoresist layer 120.

In the present embodiment, the material of the second mask material layer 112 includes spin-on carbon. Correspondingly, the material of the second mask layer comprises spin-on carbon. Because the filling property and the fluidity of the spin-on carbon are better, the flatness of the second mask material layer 112 can be improved, which is beneficial to forming the second photoresist layer 120 with higher pattern precision, so as to improve the performance of the semiconductor structure.

In this embodiment, before forming the second photoresist layer 120, an anti-reflective layer 121 may be formed on the surface of the second masking material layer 112. Therefore, the anti-reflection layer 121 can increase the anti-reflection effect during the photolithography process for forming the second photoresist layer 120, thereby improving the pattern accuracy of the second photoresist layer 120.

The anti-reflection layer 121 includes: a thin silicon anti-reflective layer (Si-ARC), an organic material bottom anti-reflective layer (organic BARC), a dielectric anti-reflective layer (DARC), or a combination of an organic bottom anti-reflective layer and a dielectric anti-reflective layer.

It should be noted that, in this embodiment, since the anti-reflection layer 121 is formed on the surface of the second mask material layer 112 before the second photoresist layer 120 is formed, the fact that the second photoresist layer 120 exposes the surface of the second mask material layer 112 on the inactive area B means that the second photoresist layer 120 exposes the surface of the anti-reflection layer 121 on the inactive area B.

In other embodiments, the antireflective layer is not formed.

Referring to fig. 8 and 9, fig. 8 is a schematic top view structure view based on fig. 6, fig. 9 is a schematic cross-sectional view of fig. 8 in the direction of X-X1, and the second masking material layer 112 is etched by using the second photoresist layer 120 as a mask to form a second masking layer 114; after the second mask material layer 112 is etched, the second hard mask material layer 111 is continuously etched until the surface of the initial substrate 100 is exposed to form a second hard mask layer 113, and the second mask layer 114 is located on the surface of the second hard mask layer 113.

In this embodiment, the second hard mask layer 113 and the second mask layer 114 form a second mask structure 110, and the second mask structure 110 is located on the surface of the initial substrate 100 and exposes the surface of the initial substrate 100 in the inactive area B.

In this embodiment, the process of etching the second hard mask material layer 111 and the second mask material layer 112 includes a dry etching process or a wet etching process.

In this embodiment, after the second mask structure 110 is formed, the anti-reflection layer 121 and the second photoresist layer 120 are removed.

Referring to fig. 10 and 11, fig. 10 is a schematic top view structure view based on fig. 8, fig. 11 is a schematic cross-sectional structure view of fig. 10 in the X-X1 direction, and the initial substrate 100 is etched by using the second mask structure 110 as a mask to form the first opening 103 in the inactive area B.

In this embodiment, the etching process for forming the first opening 103 has an etching selection ratio of the material of the initial substrate 100 to the material of the second mask layer 114 of 5:1 or more.

The etching process for forming the first opening 103 includes a dry etching process or a wet etching process.

In this embodiment, the etching process for forming the first opening 103 is a dry etching process, and the gas used in the dry etching process includes C_xF_y、C_xH_yF_z、C_xH_yH2, O2, SO2, COS, He, Ar and N₂One or a combination of more of the same.

In this embodiment, after the first opening 103 is formed, the second mask structure 110 is removed.

Referring to fig. 12, fig. 12 is a schematic top view along the same direction as fig. 10, and a cutting layer 130 is formed in the first opening 103.

The cutting layer 130 is used to subsequently provide material for forming the first dummy fin structure.

In this embodiment, the method for forming the cutting layer 130 in the first opening 103 includes: forming a layer of dicing material (not shown) within the initial substrate 100 surface and the first opening 103; the dicing material layer is planarized until the initial substrate 100 surface is exposed.

In this embodiment, the process of forming the dicing material layer includes: one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or an epitaxial growth process.

In the present embodiment, the material of the cutting layer 130 includes one or more of silicon nitride, silicon oxide, silicon germanium and silicon phosphide.

In this embodiment, the method for planarizing the cut material layer includes: a chemical mechanical flat grinding process, a wet etching process or a dry etching process.

In other embodiments, the method of forming the cutting layer further comprisesThe method comprises the following steps: after a second mask structure is formed, an ion doping process is carried out on the initial substrate of the invalid region by taking the second mask structure as a mask, the ion doping process comprises an ion implantation process, and the process parameters of the ion implantation process comprise: the dose range of implantation is 1.0e16atom/cm³～1.0e20atom/cm³(ii) a The implantation energy is in the range of 10KeV to 200 KeV.

On one hand, in the etching process of subsequently removing the cutting layer, the etching selection ratio of the etching process to the cutting layer and the initial substrate can be increased through the ion doping process; on the other hand, since the cutting layer is directly formed in the initial substrate by adopting the ion doping process, the steps of forming the cutting layer are reduced, namely, the steps of forming an opening in the initial substrate before forming the cutting layer and flattening the cutting material layer after forming the cutting material layer in the opening and on the surface of the initial substrate are not needed. Thus, the time and complexity of the semiconductor process is reduced.

Subsequently, a plurality of first mask structures are formed on the surfaces of the inactive area B and the active area a, and at least 1 first mask structure crosses the cutting layer 130. In this embodiment, the process of forming a plurality of the first mask structures includes a multiple self-aligned patterning process. Please refer to fig. 13 to fig. 18 for a process of forming the first mask structure.

Referring to fig. 13 and 14, fig. 13 is a schematic top view of the structure of fig. 12, and fig. 14 is a schematic cross-sectional view of fig. 13 along the direction X-X1, wherein a first mask material layer 140 is formed on the surface of the initial substrate 100 in the active area a and the surface of the dicing layer 130 in the inactive area B; forming a first core mold material layer 150 on the surface of the first mask material layer 140; after the first core mold material layer 150 is formed, a plurality of second core mold structures 160 which are separated from each other are formed on the surface of the first core mold material layer 150; second side walls 161 are formed on the side wall surfaces of the plurality of second mandrel structures 160 that are discrete from each other.

The first masking material layer 140 provides material for subsequent formation of a first masking structure.

In the present embodiment, the process of forming the first mask material layer 140 includes a chemical vapor deposition process, an epitaxial growth process, or an atomic layer deposition process.

In the present embodiment, the material of the first mask material layer 140 includes one or more of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon nitride. Correspondingly, the material of the first mask structure comprises one or more of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon nitride.

The first mandrel material layer 150 provides material for the subsequent formation of a first mandrel structure.

In this embodiment, the process of forming the first mandrel material layer 150 includes a chemical vapor deposition process, an epitaxial growth process, or an atomic layer deposition process.

In this embodiment, the material of the first mandrel material layer 150 includes one or more of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon, and photoresist. Correspondingly, the material of the first core mold structure comprises one or more of amorphous silicon, silicon nitride, silicon oxide, amorphous carbon and photoresist.

In this embodiment, the method of forming the second mandrel structure 160 includes: forming a second core mold material layer (not shown) on the surface of the first core mold material layer 150; forming a second core mold light resistance layer on the surface of the second core mold material layer, wherein the second core mold light resistance layer exposes out of part of the surface of the second core mold material layer; and etching the second mandrel material layer by using the second mandrel light resistance layer as a mask until the surface of the first mandrel material layer 150 is exposed.

In this embodiment, the process of forming the second mandrel material layer includes a chemical vapor deposition process, an epitaxial growth process, or an atomic layer deposition process.

In this embodiment, the process of etching the second mandrel material layer includes a wet etching process or a dry etching process.

In this embodiment, after the second mandrel structure 160 is formed, the second mandrel light blocking layer is removed.

In this embodiment, the method for forming the second sidewall 161 includes: after the second mandrel structure 160 is formed, a second layer of sidewall material (not shown) is formed on the exposed surface of the first layer of mandrel material 150, as well as on the surface of the second mandrel structure 160; the second sidewall material layer is etched back until the top surface of the second mandrel structure 160 and the surface of the first mandrel material layer 150 are exposed.

In this embodiment, the process of forming the second sidewall material layer includes a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, the process of etching back the second sidewall material layer includes an anisotropic plasma etching process.

In other embodiments, the process of forming the second mandrel structure comprises a multiple self-aligned patterning process.

In this embodiment, the second core form 160 is removed after the second side walls 161 are formed.

In this embodiment, before forming the first mask material layer 140, a first protection material layer 105 is formed on the surface of the initial substrate 100 in the active area a and the surface of the cutting layer 130 in the inactive area B.

Since the first protective material layer 105 is formed before the first mask material layer 140 is formed, the first protective material layer 105 can protect the initial substrate 100 and the dicing layer 130, and damage to the initial substrate 100 and the dicing layer 130 due to subsequent processes is reduced.

The first protective material layer 105 is used to provide a material for subsequently forming a first protective layer.

In this embodiment, the material of the first protection material layer 105 includes silicon oxide. Correspondingly, the material of the first protective layer comprises silicon oxide.

Since the first protective layer is made of silicon oxide, the filling property and the adhesion property of silicon oxide are better, on one hand, the first protective layer can increase the adhesion property between the initial substrate 100 and the dicing layer 130 and the first mask material layer 140; on the other hand, the interface state of the initial substrate 100 and the cutting layer 130 can be improved by the first protective layer. Thereby improving the performance of the semiconductor structure.

The process of forming the first protective material layer 105 includes a thermal oxidation process or a deposition process.

In this embodiment, the process of forming the first protective material layer 105 is a thermal oxidation process.

Referring to fig. 15, fig. 15 is a schematic cross-sectional structure view along the same direction as fig. 14, the first core mold material layer 150 is etched by using the second sidewalls 161 as a mask until the surface of the first mask material layer 140 is exposed, so as to form a plurality of mutually discrete first core mold structures 151 on the surface of the first mask material layer 140.

In other embodiments, the second mandrel structure and second sidewall are not formed. The method of forming the first core mold structure comprises: after the first core mold material layer is formed, forming a first light resistance layer on the surface of the first core mold material layer, wherein part of the surface of the first core mold material layer is exposed out of the first light resistance layer; and etching the first mandrel material layer by taking the first photoresist layer as a mask until the surface of the first mask material layer is exposed. Thus, a plurality of first core mold structures which are separated from each other are formed on the surface of the first mask material layer.

In this embodiment, the process of etching the first mandrel material layer 150 includes a dry etching process or a wet etching process.

Referring to fig. 16, fig. 16 is a schematic cross-sectional view taken along the same direction as fig. 15, wherein first sidewalls 152 are formed on the sidewall surfaces of each of the first core structures 151, and at least 1 of the first sidewalls 152 cross over the inactive area B.

In this embodiment, the method for forming the first sidewall spacers 152 includes: forming a first sidewall material layer (not shown) on the surface of the first mask material layer 140 and the surface of the first core mold structure 151; the first sidewall material layer is etched back until the surface of the first mask material layer 140 and the top surface of the first core mold structure 151 are exposed.

In this embodiment, the process of forming the first sidewall material layer includes a chemical vapor deposition process or an atomic layer deposition process.

In this embodiment, the process of etching back the first sidewall material layer includes an anisotropic plasma etching process.

In this embodiment, the material of the first sidewall material layer includes one or more of silicon oxide, silicon nitride, silicon and titanium oxide. Accordingly, the first sidewall 152 material comprises a combination of one or more of silicon oxide, silicon nitride, silicon and titanium oxide.

In this embodiment, after the first sidewall 152 is formed, the first core structure 151 is removed.

Referring to fig. 17 and 18, fig. 17 is a schematic top view structure view along the same direction as fig. 13, fig. 18 is a schematic cross-sectional structure view along the direction X-X1 in fig. 17, the first sidewall 152 is used as a mask to etch the first mask material layer 140 until the surface of the cutting layer 130 and the surface of the initial substrate 100 are exposed, so as to form a plurality of first mask structures 141 on the surface of the inactive area B and the surface of the active area a, and at least 1 first mask structure 141 crosses the cutting layer 130.

The first mask structure 141 is used as a mask for forming the first fin structure.

Accordingly, the pattern transferred downward by the first mask structure 141 across the inactive region B can be disconnected later by removing the first dummy fin structure.

Since the cutting layer 130 is formed in the initial substrate 100 of the invalid region B before the first mask structure 141 is formed, on one hand, the influence of the subsequent etching and cleaning processes on the cutting layer 130 is reduced to improve the pattern precision of the cutting layer 130, and the influence of the precision of the subsequent other patterning layers and the subsequent etching and cleaning processes on the overlay precision of the pattern of the second photoresist layer 120 for forming the pattern of the cutting layer 130 is reduced, so that the size of a process window of the process for forming the cutting layer 130 is increased, thereby improving the performance of the semiconductor structure. On the other hand, the first mask structure 141 can be directly formed through one patterning layer (the first core mold structure 151) to form the first fin structure, so that the number of patterning layers for forming the first mask structure 141 is reduced, and the patterning process for forming the first mask structure 141 is simplified, thereby improving the pattern precision of the first mask structure 141, improving the pattern precision of the first fin structure, and further improving the performance of the semiconductor structure. Meanwhile, the patterning process for forming the first mask structure 141 is simplified, and the etching and cleaning times for the patterning layer forming the first mask structure 141 in the patterning process can be reduced, so that the residue pollution generated in the etching and cleaning processes is reduced, the defects of the semiconductor structure can be reduced, and the over-etching caused by the etching is reduced, so that the downward transmission of the over-etching is reduced, further, the pattern precision of the first fin structure is improved, and the performance of the semiconductor structure is improved.

In this embodiment, since the first protective material layer 105 is formed on the surfaces of the initial substrate 100 in the active area a and the dicing layer 130 in the inactive area B before the first masking material layer 140 is formed, etching the first masking material layer 140 until the surfaces of the dicing layer 130 and the initial substrate 100 are exposed means etching the first masking material layer 140 until the surfaces of the dicing layer 130 and the first protective material layer 105 on the surface of the initial substrate 100 are exposed.

In this embodiment, the process of etching the first mask material layer 140 includes a wet etching process or a dry etching process.

In this embodiment, after etching the first mask material layer 140, the first protection material layer 105 is continuously etched until the surface of the cutting layer 130 and the surface of the initial substrate 100 are exposed, so as to form the first protection layer 106.

In this embodiment, the process of etching the first protective material layer 105 includes a wet etching process or a dry etching process.

In the present embodiment, after the first mask structure 141 is formed, the first sidewall 152 is removed.

Referring to fig. 19 and 20, fig. 19 is a schematic top view structure view based on fig. 17, fig. 20 is a schematic cross-sectional structure view along the direction X-X1 in fig. 19, the cutting layer 130 and the initial substrate 100 are etched by using the first mask structure 141 as a mask until a substrate 101, a plurality of first fin structures 102 located on the substrate 101, and a plurality of first dummy fin structures 131 located on the substrate 101 are formed, the first fin structures 102 are separated from each other and located in the active area a, and the first dummy fin structures 131 are located in the inactive area B.

The process of etching the cutting layer 130 and the initial substrate 100 includes a dry etching process or a wet etching process.

In this embodiment, the process of etching the cutting layer 130 and the initial substrate 100 is a plasma etching process, and the gases used in the plasma etching process include: c_xF_y、C_xH_yF_z、C_xH_y、H₂、Cl₂HBr, Ar, and He.

In this embodiment, in the etching process for etching the cutting layer 130 and the initial substrate 100, the etching selection ratio of the material of the cutting layer 130 to the material of the first mask structure 141 is greater than 3: 1.

In this embodiment, after the first fin structure 102 and the first dummy fin structure 131 are formed, the first mask structure 141 is removed.

Referring to fig. 21 and 22, fig. 21 is a schematic top view of fig. 19, and fig. 22 is a schematic cross-sectional view taken along the direction X-X1 in fig. 21, wherein after the first fin structure 102 and the first dummy fin structures 131 are formed, some of the first dummy fin structures 131 are removed.

Since the initial substrate 100 includes the plurality of inactive areas B and the active area a surrounding the inactive areas B, and the first fin structures 102 separated from each other and located in the active area a and the first dummy fin structures 131 located in the inactive areas B are formed, that is, since the first dummy fin structures 131 are connected to the first fin structures 102 in the extending direction of the first fin structures 102 and the plurality of first dummy fin structures 131 are removed after the first fin structures 102 and the first dummy fin structures 131 are formed, the first fin structures 102 on both sides of the inactive areas B can be spaced apart by the first dummy fin structures 131 in the extending direction of the first fin structures 102, so that the first fin structures 102 with shorter lengths are formed, thereby improving the integration of the semiconductor structure.

Moreover, when removing a plurality of the first dummy fin structures 131, the material of the cutting layer 130, that is, the material of the first dummy fin structure 131, may be selected to increase the etching process for removing the first dummy fin structures 131, and the etching selectivity of the material of the first fin portion structure 102 and the material of the first dummy fin structure 131 may be compared to each other, so as to reduce the damage of the etching process to the surface of the first fin portion structure 102, so as to improve the pattern accuracy of the first fin portion structure 102, and reduce the residue contamination of the first dummy fin structure 102 during the etching process, so as to reduce the defects of the semiconductor structure, thereby improving the performance of the semiconductor structure.

In this embodiment, the process of removing the first dummy fin structure 131 includes an etching process, and the etching process includes a wet etching process or a plasma etching process.

In this embodiment, in the etching process for removing the first dummy fin structure 131, an etching selection ratio of the material of the first dummy fin structure 131 to the material of the substrate 101 is greater than or equal to 5: 1.

In this embodiment, after removing the first dummy fin structure 131, a dielectric layer 170 is formed on the surface of the substrate 101.

The dielectric layer 170 serves to electrically insulate the semiconductor devices from each other.

In this embodiment, the method of forming the dielectric layer 170 includes: forming a dielectric material layer (not shown) on the surface of the substrate 101 and the surface of the first fin structure 102; the dielectric material layer is etched back until a portion of the sidewall surface of the first fin structure 102 is exposed.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.