阅读说明：本技术 半导体元件及其制作方法 (Semiconductor element and manufacturing method thereof ) 是由 朱猛剀 于 2016-12-15 设计创作，主要内容包括：本发明公开一种半导体元件及其制作方法。该制作半导体元件的方法,包括：首先提供一基底,该基底包含一第一半导体层、一绝缘层以及一第二半导体层,然后形成一主动元件于基底上,形成一层间介电层于基底及主动元件上,形成一掩模层于层间介电层上,去除部分掩模层、部分层间介电层以及部分绝缘层以形成一第一接触洞。接着形成一图案化掩模于掩模层上并填满第一接触洞,再去除部分掩模层及部分层间介电层以形成一第二接触洞暴露部分主动元件。(The invention discloses a semiconductor element and a manufacturing method thereof. The method for manufacturing the semiconductor element comprises the following steps: firstly, a substrate is provided, the substrate comprises a first semiconductor layer, an insulating layer and a second semiconductor layer, then an active element is formed on the substrate, an interlayer dielectric layer is formed on the substrate and the active element, a mask layer is formed on the interlayer dielectric layer, and a part of the mask layer, a part of the interlayer dielectric layer and a part of the insulating layer are removed to form a first contact hole. Then, a patterned mask is formed on the mask layer and fills the first contact hole, and then a part of the mask layer and a part of the interlayer dielectric layer are removed to form a second contact hole exposing a part of the active device.)

1. A method of fabricating a semiconductor device, comprising:

providing a substrate, wherein the substrate comprises a first semiconductor layer, an insulating layer and a second semiconductor layer;

forming an active device on the substrate;

forming an interlayer dielectric layer on the substrate and the active device;

forming a mask layer on the interlayer dielectric layer;

removing part of the mask layer, part of the interlayer dielectric layer and part of the insulating layer to form a first contact hole;

forming a patterned mask on the mask layer and filling the first contact hole; and

removing part of the mask layer and part of the interlayer dielectric layer to form a second contact hole exposing part of the active element.

2. The method of claim 1, wherein the active device comprises:

the grid structure is arranged on the second semiconductor layer; and

the source/drain regions are disposed on both sides of the gate structure and in the second semiconductor layer.

3. The method of claim 2, further comprising forming a shallow trench isolation surrounding said source/drain region.

4. The method of claim 3, further comprising removing a portion of said mask layer, a portion of said interlayer dielectric layer, a portion of said shallow trench isolation and a portion of said insulating layer to form said first contact hole.

5. The method of claim 3, further comprising:

forming a contact hole etching stop layer on the second semiconductor layer and the grid structure;

forming the interlayer dielectric layer on the contact hole etching stop layer;

forming the mask layer on the interlayer dielectric layer; and

removing part of the mask layer, part of the interlayer dielectric layer, part of the contact hole etching stop layer, part of the shallow trench isolation and part of the insulating layer to form the first contact hole.

6. The method of claim 3, further comprising:

forming a contact hole etching stop layer on the second semiconductor layer and the grid structure;

removing part of the contact hole etching stop layer;

forming the interlayer dielectric layer on the contact hole etching stop layer and contacting the contact hole etching stop layer and the shallow trench isolation;

forming the mask layer on the interlayer dielectric layer; and

removing part of the mask layer, part of the interlayer dielectric layer, part of the shallow trench isolation and part of the insulating layer to form the first contact hole.

7. The method of claim 1, further comprising:

carrying out a first etching manufacturing process and using the patterned mask as a mask to remove part of the mask layer and the patterned mask at the same time; and

a second etching process is performed to remove a portion of the interlayer dielectric layer to form the second contact hole and simultaneously enlarge the first contact hole in the interlayer dielectric layer.

8. The method of claim 1, further comprising:

forming a conductive layer in the first contact hole and the second contact hole; and

removing part of the conductive layer to form a first contact plug in the interlayer dielectric layer and the substrate and a second contact plug in the interlayer dielectric layer, wherein the first contact plug has a first part arranged in the insulating layer and the second semiconductor layer and a second part arranged in the interlayer dielectric layer.

9. The method of claim 8, wherein the width of the second portion is greater than the width of the first portion.

10. The method of claim 8, wherein the width of the first portion is greater than the width of the second contact plug.

11. The method of claim 1, wherein the masking layer comprises:

an amorphous carbon film; and

a dielectric anti-reflection layer is disposed on the amorphous carbon film.

12. The method of claim 1, further comprising removing a sidewall portion of the mask layer after removing a portion of the mask layer, a portion of the interlayer dielectric layer, and a portion of the insulating layer to form the first contact hole.

13. A semiconductor device, comprising:

a substrate including a first semiconductor layer, an insulating layer, and a second semiconductor layer;

an active device disposed on the substrate;

an interlayer dielectric layer disposed on the active device;

a first contact plug disposed beside the active device, the first contact plug comprising:

a first portion disposed within the insulating layer and the second semiconductor layer; and

a second portion disposed within the interlayer dielectric layer, the second portion having a width greater than a width of the first portion; and

the second contact plug is arranged in the interlayer dielectric layer and electrically connected with the active element.

14. The semiconductor device of claim 13, wherein said active device comprises:

a gate structure disposed on the second semiconductor layer; and

and the source/drain regions are arranged on two sides of the grid structure and in the second semiconductor layer.

15. The semiconductor device as defined in claim 14, further comprising shallow trench isolation surrounding said source/drain region.

16. The semiconductor device as claimed in claim 14, further comprising a contact hole etch stop layer disposed on the gate structure and the substrate, wherein the contact hole etch stop layer directly contacts the first portion of the first contact plug.

17. The semiconductor device as claimed in claim 14, further comprising a contact hole etch stop layer disposed on the gate structure and the substrate, wherein the contact hole etch stop layer does not contact the first portion of the first contact plug.

18. The semiconductor device as claimed in claim 13, wherein the width of the first portion is greater than the width of the second contact plug.

19. The semiconductor device as claimed in claim 13, wherein the width of the second portion is greater than the width of the second contact plug.

20. The semiconductor device as claimed in claim 13, wherein the upper surface of the second portion is aligned with the upper surface of the second contact plug.

Technical Field

The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a contact plug penetrating through a silicon-on-insulator (SOI) substrate and a contact plug penetrating through an interlayer dielectric (ILD) layer to connect an active device.

Background

In the fabrication of semiconductor devices, the placement of devices on a silicon-on-insulator (SOI) substrate or wafer generally results in better isolation within an integrated circuit than devices placed on a conventional silicon wafer (bulk silicon). The silicon-on-insulator substrate is typically fabricated by sandwiching a thin oxide layer or other insulating layer between silicon wafers, with the fabricated device disposed on the silicon layer above the thin oxide layer. The insulation effect provided by the semiconductor element prepared on the basis of the silicon-coated insulating substrate can eliminate latch-up (latch-up) possibly generated in a Complementary Metal Oxide Semiconductor (CMOS) transistor element and can reduce the generation of parasitic capacitance (parasitic capacitance).

At present, at least two contact plugs with different sizes are required to be formed in the process of manufacturing an active device such as a metal oxide semiconductor transistor on a silicon-on-insulator substrate, including a contact plug for connecting the active device and a back side contact plug penetrating the silicon-on-insulator substrate and connecting another silicon wafer. However, the above two methods for forming the contact plug have their drawbacks, and therefore, it is an important issue to provide a simple and low-cost method.

Disclosure of Invention

The preferred embodiment of the invention discloses a method for manufacturing a semiconductor element. Firstly, a substrate is provided, the substrate comprises a first semiconductor layer, an insulating layer and a second semiconductor layer, then an active element is formed on the substrate, an interlayer dielectric layer is formed on the substrate and the active element, a mask layer is formed on the interlayer dielectric layer, and a part of the mask layer, a part of the interlayer dielectric layer and a part of the insulating layer are removed to form a first contact hole. Then, a patterned mask is formed on the mask layer and fills the first contact hole, and then a part of the mask layer and a part of the interlayer dielectric layer are removed to form a second contact hole exposing a part of the active device.

Another embodiment of the present invention discloses a semiconductor device, which mainly comprises: a substrate comprises a first semiconductor layer, an insulating layer and a second semiconductor layer, an active device disposed on the substrate, an interlayer dielectric layer disposed on the active device, a first contact plug disposed beside the active device, and a second contact plug disposed in the interlayer dielectric layer and electrically connected to the active device. The first contact plug comprises a first part arranged in the insulating layer and the second semiconductor layer and a second part arranged in the interlayer dielectric layer, and the width of the second part is larger than that of the first part.

Drawings

FIG. 1 is a schematic diagram of a method for fabricating a semiconductor device according to a preferred embodiment of the present invention;

FIG. 2 is a schematic diagram of a method of fabricating a semiconductor device according to FIG. 1;

FIG. 3 is a schematic diagram of a method of fabricating a semiconductor device according to FIG. 2;

FIG. 4 is a schematic diagram of a method of fabricating a semiconductor device according to FIG. 3;

FIG. 5 is a schematic diagram of a method of fabricating a semiconductor device according to FIG. 4;

FIG. 6 is a schematic diagram of a method of fabricating a semiconductor device according to FIG. 5;

fig. 7 is a schematic structural diagram of a semiconductor device according to a preferred embodiment of the invention.

Description of the main elements

12 a first region of a substrate 14

16 second region 18 first semiconductor layer

20 insulating layer 22 second semiconductor layer

24 shallow trench isolation 26 active device

28 gate structure 30 spacer

32 spacer 34 lightly doped drain

36 source/drain regions 38 metal silicide layer

40 gate dielectric layer 42 gate material layer

44 contact hole etch stop 46 interlevel dielectric layer

48 mask layer 50 patterned photoresist

52 amorphous carbon film 54 dielectric antireflective layer

56 opening 58 first contact hole

60 patterning the mask 62 second contact hole

64 second contact hole 66 conductive layer

68 first contact plug 70 second contact plug

72 first portion 74 second portion

Detailed Description

Referring to fig. 1 to 5, fig. 1 to 5 are schematic diagrams illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the invention. As shown in fig. 1, a substrate 12 is first provided, and a first region 14 and a second region 16 are preferably defined on the substrate 12, wherein the first region 14 is preferably used for preparing active devices such as mos transistors, and the second region 16 is used for forming back side contact plugs (backsides) that penetrate through the entire substrate 12 and connect to another substrate or semiconductor chip through the back side of the substrate.

In the present embodiment, the substrate 12 is preferably a silicon-on-insulator (SOI) substrate, which mainly includes a first semiconductor layer 18, an insulating layer 20 disposed on the first semiconductor layer 18, and a second semiconductor layer 22 disposed on the insulating layer 20. More specifically, the first semiconductorThe layer 18 and the second semiconductor layer 22 may comprise the same or different materials and may be selected from the group consisting of silicon, germanium, and silicon germanium, respectively, and the insulating layer 20 disposed between the first semiconductor layer 18 and the second semiconductor layer 22 preferably comprises silicon dioxide (SiO)₂) But is not limited thereto. It should be noted that although the present embodiment preferably uses a silicon-on-insulator substrate as the substrate of the semiconductor device, according to other embodiments of the present invention, the substrate 12 may be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, etc., and these material choices are also within the scope of the present invention.

A portion of the second semiconductor layer 22 may then be removed to form a Shallow Trench Isolation (STI) 24 surrounding the second semiconductor layer 22, wherein the second semiconductor layer 22 surrounded by the STI 24 is preferably used to provide an active device.

An active device 26 is then formed on the substrate 12. In the present embodiment, the fabricated active device 26 is preferably a metal oxide semiconductor transistor, which mainly comprises a gate structure 28, a spacer 30 and a spacer 32 disposed on the sidewall of the gate structure 28, a lightly doped drain 34 disposed in the second semiconductor layer 22 at both sides of the spacer 28, a source/drain region 36 disposed in the second semiconductor layer 22 at both sides of the spacer 32, an optional epitaxial layer (not shown) disposed in the second semiconductor layer 22 at both sides of the spacer 32, and an optional silicide layer 38 disposed on the surface of the source/drain region 36 and on the top of the gate structure 28.

In the present embodiment, the gate structure 28 further includes a gate dielectric layer 40 and a gate material layer 42 or gate electrode disposed on the gate dielectric layer 40, wherein the gate dielectric layer 22 may include silicon dioxide, silicon nitride or a high dielectric constant (high-k) material, and the gate material layer 24 may include a conductive material such as a metal material, polysilicon or metal silicide (silicide).

The spacers 30 and 32 are each a single spacer selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, but not limited thereto. In addition, according to an embodiment of the present invention, each of the spacers 30 and 32 may be a composite spacer according to the manufacturing process requirements, for example, the composite spacer may further include a first sub-spacer (not shown) and a second sub-spacer (not shown), one of the first sub-spacer and the second sub-spacer may have an L-shape or an I-shape in cross section, the first sub-spacer and the second sub-spacer may comprise the same or different materials, and both of the first sub-spacer and the second sub-spacer may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide nitride, which are all within the scope of the present invention.

A Contact Etch Stop Layer (CESL) 44 of silicon nitride is then formed on the substrate 12 covering the gate structure 28 and an interlayer dielectric layer 46 on the CESL 44. Then, a mask layer 48 and a patterned photoresist 50 are sequentially formed on the interlayer dielectric layer 46, wherein the mask layer 48 preferably includes an amorphous carbon film (APF) 52 and a dielectric antireflective coating (DARC) 54 disposed on the amorphous carbon film 52, and the patterned photoresist 50 has an opening 56 exposing a portion of the surface of the dielectric antireflective coating 54 of the second region 16.

As shown in FIG. 2, an etching process is then performed using the patterned photoresist 50 as a mask to remove a portion of the dielectric ARC layer 54, a portion of the amorphous carbon film 52, a portion of the interlayer dielectric 46, a portion of the contact hole etch stop layer 44, a portion of the shallow trench isolation 24, and a portion of the insulating layer 20 in the second region 16 to form a first contact hole 58, wherein the first contact hole 58 is preferably formed to expose the surface of the first semiconductor layer 18. In the present embodiment, the etching gas used to form the first contact hole 58 may be selected from the group consisting of octafluorocyclobutane (C)₄F₈) Argon (Ar), and oxygen, but not limited thereto.

Subsequently, as shown in fig. 3, the patterned photoresist 50 is stripped with oxygen, and a portion of the sidewall of the mask layer 48, particularly a portion of the dielectric anti-reflection layer 54 and a portion of the amorphous carbon film 52 located in the second region 16 adjacent to the first contact hole 58, is removed simultaneously while the patterned photoresist 50 is removed, thereby enlarging the first contact hole 58 located in the dielectric anti-reflection layer 54 and the amorphous carbon film 52. In other words, the first contact hole 58 in the second region 16 preferably has two widths, wherein the width of the first contact hole 58 in the ARC 54 and the amorphous carbon film 52 is preferably greater than the width of the first contact hole 58 in the ILD 46, the contact hole etch stop layer 44, the STI 24, and the insulating layer 20.

Then, a patterned mask 60 is formed on the mask layer 48 and fills the first contact hole 58, wherein the patterned mask 60 filled in the first contact hole 58 preferably fills the first contact hole 58 with a smaller width in the interlayer dielectric layer 46, the contact hole etch stop layer 44, the shallow trench isolation 24 and the insulating layer 20 but does not fill the first contact hole 58 with a larger width in the dielectric anti-reflective layer 54 and the amorphous carbon film 52. In the present embodiment, the patterned mask 60 is preferably a patterned photoresist, but is not limited thereto.

Then, as shown in FIG. 4, a first etching process is performed using the patterned mask 60 as a mask to remove a portion of the mask layer 48, particularly a portion of the dielectric antireflection layer 54 and a portion of the amorphous carbon film 52 in the first region 14 and expose a portion of the surface of the interlayer dielectric layer 46. In other words, the first etching process preferably transfers the pattern of the patterned mask 60 onto the mask layer 48 to form a plurality of second contact holes 62 in the mask layer 48. It is noted that most of the patterned mask 60 in the process of removing part of the dielectric antireflection layer 54 and part of the amorphous carbon film 52 in the present embodiment is removed or even completely consumed by the etching gas and exposes the underlying material layers, including the dielectric antireflection layer 54 in the first region 14 and the interlayer dielectric layer 46 in the second region 16. Therefore, after forming second contact hole 62 in dielectric antireflective layer 54 and amorphous carbon film 52, most of patterned mask 60 is removed and exposes the top surface and sidewalls of mask layer 48 in first region 14 and first contact hole 58 in second region 16.

Next, as shown in fig. 5, a second etching process is performed using the dielectric anti-reflective layer 54 as a mask to transfer the pattern of the second contact hole 62 formed in the dielectric anti-reflective layer 54 and the amorphous carbon film 52 into the interlayer dielectric layer 46 and the contact hole etch stop layer 44, so as to form a second contact hole 64 in the interlayer dielectric layer 46 and the contact hole etch stop layer 44 of the first region 14 to expose the gate structure 28 and the source/drain regions 36 of the active device 26. It is noted that since the second etching process is performed on the second region 16 without any patterned mask 60, the second contact hole 64 is preferably formed in the first region 14 by removing a portion of the second region 16 of the interlayer dielectric 46 to enlarge the first contact hole 58 in the interlayer dielectric 46 and expose a portion of the upper surface of the contact hole etch stop layer 44. The remaining patterned mask 60, dielectric antireflective layer 54, and amorphous carbon film 52 may then be removed by oxygen plasma treatment to completely expose the top surface of interlayer dielectric layer 46.

Then, as shown in fig. 6, a contact plug process is performed, for example, a conductive layer 66 may be formed in the first contact hole 58 and the second contact hole 64, wherein the conductive layer 66 may include a barrier layer (not shown) and a metal layer (not shown). A planarization process, such as a chemical mechanical polishing process, is then used to remove a portion of the metal layer, a portion of the barrier layer, or even a portion of the interlayer dielectric 46, so as to form a first contact plug 68 in the interlayer dielectric 46 and the substrate 12 in the second region 16 and a second contact plug 70 in the interlayer dielectric 46 in the first region 14 to electrically connect the gate structure 28 and the source/drain region 36, wherein the first contact plug 68 has a first portion 72 disposed in the insulating layer 20 and the shallow trench isolation 24 and a second portion 74 disposed in the interlayer dielectric 46. In the present embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride and tungsten nitride, and the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum and copper, but not limited thereto.

Then, a post-stage process can be performed according to the process requirements, for example, a metal interconnect process can be performed to form a plurality of inter-metal dielectric layers and metal wires embedded therein on the inter-layer dielectric layers, the first semiconductor layer 18 of the substrate 12 is completely removed to expose the bottom of the insulating layer 20 and the bottom of the first contact plug 68, and then another fabricated substrate or semiconductor wafer is bonded to the bottom of the insulating layer 20 and the two substrates are connected through the first contact plug 68. Thus, a semiconductor device according to the preferred embodiment of the present invention is manufactured.

In addition, according to an embodiment of the present invention, the portion of the second region 16 used for forming the backside contact plug (TSV) through the entire substrate 12 in the above-described embodiment may be slightly modified and applied to the formation of the through-silicon via (TSV). For example, the present invention can form the first contact hole 58 in fig. 2 by extending the first contact hole 58 down into a portion of the first semiconductor layer 18 without penetrating the first semiconductor layer 18, then before the manufacturing process of fig. 3 to 6 fills the conductive layer with the first contact hole 58 and then removes only a portion of the first semiconductor layer 18 by planarization until the bottom of the first contact plug 68 is exposed. In terms of the final structure, the first portion 72 of the bottom of the portion of the first contact plug 68 is preferably embedded in the first semiconductor layer 18 rather than being cut off from the bottom of the insulating layer 20 as in the previous embodiment, which is also within the scope of the present invention.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a semiconductor device according to a preferred embodiment of the invention. As shown in fig. 6, the semiconductor device mainly includes a substrate 12, a first region 14 and a second region 16 defined on the substrate 12, an active device 26 disposed on the substrate 12, an interlayer dielectric 46 disposed on the active device 26, a first contact plug 68 disposed in the interlayer dielectric 46 and the substrate 12 of the second region 16, and a second contact plug 70 disposed in the interlayer dielectric 46 of the first region 14 and electrically connected to the active device 26.

The substrate 12 is preferably a silicon-on-insulator substrate and includes a first semiconductor layer 18, an insulator layer 20, and a second semiconductor layer 22, the active device 26 includes a gate structure 28 disposed on the second semiconductor layer 22 and a source/drain region 36 disposed in the second semiconductor layer 22 on both sides of the gate structure 28.

In detail, the first contact plug 68 includes a first portion 72 disposed in the insulating layer 20 and the second semiconductor layer 22 or the shallow trench isolation 24 and a second portion 74 disposed in the interlayer dielectric layer 46, wherein the width of the second portion 74 is preferably greater than the width of the first portion 72, the width of the first portion 72 is preferably greater than the width of the second contact plug 70, the width of the second portion 74 is greater than the width of the second contact plug 70, and the upper surface of the second portion 74 is flush with the upper surfaces of the second contact plug 70 and the interlayer dielectric layer 46.

In addition, a contact hole etch stop layer 44 is formed on the substrate 12 and the gate structure 28, wherein the sidewall of the contact hole etch stop layer 44 directly contacts the first portion 72 of the first contact plug 68 and the sidewall of the contact hole etch stop layer 44 is preferably aligned with the sidewall of the shallow trench isolation 24, the insulating layer 20 and the first semiconductor layer 18. According to one embodiment of the present invention, the distance from the top surface of the shallow trench isolation 24 or the second semiconductor layer 22 to the top surface of the interlayer dielectric layer 46 is about 2000 angstroms to about 3000 angstroms, and the distance from the top surface of the insulating layer 20 to the top surface of the interlayer dielectric layer 46 is about 5000 angstroms.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the invention. As shown in FIG. 7, in contrast to the previous embodiment in which the entire contact hole etch stop layer 44 is covered with the IMD layer 46, the present invention may be configured to remove a portion of the contact hole etch stop layer 44 in the second region 16 in advance by a metal silicide process after the formation of the contact hole etch stop layer 44 in FIG. 1, such that the removal of a portion of the masking layer 48, a portion of the IMD layer 46, a portion of the STI 24, and a portion of the insulating layer 20 to form the first contact hole 58 in FIG. 2 does not remove any of the contact hole etch stop layer 44, or the sidewalls of the contact hole etch stop layer 44 may completely cover the IMD layer 46 and not be exposed to the first contact hole 58 as in FIG. 2. The fabrication of the first contact plug 68 and the second contact plug 70 may then be completed compared to the fabrication processes of fig. 3 to 6. Since the contact hole etch stop layer 44 is disconnected or not located in the second region 16 before the formation of the interlayer dielectric layer 46, the subsequently formed first contact plug 68, including the first portion 72 and the second portion 74 of the first contact plug 68, will not directly contact the contact hole etch stop layer 44, which is also within the scope of the present invention.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.