阅读说明：本技术 基于超结mosfet的集成器件及其制造方法 (Integrated device based on super junction MOSFET and manufacturing method thereof ) 是由 盛琳 东伟 于 2021-10-19 设计创作，主要内容包括：本发明属于半导体技术领域,提供了基于超结MOSFET的集成器件及其制造方法。本发明提供的基于超结MOSFET的集成器件包括：漏极、半导体衬底、半导体衬底上设置的至少两个超结MOSFET、用于源极不相连的超结MOSFET之间的源极隔离结构,所述隔离结构包括至少一个浮空P柱结构,所述超结MOSFET包括了P型体掺杂区、P柱、外延区、源极区、源极金属层、绝缘介质层、氧化物层、多晶硅栅极；所述两个源极不相连的超结MOSFET相邻P柱之间具有隔离距离,通过设置不同的隔离结构增大所述隔离距离,可以提高超结MOSFET之间的隔离电压,保证隔离电压性能同时将超结MOSFET集成一体。(The invention belongs to the technical field of semiconductors, and provides an integrated device based on a super junction MOSFET and a manufacturing method thereof. The invention provides a super junction MOSFET-based integrated device, which comprises: the super-junction MOSFET comprises a P-type body doping area, a P column, an epitaxial area, a source metal layer, an insulating medium layer, an oxide layer and a polycrystalline silicon grid; the isolation distance is arranged between the two adjacent P columns of the super-junction MOSFET with the unconnected source electrodes, and the isolation distance is increased by arranging different isolation structures, so that the isolation voltage between the super-junction MOSFET can be increased, and the performance of the isolation voltage is ensured, and the super-junction MOSFET is integrated into a whole.)

1. An integrated device based on a super junction MOSFET, comprising:

a drain electrode;

the semiconductor substrate is provided with at least two super-junction MOSFETs and an isolation structure, the super-junction MOSFETs share a drain electrode, the isolation structure is arranged between any two super-junction MOSFETs with unconnected source electrodes, and the isolation structure at least comprises a floating P column.

2. The integrated device of claim 1, wherein the super-junction MOSFET comprises at least a P-type body doped region, a P-column and an epitaxial region arranged on the semiconductor substrate, wherein the P-column and the P-type body doped region are located in the epitaxial region and are in contact with the P-type body doped region, a source region is arranged on the P-type body doped region, a gate is arranged on the P-type body doped region, an oxide layer is arranged between the gate and the epitaxial region, the upper surface of the gate is covered with an insulating medium layer, and a source metal layer in contact with the source region is covered on the insulating medium layer;

the P columns have a first width, and a first P column distance is reserved between adjacent P columns of the super junction MOSFET; the floating P-pillar has a second width, and a second P-pillar distance exists between the floating P-pillar and the adjacent P-pillar or the floating P-pillar, wherein the ratio of the first width to the first P-pillar distance is equal to the ratio of the second width to the second P-pillar distance.

3. The integrated device of claim 2, wherein the first width and the second width are the same, and the first P-pillar distance and the second P-pillar distance are the same.

4. The integrated device of any of claims 1 to 3, wherein the isolation structure further comprises an isolation dielectric layer disposed at intervals between adjacent floating P-pillars.

5. The integrated device of claim 1, wherein charge balance is between adjacent ones of the superjunction MOSFETs.

6. Method for manufacturing an integrated device based on a superjunction MOSFET according to any of claims 1 to 5, characterized in that it comprises the following steps:

growing an epitaxial region on the surface of the semiconductor substrate;

forming a plurality of P columns in the epitaxial region;

depositing an oxide layer and a grid electrode material layer above the epitaxial region in sequence, and etching the grid electrode material layer to form more than two grid electrodes;

forming a P-type body doping area through high-temperature diffusion after ion implantation;

forming more than two source regions on partial surface of the P-type body doping region;

after depositing an insulating medium layer above the epitaxial region, etching the insulating medium layer to form a source contact hole which enables the source region to be at least partially exposed;

depositing metal above the insulating medium layer to form a source metal layer, etching the source metal layer to form at least two unconnected source electrodes, wherein each source electrode is respectively contacted with at least one source electrode region;

depositing a layer of metal on the semiconductor substrate to lead out and form a drain so as to form at least two super junction MOSFETs with unconnected source electrodes;

the plurality of P columns comprise a first P column in contact with the source region and a floating P column located between any two super junction MOSFETs with unconnected source electrodes, and the floating P column is used for improving source isolation voltage.

7. The method of manufacturing of claim 6, wherein the first P-pillars have a first width, first P-pillar distances between first P-pillars of the super-junction MOSFET, the floating P-pillars have a second width, a second P-pillar distance between the floating P-pillar and an adjacent first P-pillar or the floating P-pillar, and a ratio of the first width to the first P-pillar distance is equal to a ratio of the second width to the second P-pillar distance.

8. The method of manufacturing of claim 7, wherein the first width and the second width are the same, and the first P-pillar distance and the second P-pillar distance are the same.

9. The method of manufacturing of claim 6, wherein said forming a plurality of P-pillars in said epitaxial region further comprises, prior to said forming a plurality of P-pillars:

and depositing a medium in the epitaxial region to form an isolation medium layer, wherein the isolation medium layer is positioned between the adjacent floating P columns at intervals.

10. The method of manufacturing of claim 6 or 9, wherein said forming a plurality of P-pillars in said epitaxial region comprises:

and growing and forming a plurality of P columns in the epitaxial region by a deep groove etching method or a multiple epitaxial method.

Technical Field

The application belongs to the technical field of semiconductors, and particularly relates to an integrated device based on a super junction MOSFET and a manufacturing method thereof.

Background

A Super Junction field effect transistor (SJMOS) is a novel power device, compared with a traditional vertical conduction field effect transistor (VDMOS) device, a P column (P-pilar) structure is added to the SJMOS, the structure adopts a charge balance principle, and the forward conduction resistance of the SJMOS in unit area is far lower than that of the VDMOS by generating a transverse electric field. SJMOS devices are becoming mainstream devices for manufacturing power integrated circuits with low power consumption and low cost due to their advantages of high switching speed, low power consumption, high withstand voltage, and the like.

SJMOS and conventional VDMOS are three-terminal (drain, source and gate) devices, and as the integration capability of an integrated circuit system is improved, many applications require the three-terminal device to add an auxiliary function, such as a current sampling function or a start-up function, so that there is a case where a plurality of MOSFETs share a drain and a gate on one device, but the sources between different main MOSFETs and auxiliary MOSFETs are not connected, and a certain voltage withstanding capability is required between the sources, so an isolation structure is required between the sources. A conventional source isolation structure commonly used for the VDMOS is to set an isolation region between P-body doped regions (P-bodies) of a main MOSFET and an adjacent auxiliary MOSFET, and an SJMOS may adopt an isolation structure similar to the VDMOS, but since a P pillar of the SJMOS has a voltage balance requirement, an isolation voltage cannot be increased by simply increasing a distance between the P-body doped regions, and the distance between the P-body doped regions must be the same as that between the P pillars, otherwise, a breakdown voltage of a device may be reduced, resulting in a functional defect of the device.

Therefore, how to stably and reliably integrate the SJMOS together while ensuring the isolation voltage performance of the SJMOS is an urgent problem to be solved in the application of semiconductor products.

Disclosure of Invention

The application aims to provide an integrated device based on a super-junction MOSFET and a manufacturing method thereof, and aims to solve the problem that the source isolation voltage cannot be improved by simply increasing the distance between P-type body doped regions when the super-junction MOSFETs are integrated together.

A first aspect of embodiments of the present application provides an integrated device based on a super junction MOSFET, including:

a drain electrode;

the semiconductor substrate is provided with at least two super-junction MOSFETs and an isolation structure, the super-junction MOSFETs share a drain electrode, the isolation structure is arranged between any two super-junction MOSFETs with unconnected source electrodes, and the isolation structure at least comprises a floating P column.

In one embodiment, the super-junction MOSFET at least comprises a P type body doping area, a P column and an epitaxial area which are arranged on the semiconductor substrate, wherein the P column and the P type body doping area are located in the epitaxial area and are in contact with each other, a source area is arranged on the P type body doping area, a multi-grid is arranged on the P type body doping area, an oxide layer is arranged between the grid and the epitaxial area, the upper surface of the grid is covered with an insulating medium layer, and a source metal layer in contact with the source area is covered on the insulating medium layer;

in one embodiment, the semiconductor substrate, the epitaxial region and the source region are doped with a first conductive type element.

In one embodiment, the P-column and the floating P-column of the superjunction MOSFET are doped with a second conductivity type element.

In one embodiment, the first conductive type element or the second conductive type element is selected according to a type required by a user in actual production.

In one embodiment, the first conductive type element is an N-type element and the second conductive type element is a P-type element.

In one embodiment, the P-pillars have a first width, with a first P-pillar distance between adjacent P-pillars of the superjunction MOSFET; the floating P column has a second width, a second P column distance is arranged between the floating P column and the adjacent P column or the floating P column, and the ratio of the first width to the first P column distance is equal to the ratio of the second width to the second P column distance.

In one embodiment, the first width and the second width are the same, and the first P-pillar distance and the second P-pillar distance are the same.

In one embodiment, the isolation structure comprises isolation dielectric layers which are arranged between adjacent floating P columns at intervals.

In one embodiment, the super junction MOSFET satisfies charge balance.

A second aspect of the embodiments of the present application provides a method for manufacturing a super junction MOSFET-based integrated device, including the steps of:

growing an epitaxial region on the surface of the semiconductor substrate;

forming a plurality of P columns in the epitaxial region;

depositing an oxide layer and a grid electrode material layer above the epitaxial region in sequence, and etching the grid electrode material layer to form more than two grid electrodes;

forming a P-type body doping area through high-temperature diffusion after ion implantation;

forming more than two source regions on partial surface of the P-type body doping region;

after depositing an insulating medium layer above the epitaxial region, etching the insulating medium layer to form a source contact hole which enables the source electrode to be at least partially exposed;

depositing metal above the insulating medium layer to form a source metal layer, etching the source metal layer to form at least two unconnected source electrodes, wherein each source electrode is respectively contacted with at least one source electrode region;

depositing a layer of metal on the semiconductor substrate to lead out and form a drain so as to form at least two super junction MOSFETs with unconnected source electrodes;

the plurality of P columns comprise a first P column in contact with the source region and a floating P column located between any two super-junction MOSFETs with unconnected sources, and the floating P column is used for improving source isolation voltage.

In one embodiment, the first P-pillars have a first width, the first P-pillars of the super-junction MOSFET have a first P-pillar distance therebetween, the floating P-pillars have a second width, the floating P-pillars have a second P-pillar distance therebetween, and a ratio of the first width to the first P-pillar distance is equal to a ratio of the second width to the second P-pillar distance.

In one embodiment, the first width and the second width are the same, and the first P-pillar distance and the second P-pillar distance are the same.

In one embodiment, the step of forming a plurality of P pillars in the epitaxial region further includes:

and depositing a medium in the epitaxial region to form an isolation medium layer, wherein the isolation medium layer is positioned between the adjacent floating P columns at intervals.

In one embodiment, the forming a plurality of P pillars on the epitaxial region comprises:

and growing and forming a plurality of P columns in the epitaxial region by a deep groove etching method or a multiple epitaxial method.

In one embodiment, the semiconductor substrate, the epitaxial region and the source region are doped with a first conductive type element.

In one embodiment, the P-column and the floating P-column of the superjunction MOSFET are doped with a second conductivity type element.

In one embodiment, the first conductive type element or the second conductive type element is selected according to a type required by a user in actual production.

In one embodiment, the first conductive type element is an N-type element and the second conductive type element is a P-type element.

In the super-junction MOSFET-based integrated device and the manufacturing method thereof, the super-junction MOSFET-based integrated device comprises a drain electrode and a semiconductor substrate, wherein the semiconductor substrate is provided with at least two super-junction MOSFET and an isolation structure, the super-junction MOSFET shares the drain electrode, and the isolation structure at least comprises a floating P column isolation structure; a source isolation structure is realized by arranging the floating P column, the charge balance requirement of the super-junction MOSFET is met, the source isolation voltage between the super-junction MOSFETs with unconnected sources is increased, a plurality of super-junction MOSFETs are stably integrated on one device, and the performance of the super-junction MOSFETs is ensured.

Drawings

Fig. 1 is a schematic structural diagram of a super junction MOSFET-based integrated device provided in an embodiment of the present application;

fig. 2 is a schematic diagram of a super junction MOSFET-based integrated device structure in which an isolation structure provided in an embodiment of the present application includes two floating P pillars;

fig. 3 is a schematic diagram of a super junction MOSFET-based integrated device structure in which an isolation structure provided in an embodiment of the present application includes two floating P pillars and an isolation dielectric layer;

FIG. 4 is a schematic structural diagram of a P-pillar and a floating P-pillar formed during a manufacturing method according to an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of a gate formed during a manufacturing process according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a P-type body doped region formed during a fabrication method according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram illustrating the formation of a source region during a manufacturing method according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram illustrating formation of a source contact hole during a manufacturing process according to an embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating a structure of a source formed during a manufacturing process according to an embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a structure of a drain formed during a manufacturing process according to an embodiment of the present invention;

FIG. 11 is a schematic structural diagram illustrating the formation of an isolation dielectric layer during a fabrication process according to an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of a floating P-pillar and an isolation dielectric layer formed during a manufacturing method according to an embodiment of the present invention;

reference numerals:

1. a source electrode; 2. an insulating dielectric layer; 3. a gate electrode; 4. an oxide layer; 5. a source region; 6. an epitaxial region; 7. a P-type body doped region; 8. a P column; 9. an isolation structure; 10. floating the P column; 11. a semiconductor substrate; 12. isolating the dielectric layer; 13. and a drain electrode.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

As shown in fig. 1, the present application embodiment provides a super junction MOSFET based integrated device. The super junction MOSFET-based integrated device in the embodiment comprises a drain 13 and a semiconductor substrate 11, at least two super junction MOSFETs and an isolation structure 9 are arranged on the semiconductor substrate 11, the isolation structure 9 is arranged between any two super junction MOSFETs with unconnected source electrodes 1, and the isolation structure 9 comprises a floating P column 10.

In the example of fig. 1, the super-junction MOSFETs shown are three, three super-junction MOSFETs share a drain, two super-junction MOSFETs are main super-junction MOSFETs, the two main super-junction MOSFETs share a source 1, the other is an auxiliary super-junction MOSFET for adding auxiliary functions to the integrated device, the source 1 of the auxiliary super-junction MOSFET and the sources 1 of the two main super-junction MOSFETs are not connected, an isolation structure 9 is provided between the main super-junction MOSFET and the auxiliary super-junction MOSFET for isolating the sources 1 between the main super-junction MOSFET and the auxiliary super-junction MOSFET, and by using an isolation structure such as a floating P column 10, it is possible to increase the source isolation voltage between the main super-junction MOSFET and the auxiliary super-junction MOSFET while ensuring that each super-junction MOSFET maintains charge balance.

In an embodiment, in the super-junction MOSFET, the epitaxial region 6 is formed above the semiconductor substrate 11, the drain 13 is formed below the semiconductor substrate 11, the super-junction MOSFET includes a P-pillar 8 and a P-type body doped region 7 disposed on the semiconductor substrate 11 and located in the epitaxial region 6, wherein two source regions 5 are disposed in the P-type body doped region 7, a gate 3 is disposed above the P-type body doped region 7, and the gate 3 may be made of polysilicon; an oxide layer 4 is arranged below the grid 3, an insulating medium layer 2 covers the upper surface of the grid 3, a metal layer covers the upper surface of the insulating medium layer 2 and is used for forming a source electrode 1, a P column 8 is in contact with a P type doped body region 7, the P type doped body region 7 is used for forming a transverse conducting channel, and a source electrode region 5 is in contact with the source electrode 1.

As an embodiment, the epitaxial region 6 is doped with a first conductive type element, and the source region 5 is doped with the first conductive type element. The semiconductor substrate 11 is doped with a first conductivity type element. The P-pillar 8 and the floating P-pillar 10 of the super junction MOSFET are doped with a second conductivity type element different from the first conductivity type element. The first conductive type element or the second conductive type element is selected according to the type required in actual production by a user.

In one embodiment, the first conductive type element is an N-type element, and the second conductive type element is a P-type element.

As an embodiment, as shown in fig. 1 and 2, the super junction MOSFET may include at least: a source metal layer (namely a source electrode) 1, an insulating dielectric layer 2, a grid electrode 3, an oxide layer 4, a source electrode region 5, an epitaxial region 6, a P-type body doping region 7 and a P column 8; the P columns 8 of the super-junction MOSFET are distinguished from the floating P columns 10 as the isolation structures 9, the P columns 8 have a first width Xp, the P columns 8 of the super-junction MOSFET have a first P column distance Xn therebetween, the floating P columns 10 have a second width Xgp, the floating P columns 10 and the adjacent P columns 8 have a second P column distance Xgn therebetween, and the ratio of the first width to the first P column distance is equal to the ratio of the second width to the second P column distance, that is, Xp/Xn = Xgp/Xgn, so as to ensure that each super-junction MOSFET maintains charge balance.

Optionally, the isolation structure 9 of this embodiment includes a plurality of floating P pillars 10, the P pillars 8 of the superjunction MOSFET have a first width Xp, the P pillars 8 of the superjunction MOSFET have a first P pillar distance Xn therebetween, the floating P pillars 10 have a second width Xgp, the floating P pillars 10 and the P pillars 8 of the adjacent superjunction MOSFET have a second P pillar distance Xgn therebetween, where Xp = Xgp and Xn = Xgn, so as to ensure that each superjunction MOSFET maintains charge balance.

As shown in fig. 3, as an embodiment, the isolation structure 9 of this embodiment includes two floating P pillars 10, the P pillars 8 have a first width Xp therebetween, the P pillars 8 of the super junction MOSFET have a first P pillar distance Xn therebetween, the floating P pillars 10 have a second width Xgp, the floating P pillars 10 and the adjacent P pillars 8 and the adjacent floating P pillars 10 have a second P pillar distance Xgn therebetween, where Xp = Xgp and Xn = Xgn. The width of the P columns of the super-junction MOSET is equal to the width of the floating P columns 10, and the distance between the P columns 8 of the super-junction MOSFET is equal to the distance between the adjacent floating P columns 10, so that the integrated device is easier to realize in the manufacturing process; the two floating P columns 10 are arranged to further increase the isolation distance of the super-junction MOSFET with unconnected source electrodes under the condition of meeting the charge balance requirement of the super-junction MOSFET, so that the source isolation voltage of the integrated device is further improved.

As shown in fig. 3, as an embodiment, the isolation structure 9 includes at least two floating P pillars 10 and an isolation dielectric layer 12, the isolation dielectric layer 12 is located between the two floating P pillars 10, and the isolation dielectric layer 12 further increases the isolation between the two floating P pillars 10 while increasing the source isolation voltage of the integrated device, so as to further reduce the surface leakage current of the isolation structure 9 and improve the performance of the integrated device. Optionally, the material of the isolation dielectric layer 12 is an oxide, such as silicon dioxide.

It will also be appreciated that each super junction MOSFET meets the charge balance requirements.

In the super junction MOSFET-based integrated device in this embodiment, by providing different isolation structures 9, for example, by providing one or two floating P-pillars 10 isolation structures, the isolation distance between the super junction MOSFETs whose sources are not connected is increased, and the source isolation voltage of the integrated device is increased; or an isolation medium layer 12 isolation structure is further added between the floating P columns 10, so that the source isolation voltage of the integrated device of the super-junction MOSFET is improved, the surface leakage current of the isolation structure can be reduced, and the integration of the super-junction MOSFET is facilitated and the performance of the integrated device is improved.

The application provides a manufacturing method of an integrated device based on a super junction MOSFET. The manufacturing method of the super junction MOSFET-based integrated device provided by the embodiment comprises the following steps:

step one, an epitaxial region 6 is grown and formed on the surface of the semiconductor substrate 11.

Referring to fig. 4, the semiconductor substrate 11 and the epitaxial region 6 are doped with a first conductive type element.

And step two, forming a plurality of P columns on the epitaxial region 6.

Wherein, a P column can be formed on the epitaxial region 6 by deep trench etching or multiple epitaxial growth; as shown in fig. 4, the position of the deep trench for forming the P-pillar is determined in the epitaxial region 6, the deep trench is etched by using a deep trench etching process, and the P-type silicon is filled in the deep trench to form the P-pillar 8 and the floating P-pillar 10, or the P-pillar 8 and the P-pillar 10 are formed by using a multi-time epitaxial method.

And step three, depositing an oxide layer and a grid electrode material layer above the epitaxial region 6 in sequence, and etching the grid electrode material layer to form more than two grid electrodes 3.

As shown in fig. 5, an oxide layer 4 is formed by depositing an oxide layer on the epitaxial region 6, a gate material (such as polysilicon) is deposited on the oxide layer 4, and then the gate material is etched to form 3 gates 3, wherein the gates 3 are used for forming the gates of the super junction MOSFET, and the number of the gates 3 can be adjusted according to the number of the super junction MOSFETs.

And step four, forming a P-type body doping region 7 through high-temperature diffusion after ion implantation.

As shown in fig. 6, ions doped with the second conductivity type are implanted on the P-pillar 10 and diffused at high temperature to form a P-type body doped region 7 for forming a lateral conduction channel of the super junction MOSFET. Alternatively, the threshold voltage of the super junction device can be adjusted by changing the dopant amount.

Step five, forming more than two source regions 5 on partial surface of the P-type body doping region 7;

as shown in fig. 7, six source regions 5 are formed on the surface of the P-type body doping region 7 by ion implantation, and the source regions 5 are doped with the first conductive type element. The number of source regions 5 may be adjusted according to the number of super junction MOSFETs.

And sixthly, after the insulating medium layer 2 is deposited above the epitaxial region 6, etching the insulating medium layer 2 to form a source contact hole which enables the source region 5 to be at least partially exposed.

As shown in fig. 8, an insulating dielectric layer 2 is deposited on the epitaxial region 6, and the insulating dielectric layer 2 is etched to form a source contact hole, wherein a source region 5 at the source contact hole is at least partially exposed for arranging a source 1 of the super junction MOSFET.

And seventhly, depositing metal above the insulating dielectric layer 2 to form a source metal layer, etching the source metal layer to form at least two unconnected source electrodes 1, wherein each source electrode 1 is respectively contacted with at least one source electrode area 5.

As shown in fig. 9, in this embodiment, a metal is deposited over the insulating dielectric layer 2 to form a source metal layer, and then the source metal layer is etched to form two unconnected source electrodes 1, each source electrode 1 is in contact with at least one source region 5 for forming the source electrodes of two super junction MOSFETs, and the source metal layer may be aluminum metal. Wherein, in other embodiments, the number of unconnected sources 1 can be adjusted according to the number of super junction MOSFETs.

And step eight, depositing a layer of metal on the bottom of the semiconductor substrate 11 to be led out to form a drain electrode 13 so as to form at least two super junction MOSFETs with unconnected source electrodes 1.

As shown in fig. 10, metal is deposited on the bottom of the semiconductor substrate 11, and the metal is led out as the drain 13 of the super junction MOSFET.

In the super-junction MOSFET-based integrated device manufactured by the method of the present embodiment, the P column includes a first P column (i.e., the P column of the above-mentioned super-junction MOSFET) 8 in contact with the source region 5, and a floating P column 10 between the two super-junction MOSFETs whose sources 1 are not connected, where the floating P column 10 is used to increase the isolation distance between the super-junction MOSFETs and increase the source isolation voltage.

Wherein the first P pillars 8 have a first width Xp, the P pillars 8 of the superjunction MOSFET have a first P pillar distance Xn therebetween, the floating P pillars 10 have a second width Xgp, and the floating P pillars 10 and the P pillars 8 of the adjacent superjunction MOSFET have a second P pillar distance Xgn therebetween, where Xp = Xgp and Xn = Xgn, to facilitate ensuring that each superjunction MOSFET maintains charge balance, see fig. 1 and 2.

As an embodiment, in the super junction MOSFET-based integrated device manufactured by the method of this embodiment, the first width and the second width are the same, and the first P-column distance and the second P-column distance are the same.

In one embodiment, the first conductive type element is an N-type element, and the second conductive type element is a P-type element.

In another embodiment, a step of depositing a medium in the epitaxial region 6 to form an isolation medium layer 12 is further included before the second step.

Referring to fig. 11, the epitaxial region 6 is located with a deep trench, a trench is etched by a deep trench etching process, and after a dielectric is deposited, the dielectric on the surface is etched to form an isolation dielectric layer 12, where the dielectric is made of an oxide, such as silicon dioxide. As shown in fig. 12, in the present embodiment, the isolation dielectric layer 12 is disposed between adjacent floating P pillars at intervals. The isolation dielectric layer 12 further increases the isolation between the two floating P pillars 10 while improving the source isolation voltage of the integrated device, thereby further reducing the surface leakage current of the isolation structure 9 and improving the performance of the integrated device. Optionally, the material of the isolation dielectric layer 12 is an oxide, such as silicon dioxide.

In this embodiment, steps three to eight are the same as in the previous embodiment, and are not described again here.

In the super-junction MOSFET-based integrated device and the manufacturing method thereof, the super-junction MOSFET-based integrated device comprises a drain electrode and a semiconductor substrate, wherein the semiconductor substrate is provided with at least two super-junction MOSFET and an isolation structure, the super-junction MOSFET shares the drain electrode, and the isolation structure at least comprises a floating P column isolation structure; a source isolation structure is realized by arranging the floating P column, the charge balance requirement of the super-junction MOSFET is met, the source isolation voltage between the super-junction MOSFETs with unconnected sources is increased, a plurality of super-junction MOSFETs are stably integrated on one device, and the performance of the super-junction MOSFETs is ensured.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.