阅读说明：本技术 一种高频高功率的soi射频收发开关 (High-frequency high-power SOI radio frequency transceiving switch ) 是由 孙洋涛 苏黎明 陈阳平 姚静石 毛毅 于 2021-10-21 设计创作，主要内容包括：本发明提出了一种高频高功率的SOI射频收发开关,包括接收通路输入端RX、接收串联支路、接收并联支路、发射串联支路、发射并联支路、发射通路输出端TX、第一控制电压模块、第二控制电压模块和天线输入端ANT；所述接收通路输入端RX、接收串联支路、发射串联支路和发射通路输出端TX依次连接；所述接收并联支路接地后搭接在接收通路输入端RX和接收串联支路之间；所述发射并联支路接地后搭接在发射通路输出端TX和发射串联支路之间；在所述发射并联支路内还设置有电压平均网络,所述发射并联支路通过电压平均网络与第二控制电压模块连接；所述发射串联支路与所述第一控制电压模块连接。(The invention provides a high-frequency high-power SOI radio frequency transceiving switch, which comprises a receiving path input end RX, a receiving series branch, a receiving parallel branch, a transmitting series branch, a transmitting parallel branch, a transmitting path output end TX, a first control voltage module, a second control voltage module and an antenna input end ANT; the receiving path input end RX, the receiving series branch, the transmitting series branch and the transmitting path output end TX are connected in sequence; the receiving parallel branch is grounded and then is lapped between the receiving path input end RX and the receiving series branch; the transmitting parallel branch is grounded and then is lapped between the transmitting path output end TX and the transmitting series branch; a voltage averaging network is further arranged in the transmitting parallel branch, and the transmitting parallel branch is connected with a second control voltage module through the voltage averaging network; the transmitting series branch is connected with the first control voltage module.)

1. A high-frequency high-power SOI radio frequency transceiving switch is characterized by comprising a receiving access input end RX, a receiving series branch (3), a receiving parallel branch (4), a transmitting series branch (1), a transmitting parallel branch (2), a transmitting access output end TX, a first control voltage module, a second control voltage module and an antenna input end ANT;

the receiving path input end RX, the receiving series branch (3), the transmitting series branch (1) and the transmitting path output end TX are connected in sequence;

the receiving parallel branch (4) is grounded and then is lapped between the receiving path input end RX and the receiving series branch (3);

the transmitting parallel branch (2) is grounded and then is lapped between the transmitting path output end TX and the transmitting series branch (1);

a voltage averaging network (5) is further arranged in the transmitting parallel branch (2), and the transmitting parallel branch (2) is connected with a second control voltage module through the voltage averaging network (5);

the transmitting series branch (1) is connected with the first control voltage module;

the antenna input end ANT is lapped between the transmitting series branch (1) and the receiving series branch (3).

2. A high frequency high power SOI radio frequency transmit-receive switch as claimed in claim 1, characterized in that said transmitting parallel branch (2) comprises n series units, each series unit comprising an NMOS capacitor C, a transistor M2, a gate resistor RG, a diode D;

in each series unit, two ends of the NMOS capacitor C are respectively lapped between the source and the drain of the transistor M2; the anode of the grid resistor RG and the diode D after being connected in parallel is lapped on the grid of the transistor M2, and the cathode is connected with the voltage averaging network (5);

the drain of the transistor M2 in the first series unit is connected between the transmission path output TX and the transmission series branch (1); each series cell is connected in series by the source and drain of the transistor M2 of each other; the source of the last transistor M2 is grounded;

the transistor M2 is connected to the voltage averaging network (5) via a parallel connected gate resistor RG and a diode D.

3. A high frequency high power SOI radio frequency transmit-receive switch according to claim 2, characterized in that said voltage averaging network (5) comprises n bias resistors Rb and n-1 bias resistors Rs;

the n bias resistors Rb are connected in parallel, one end of each of the n bias resistors Rb is correspondingly connected with the gate resistor RG of one series unit, and the other end of each of the n bias resistors Rb is connected with the second control voltage module and receives a control voltage VG2 sent by the second control voltage module;

n-1 bias resistors Rs are respectively connected to one end of a gate resistor RG of a series unit in which two bias resistors Rb are connected at intervals.

4. A high frequency high power SOI radio frequency transmit-receive switch as claimed in claim 1, characterized in that said transmit series branch (1) comprises M transistors M1, M gate resistances Rg;

m transistors M1 are connected in series in pairs through source electrodes and grid electrodes; the source of the first transistor M1 is connected to the transmit path output TX, and the drain of the nth transistor M1 is connected to the antenna input ANT;

one end of each of the M gate resistors Rg is correspondingly connected to the gate of the transistor M1, and the other end of each of the M gate resistors Rg is connected to the first control voltage module for receiving the control voltage VG1 sent by the first control voltage module.

5. The SOI radio frequency transceiver switch of claim 4, wherein the number of the transistors M1 and the gate resistor Rg is 18, the width of the transistor M1 is 6mm, and the resistance of the gate resistor Rg is 40K Ω.

6. The SOI radio frequency transmit-receive switch of high frequency and high power according to claim 1, wherein 10 transistors and gate resistors are arranged in the receiving parallel branch (4) to form a transistor stacked circuit structure, the width of 10 transistors is set to be 2mm, and the resistance of the gate resistor is 130 kOmega.

7. A high-frequency high-power SOI radio frequency transmit-receive switch as claimed in claim 2 or 3, characterized in that 28 series units are provided in said transmitting parallel branch (2), the width of the transistor in each series unit in the transmitting parallel branch (2) is 6mm, and the resistance of the gate resistor RG is 130K Ω.

8. A high frequency high power SOI radio frequency transmit-receive switch as claimed in claim 2, characterized in that said receiving series branch (3) comprises a plurality of series connected cells, the drain of the transistor M2 in the first series cell being connected to the antenna input ANT, and the source of the transistor M2 in the last series cell being connected to the receiving path input RX.

9. A high frequency high power SOI radio frequency transmit-receive switch as claimed in claim 8, characterized in that 28 series cells are provided in said receiving series branch (3), and that the transistor width of the transistor M2 of the series cell in the receiving series branch (3) is set to 2 mm.

10. SOI radio frequency transmit-receive switch with high frequency and high power as claimed in claim 9, characterized in that the gate resistance RG in the receiving series branch (3) has a value of 30K Ω.

Technical Field

The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a high-frequency and high-power SOI radio frequency transceiving switch.

Background

In recent years, with the development of wireless communication technology and the increasing demand for high-speed data transmission, communication devices such as mobile phones and base stations have made more stringent requirements on the performance and reliability of radio frequency front-end devices, such as higher frequency band and higher power tolerance. The rf transceiver switch plays a crucial role in the whole transceiver link as a key device of the rf front end, for example, it is desirable to have higher power tolerance when transmitting is conducted, and it is desirable to have lower insertion loss when receiving is conducted.

In addition, since SOI (silicon on insulator) technology has the advantages of low substrate loss, low parasitic capacitance, and the like, SOI technology is the primary choice for radio frequency transceiver switches at present. Among them, the transistor stacking technology is a conventional means for improving the power endurance of the switch. However, as the operating frequency and the input power are continuously increased, the parasitic effect and the non-linear characteristic of the transistor itself become more significant, so that the voltage swing of the rf signal on the stacked branch of the turn-off transistor is more uneven, and finally the power endurance and the operating frequency of the switch cannot meet the real requirement. Therefore, the research and design of the high-frequency high-power radio frequency transceiving switch have practical significance.

Disclosure of Invention

In view of the above requirements of the prior art, the present invention provides a high-frequency high-power SOI rf transceiver switch, which ensures that the gate impedance of the transistor does not drop at high frequency and the gate voltage distribution of the transistor is more uniform by introducing a voltage averaging network in the transistor stacking branch of the transmitting parallel branch based on the conventional transistor stacking technology.

The specific implementation content of the invention is as follows:

the invention provides a high-frequency high-power SOI radio frequency transceiving switch, which comprises a receiving path input end RX, a receiving series branch, a receiving parallel branch, a transmitting series branch, a transmitting parallel branch, a transmitting path output end TX, a first control voltage module, a second control voltage module and an antenna input end ANT;

the receiving path input end RX, the receiving series branch, the transmitting series branch and the transmitting path output end TX are connected in sequence;

the receiving parallel branch is grounded and then is lapped between the receiving path input end RX and the receiving series branch;

the transmitting parallel branch is grounded and then is lapped between the transmitting path output end TX and the transmitting series branch;

a voltage averaging network is further arranged in the transmitting parallel branch, and the transmitting parallel branch is connected with a second control voltage module through the voltage averaging network;

the transmitting series branch is connected with the first control voltage module;

the antenna input end ANT is lapped between the transmitting series branch and the receiving series branch.

In order to better implement the present invention, further, the transmitting parallel branch includes n series units, each series unit includes an NMOS capacitor C, a transistor M2, a gate resistor RG, and a diode D;

in each series unit, two ends of the NMOS capacitor C are respectively lapped between the source and the drain of the transistor M2; the anode of the grid resistor RG and the diode D after being connected in parallel is lapped on the grid of the transistor M2, and the cathode of the grid resistor RG and the diode D is connected with the voltage averaging network;

the drain of the transistor M2 in the first series unit is connected between the transmission path output terminal TX and the transmission series branch; each series cell is connected in series by the source and drain of the transistor M2 of each other; the source of the last transistor M2 is grounded;

the transistor M2 is connected to the voltage averaging network through a parallel connected gate resistor RG and diode D.

To better implement the present invention, further, the voltage averaging network includes n bias resistors Rb and n-1 bias resistors Rs;

the n bias resistors Rb are connected in parallel, one end of each of the n bias resistors Rb is correspondingly connected with the gate resistor RG of one series unit, and the other end of each of the n bias resistors Rb is connected with the second control voltage module and receives a control voltage VG2 sent by the second control voltage module;

n-1 bias resistors Rs are respectively connected to one end of a gate resistor RG of a series unit in which two bias resistors Rb are connected at intervals.

In order to better implement the present invention, further, the transmitting series branch includes M transistors M1, M gate resistors Rg;

m transistors M1 are connected in series in pairs through source electrodes and grid electrodes; the source of the first transistor M1 is connected to the transmit path output TX, and the drain of the nth transistor M1 is connected to the antenna input ANT;

one end of each of the M gate resistors Rg is correspondingly connected to the gate of the transistor M1, and the other end of each of the M gate resistors Rg is connected to the first control voltage module for receiving the control voltage VG1 sent by the first control voltage module.

In order to better implement the present invention, further, 18 transistors M1 and gate resistors Rg are provided, the width of the transistor M1 is set to 6mm, and the resistance of the gate resistor Rg is 40K Ω.

In order to better implement the present invention, further, 10 transistors and a gate resistor are disposed in the receiving parallel branch to form a transistor stacked circuit structure, the width of the 10 transistors is set to be 2mm, and the resistance value of the gate resistor is 130K Ω.

In order to better implement the present invention, 28 series units are further provided in the transmitting parallel branch, the width of the transistor in each series unit in the transmitting parallel branch is 6mm, and the resistance value of the gate resistor RG is 130K Ω.

To better implement the present invention, the receiving serial branch further includes a plurality of serial cells connected in series, the drain of the transistor M2 in the first serial cell is connected to the antenna input ANT, and the source of the transistor M2 in the last serial cell is connected to the receiving path input RX.

To better implement the present invention, further, 28 series cells are provided in the receiving series branch, and the transistor width of the transistor M2 of the series cell in the receiving series branch is set to 2 mm.

To better implement the present invention, further, the gate resistor RG in the receiving series branch has a resistance of 30K Ω.

Compared with the prior art, the invention has the following advantages and beneficial effects:

(1) the parallel diode is introduced into the grid resistor of the transistor, so that the problem of impedance reduction of the grid resistor under the condition of high frequency and high power can be effectively avoided, and the power resistance of the radio frequency transceiving switch is improved. Under the high-frequency and high-power working condition, the parasitic effect of the grid electrode of the transistor can cause the grid electrode to generate smaller leakage current, thereby reducing the impedance of the grid electrode resistance. By introducing the parallel diode, when a small gate leakage current is generated, the parallel diode is in a forward bias state but cannot be conducted due to the fact that the parallel diode is lower than a conducting voltage, and therefore high impedance can still be kept at the gate of the transistor. In addition, the size of the diode is small, and complexity cannot be increased for a radio frequency switch layout.

(2) According to the invention, the NMOS capacitor is introduced between the source and the drain of each transistor, so that the voltage swing of the radio-frequency signal between the drain and the source of each transistor can be adjusted in a self-adaptive manner, the radio-frequency signal is more uniform, and the power resistance of the switch is improved. Because the equivalent turn-off capacitance from the first transistor to the last transistor in the turn-off stacked transistor is gradually increased, when a high-power radio-frequency signal enters the turn-off branch circuit, the voltage between the source and the drain of the first transistor to the source and the drain of the last transistor is gradually reduced, so that the first transistor is easier to break down. The capacitance value of the NMOS capacitor is reduced along with the reduction of the voltage of the source electrode and the drain electrode, so that the capacitance value from the first NMOS capacitor to the last NMOS capacitor is reduced step by step, the turn-off equivalent capacitance of each transistor is approximately equal, the voltage swing of a radio frequency signal between the drain electrode and the source electrode of each transistor is more uniform, and the power-resisting capability of the switch is finally improved.

(3) According to the invention, the voltage averaging network is introduced into the grid of the stacked transistor, so that the voltage on the grid voltage bias port in the switch branch circuit is more evenly transmitted to the grid of each transistor, the nonuniformity of the voltage swing of the grid drain and the grid source of the radio frequency signal on each transistor is improved, and the power resistance of the radio frequency transceiving switch is improved.

(4) By adopting the SOI process, the invention has the advantages of high resistivity of the substrate, small parasitic capacitance and the like, and is easier to realize the radio frequency transceiving switch with low insertion loss, high frequency and high power.

Drawings

FIG. 1 is a circuit block diagram of the present invention;

FIG. 2 is a power-tolerant curve when the operating frequency is 7.2GHz and the ambient temperature is 125 ℃ under the condition of transmitting conduction;

FIG. 3 is a simulation result of the normal temperature S parameter under the transmitting conduction condition of the embodiment of the present invention;

FIG. 4 shows simulation results of normal temperature S parameters under the condition of receiving conduction in the embodiment of the present invention.

Wherein: 1. a sending series branch 2, a sending parallel branch 3, a receiving series branch 4, a receiving parallel branch 5 and a voltage averaging network.

Detailed Description

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and therefore should not be considered as a limitation to the scope of protection. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Example 1:

the present embodiment provides a high-frequency and high-power SOI radio frequency transceiver switch, as shown in fig. 1, which includes a receiving path input terminal RX, a receiving series branch 3, a receiving parallel branch 4, a transmitting series branch 1, a transmitting parallel branch 2, a transmitting path output terminal TX, a first control voltage module, a second control voltage module, and an antenna input terminal ANT;

the receiving path input end RX, the receiving series branch 3, the transmitting series branch 1 and the transmitting path output end TX are connected in sequence;

the receiving parallel branch 4 is grounded and then is lapped between the receiving path input end RX and the receiving series branch 3;

the transmitting parallel branch 2 is grounded and then is lapped between the output end TX of the transmitting path and the transmitting series branch 1;

a voltage averaging network 5 is further arranged in the transmitting parallel branch 2, and the transmitting parallel branch 2 is connected with a second control voltage module through the voltage averaging network 5;

the transmitting series branch 1 is connected with the first control voltage module;

the antenna input ANT is lapped between the transmitting series branch 1 and the receiving series branch 3.

Example 2:

on the basis of the foregoing embodiment 1, as shown in fig. 1, the present embodiment is formed by a transmitting series branch 1, a transmitting parallel branch 2, a receiving series branch 3, and a receiving parallel branch 4, and is characterized in that the transmitting series branch 1 is a conventional transistor stacked link structure and mainly includes M transistors M1 … Mm and M gate resistors Rg1 … Rgm; the M transistors are connected in series to form a stacked transistor, the source of the transistor M1 is used as a transmitting path output end TX, the source of the transistor M1 is connected with the transmitting parallel branch 2, the drain of the transistor Mm is connected with an antenna input end ANT, and the drain of the transistor Mm is connected with the receiving series branch 3; one end of each of the M gate resistors Rg1 … rcm is respectively connected with the gate of the corresponding M transistors M1 … Mm, and the other end of each of the M gate resistors Rg1 … rcm is connected with the gate control voltage port VG1 of the emitting series branch 1; m is a positive integer greater than 1.

The transmitting parallel branch 2 is an improved transistor stacked link structure and mainly comprises n transistors M1 … Mn, n gate resistors RG1 … RGn, n diodes D1 … Dn, n NMOS capacitors C1 … Cn and a voltage averaging network 5; the n transistors M1 … Mn are connected in series to form a stacked transistor, the drain electrode of the transistor M1 is connected with the output end TX of the emission path, and the source electrode of the transistor Mn is grounded; one ends of the n gate resistors RG1 … RGn are respectively connected to the gates of the n transistors M1 … Mn, and the other ends are respectively connected to the voltage averaging network 5; the n diodes D1 … Dn are respectively connected with the corresponding n grid resistors RG1 … RGn in parallel, the anodes of the n diodes D1 … Dn are respectively connected with the grids of the corresponding n transistors, and the cathodes of the n diodes D1 … Dn are respectively connected with the voltage averaging network 5; the grid electrodes of the n NMOS capacitors C1 … Cn are respectively connected with the drain electrodes of the corresponding n transistors M1 … Mn, and the source drain electrodes of the n NMOS capacitors C1 … Cn are respectively connected with the source electrodes of the corresponding n transistors M1 … Mn;

the voltage averaging network 5 comprises n bias resistors Rb1 … Rbn and n-1 bias resistors Rs1 … Rsn-1; one end of each of the n bias resistors Rb1 … Rbn is connected to the cathode of the corresponding n diodes D1 … Dn, and the other end is connected to the gate control voltage port VG2 of the emitting parallel branch 2; n-1 bias resistors Rs1 … Rsn-1 respectively span between every two adjacent bias resistors Rb1 … Rbn; n is a positive integer greater than 1.

The receiving serial branch 3 adopts an improved transistor stacked link structure, one end of which is connected with the antenna input ANT and the input end of the transmitting serial branch 1 at the same time, and the other end of which is used as the receiving path output terminal RX and is connected with the receiving parallel branch at the same time.

The receiving parallel branch 4 adopts a conventional transistor stacked link structure, and one end of the receiving parallel branch is connected with the receiving path output terminal RX, and the other end is grounded.

Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.

Example 3:

in this embodiment, on the basis of any of the above embodiments 1-2, the number of transistors stacked in the transmitting series branch 1, the transmitting parallel branch 2, the receiving series branch 3, and the receiving parallel branch 4, and the size of the transistors are generally determined by technical indexes such as return loss, insertion loss, isolation, and power tolerance of the whole rf transceiver switch.

Other parts of this embodiment are the same as any of embodiments 1-2 described above, and thus are not described again.

Example 4:

in this embodiment, on the basis of any of the above embodiments 1 to 3, further, for the rf transceiving switch, when the transmitting path is turned on, the transmitting parallel branch 2 and the receiving series branch 3 usually bear equal and larger voltage swing of the rf signal, and therefore, the number of the transistors stacked in the transmitting parallel branch 2 and the receiving series branch 3 is generally larger than the number of the transistors stacked in the transmitting series branch 1 and the receiving parallel branch 4.

Other parts of this embodiment are the same as any of embodiments 1 to 3, and thus are not described again.

Example 5:

in this embodiment, on the basis of any of the embodiments 1 to 4, further, when the transmission path and the reception path are both on for the rf transceiving switch branch, it is desirable that the insertion loss on the on path is as small as possible, so that the size of the crystal in the transmission series branch 1 and the reception series branch 3 is generally much larger than the size of the transistor in the transmission parallel branch 2 and the reception parallel branch 4.

Other parts of this embodiment are the same as any of embodiments 1 to 4, and thus are not described again.

Example 6:

in this embodiment, based on any one of the above embodiments 1 to 5, the gate control voltages of the transmitting series arm 1 and the receiving parallel arm 4 are the same and are both VG1, and the gate control voltages of the receiving series arm 3 and the transmitting parallel arm 2 are the same and are both VG 2.

Other parts of this embodiment are the same as any of embodiments 1 to 5, and thus are not described again.

Example 7:

in this embodiment, on the basis of any one of the embodiments 1 to 6, further, the gate resistances of the transistors in all the branches of the rf transceiving switch are large enough to ensure that the rf signal voltages are respectively uniform on the gate drain and the gate source, so that the power endurance capability of the switch is not reduced.

Other parts of this embodiment are the same as any of embodiments 1 to 6, and thus are not described again.

Example 8:

this embodiment is based on any of the above embodiments 1 to 7, and further, as shown in fig. 1, in order to better implement the present invention, further, the transmitting parallel branch 2 includes n series units, each series unit includes an NMOS capacitor C, a transistor M2, a gate resistor RG, and a diode D;

in each series unit, two ends of the NMOS capacitor C are respectively lapped between the source and the drain of the transistor M2; the anode of the grid resistor RG and the diode D after being connected in parallel is lapped on the grid of the transistor M2, and the cathode is connected with the voltage averaging network 5;

the drain of the transistor M2 in the first series unit is connected between the transmit path output TX and the transmit series branch 1; each series cell is connected in series by the source and drain of the transistor M2 of each other; the source of the last transistor M2 is grounded;

the transistor M2 is connected to the voltage averaging network 5 via a parallel connected gate resistor RG and a diode D.

The receiving parallel branch 3 adopts the same improved structure as the transmitting parallel branch 2.

The working principle is as follows: the parallel diode is introduced at the grid resistor of the transistor, so that the problem of impedance reduction of the grid resistor under the condition of high frequency and high power can be effectively avoided, and the power resistance of the radio frequency transceiving switch is improved. Under the high-frequency and high-power working condition, the parasitic effect of the grid electrode of the transistor can cause the grid electrode to generate smaller leakage current, thereby reducing the impedance of the grid electrode resistance. By introducing the parallel diode, when a small gate leakage current is generated, the parallel diode is in a forward bias state but cannot be conducted due to the fact that the parallel diode is lower than a conducting voltage, and therefore high impedance can still be kept at the gate of the transistor. In addition, the size of the diode is small, and complexity cannot be increased for a radio frequency switch layout.

By introducing the NMOS capacitor between the source and the drain of each transistor, the voltage swing of the radio-frequency signal between the drain and the source of each transistor can be adjusted in a self-adaptive mode, so that the radio-frequency signal is more uniform, and the power-resisting capability of the switch is improved. Because the equivalent turn-off capacitance from the first transistor to the last transistor in the turn-off stacked transistor is gradually increased, when a high-power radio-frequency signal enters the turn-off branch circuit, the voltage between the source and the drain of the first transistor to the source and the drain of the last transistor is gradually reduced, so that the first transistor is easier to break down. The capacitance value of the NMOS capacitor is reduced along with the reduction of the voltage of the source electrode and the drain electrode, so that the capacitance value from the first NMOS capacitor to the last NMOS capacitor is reduced step by step, the turn-off equivalent capacitance of each transistor is approximately equal, the voltage swing of a radio frequency signal between the drain electrode and the source electrode of each transistor is more uniform, and the power-resisting capability of the switch is finally improved.

Other parts of this embodiment are the same as any of embodiments 1 to 7, and thus are not described again.

Example 9:

this embodiment is based on any of the above embodiments 1 to 8, and in order to better implement the present invention, as shown in fig. 1, and further, in order to better implement the present invention, further, the voltage averaging network 5 includes n bias resistors Rb and n-1 bias resistors Rs;

the n bias resistors Rb are connected in parallel, one end of each of the n bias resistors Rb is correspondingly connected with the gate resistor RG of one series unit, and the other end of each of the n bias resistors Rb is connected with the second control voltage module and receives a control voltage VG2 sent by the second control voltage module;

n-1 bias resistors Rs are respectively connected to one end of a gate resistor RG of a series unit in which two bias resistors Rb are connected at intervals.

The working principle is as follows: by introducing the voltage averaging network into the gates of the stacked transistors, the voltage on the gate voltage bias port in the switch branch is more evenly transmitted to the gate of each transistor, so that the nonuniformity of the gate-drain and gate-source voltage swings of radio-frequency signals on each transistor is improved, and the power-resisting capability of the radio-frequency transceiving switch is improved.

Other parts of this embodiment are the same as any of embodiments 1 to 8, and thus are not described again.

Example 11:

in this embodiment, on the basis of any one of the embodiments 1 to 10, further, the present embodiment provides a high-frequency high-power rf transceiving switch, a circuit structure of which is shown in fig. 1; the process adopted by the embodiment is an SOI process of 0.18um, the transmitting series branch 1 and the receiving parallel branch 4 both adopt a traditional transistor stacked circuit structure, the number of transistors is respectively 18 and 10, the width of the transistors is respectively 6mm and 2mm, and the grid resistance of the transistors is respectively 40K omega and 130K omega; the receiving series branch 3 and the transmitting parallel branch 2 both adopt improved transistor stacking circuit structures, the stacking number of the transistors is 28, the widths of the transistors are respectively 6m and 2m, and the grid resistances of the transistors are respectively 40K omega and 130K omega;

fig. 2 shows a power withstand curve at an operating frequency of 7.2GHz and an ambient temperature of 125 ℃ in the case of transmit-on, where the ordinate represents the high-temperature insertion loss in the case of transmit-on in mdB, and the abscissa represents the input power variation range in dBm. As can be seen, the 0.1dB compression point P0.1dB can achieve 48dBm under the high temperature condition at 7.2GHz in the embodiment of the invention. The radio frequency transceiving switch in the example basically realizes the power endurance capability of 20W continuous waves.

Fig. 3 shows simulation results of the normal temperature S parameter in the case of emission conduction. The ordinate of the diagram is in dB and the abscissa is frequency in GHz. As can be seen from the figure, the input and output return loss of the invention at 7.2GHz is below-22 dB, the insertion loss is about 0.48dB, and the isolation is about 30 dB. Under the condition that the radio frequency transceiving switch in the example is transmitted and conducted, small insertion loss and high isolation are achieved at high frequency.

Fig. 4 shows the simulation result of the normal temperature S parameter in the case of receiving the on state. The ordinate of the diagram is in dB and the abscissa is frequency in GHz. As can be seen from the figure, the input and output return loss of the invention at 7.2GHz is below-22 dB, and the insertion loss is 0.58 dB. The radio frequency transceiving switch in the example has higher performance under the condition of receiving conduction.

Other parts of this embodiment are the same as any of embodiments 1 to 10, and thus are not described again.

Example 12:

in this embodiment, an approximate circuit configuration is described in any of embodiments 1 to 11, for example, in patent application CN108039585A and patent application CN 106972845A.

The parallel branch in patent application CN108039585A adopts a traditional transistor stack structure, and since the voltage swing of the rf signal cannot be uniformly superimposed on each stacked transistor when the rf signal with high power is superimposed on the switched-off parallel branch, the topmost transistor is easily broken down, and finally the power endurance of the switch is reduced. Conventional transistor stack structures have therefore not been able to meet the practical requirements of high power rf switches. In patent application CN106972845A, the parallel branch divides the transistor stack link into two parts based on the traditional transistor stack structure, which improves the power endurance of the switch to some extent in the low frequency case, but does not improve the power endurance in the high frequency case, especially in the frequency band above 6 GHz. Due to the fact that the parasitic effect of the transistor becomes strong under the high-frequency condition and the equivalent impedance of the grid electrode of the transistor becomes small, the voltage distribution of the drain source, the grid source and the grid drain of the transistor is not even any more, and the power resisting capacity is reduced. Compared with patent application CN108039585A and patent application CN106972845A, the present application realizes a switch circuit structure with high power endurance under high frequency condition, and the main improvement points are as follows: firstly, an NMOS capacitor is introduced between the drain and the source of each transistor, so that when a radio frequency large signal comes in, the NMOS capacitor can adaptively adjust the capacitance value according to different voltage values superposed on each transistor, and the voltage distribution at the two ends of the drain and the source of each transistor is more uniform; secondly, parallel diodes are introduced at the grid resistance of the transistor, and because the grid of the transistor has smaller leakage current under the high-frequency and high-power condition, the parallel diodes can not be conducted at the moment, so that the impedance at the grid can keep a larger value under the high-frequency and high-power condition; thirdly, a voltage averaging network is introduced at the grid electrode of the transistor, so that the grid electrode voltage transmitted to each transistor is equal, and the grid source voltage and the grid drain voltage are distributed more uniformly; therefore, the invention is improved to realize a high-frequency and high-power SOI radio frequency transceiving switch.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.