阅读说明：本技术 用于无损压缩硬件电路的存储器 (Memory for lossless compression hardware circuit ) 是由 罗奥 雷燕婕 于 2021-04-15 设计创作，主要内容包括：本发明公开了一种用于无损压缩硬件电路的存储器,所述存储器用于存储已压缩数据,所述已压缩数据包含至少一个匹配字符串,所述存储器包括寄存器模块与静态随机存取存储器模块；所述寄存器模块用于存储所述已压缩数据的第一部分,所述第一部分包含的所述匹配字符串的分布密度大于或等于第一阈值；所述静态随机存取存储器模块用于存储所述已压缩数据的第二部分,所述第二部分包含的所述匹配字符串的分布密度小于所述第一阈值。本发明实施例通过组合寄存器模块和静态随机存取存储器模块来构建存储器,能够使用较小的电路面积实现较高的数据读取速率,并实现对硬件制造成本的控制。(The invention discloses a memory for lossless compression hardware circuit, which is used for storing compressed data, wherein the compressed data comprises at least one matching character string, and the memory comprises a register module and a static random access memory module; the register module is used for storing a first part of the compressed data, and the distribution density of the matching character strings contained in the first part is greater than or equal to a first threshold value; the static random access memory module is used for storing a second part of the compressed data, and the distribution density of the matching character strings contained in the second part is smaller than the first threshold value. The embodiment of the invention constructs the memory by combining the register module and the static random access memory module, can realize higher data reading speed by using smaller circuit area, and realizes the control of hardware manufacturing cost.)

1. A memory for use in lossless compression hardware circuitry, the memory for storing compressed data, the compressed data including at least one matching string, the memory comprising:

the memory comprises a register module and a static random access memory module;

the register module is used for storing a first part of the compressed data, and the distribution density of the matching character strings contained in the first part is greater than or equal to a first threshold value;

the static random access memory module is used for storing a second part of the compressed data, and the distribution density of the matching character strings contained in the second part is smaller than the first threshold value.

2. The memory of claim 1,

the register module comprises M register sub-blocks having a first number of first ports through which the matching strings can be read one at a time, the first number being equal to the number of matching strings to be read from the register sub-blocks, M being a positive integer.

3. The memory of claim 2,

the capacity of the register subblock is greater than or equal to 1K.

4. The memory of claim 3, wherein M equals 2, wherein the register module comprises a first register sub-block and a second register sub-block, wherein,

the first register sub-block has a capacity of 1K, and the first register sub-block has 32 first ports; the second register sub-block has a capacity of 2K and has 16 first ports.

5. The memory of claim 1,

the sram module includes N sram sub-blocks having a second number of second ports, wherein the matching strings can be read one at a time through two adjacent second ports, the second number is equal to twice the number of the matching strings to be read from the sram sub-blocks, N is a positive integer.

6. The memory of claim 5,

the sram subblock includes a second number of sram grains, and a capacity of the sram grains is greater than or equal to 0.5K.

7. The memory of claim 1,

the SRAM module comprises L first sub-blocks of the SRAM and L copies of the first sub-blocks of the SRAM, wherein each first sub-block of the L first sub-blocks of the SRAM has one copy, the first sub-blocks of the SRAM are used for storing data of which the distribution density of the matching character strings is greater than or equal to a second threshold value and smaller than a first threshold value, the copies are used for storing the same data as the copied first sub-blocks of the SRAM, and L is a positive integer;

the duplicate has a third number of second ports, the first sub-block of the SRAM to be duplicated has a fourth number of second ports, wherein the matching strings can be read one at a time through two adjacent second ports, and the sum of the third number and the fourth number is equal to twice the number of the matching strings to be read from the first sub-block of the SRAM.

8. The memory of claim 7,

the duplicate of the first sub-block of SRAM includes a third number of SRAM grains, the first sub-block of SRAM includes a fourth number of SRAM grains, and a capacity of the SRAM grains is greater than or equal to 0.5K.

9. The memory of claim 7,

the sram module further includes Q second sub-blocks of sram for storing data in which the distribution density of the matching strings is smaller than the second threshold, the second sub-blocks of sram having a fifth number of the second ports, wherein the matching strings can be read one at a time through two of the second ports that are adjacent, the fifth number is equal to twice the number of the matching strings to be read from the second sub-blocks of sram, and Q is a positive integer.

10. The memory of claim 9,

the second sub-block of SRAM includes the fifth number of SRAM grains, and a capacity of the SRAM grains is greater than or equal to 0.5K.

Technical Field

The present invention relates to the field of memories, and more particularly to a memory for lossless compression hardware circuits.

Background

The compression mode GZIP is a lossless compression mode based on a compression algorithm LZ77 and Huffman coding. The compression algorithm LZ77 is implemented using a look-up buffer in which a string to be compression encoded (referred to as a target string) is stored, and a look-up buffer in which a string that has been compression encoded is stored. Implementing the LZ77 algorithm first requires finding individual strings in the look-up buffer that are identical to the first few characters of the target string (called matching strings). To achieve better compression efficiency, it is desirable that the matching string be as many as possible of the same character as the target string. Therefore, the matching character string needs to be read from the search buffer and compared with the target character string continuously to determine the matching character string with the same number of characters as the target character string and the largest number of characters. And after the matched character string with the same character number as the target character string and the maximum character number is found, carrying out compression coding on the target character string.

It can be seen that the rate at which matching strings are read in the look-up buffer will affect the overall compression rate. Therefore, the read-write rate of the lookup buffer limits the compression rate.

Disclosure of Invention

Technical problem to be solved

In order to solve the problems that a memory applied to the technical field of lossless compression in the prior art cannot meet the requirement of an LZ77 algorithm on port reading rate, cannot give consideration to the influence on the area of a hardware circuit and the control of cost and the like, the invention provides the memory for the lossless compression hardware circuit.

(II) technical scheme

The invention has proposed a memorizer used for hardware circuit of lossless compression, the memorizer is used for storing the compressed data, the compressed data includes at least one matching character string, the memorizer includes module and Static Random Access Memory (SRAM) module of the register; the register module is used for storing a first part of the compressed data, and the distribution density of the matching character strings contained in the first part is greater than or equal to a first threshold value; the SRAM module is used for storing a second part of the compressed data, and the distribution density of the matching character strings contained in the second part is smaller than a first threshold value.

Optionally, the register module includes M register sub-blocks, each having a first number of first ports, where one matching string can be read at a time through the first ports, the first number is equal to the number of matching strings to be read from the register sub-blocks, and M is a positive integer.

Optionally, the capacity of the register subblock is greater than or equal to 1K.

Optionally, when M is equal to 2, the register module includes a first register sub-block and a second register sub-block, the capacity of the first register sub-block is 1K, and the first register sub-block has 32 first ports; the second register sub-block has a capacity of 2K and has 16 first ports.

Optionally, the SRAM module includes N SRAM sub-blocks, the SRAM sub-blocks having a second number of second ports, wherein one matching string can be read at a time through two adjacent second ports, the second number is equal to twice the number of matching strings to be read from the SRAM sub-blocks, and N is a positive integer.

Optionally, the SRAM sub-block comprises a second number of SRAM grains, and the capacity of the SRAM grains is greater than or equal to 0.5K.

Optionally, the SRAM module includes L SRAM first sub-blocks and copies of the L SRAM first sub-blocks, where each SRAM first sub-block of the L SRAM first sub-blocks has one copy, the SRAM first sub-block is configured to store data with a distribution density of a matching string greater than or equal to a second threshold and smaller than a first threshold, the copy is configured to store the same data as the copied SRAM first sub-block, and L is a positive integer; the duplicate has a third number of second ports, the duplicated SRAM first sub-block has a fourth number of second ports, wherein one matching string can be read at a time through two adjacent second ports, and the sum of the third number and the fourth number is equal to twice the number of matching strings to be read from the SRAM first sub-block.

Optionally, the replica of the first sub-block of SRAM comprises a third number of SRAM grains, the first sub-block of SRAM comprises a fourth number of SRAM grains, and the capacity of the SRAM grains is greater than or equal to 0.5K.

Optionally, the SRAM module further includes Q second SRAM sub-blocks, the second SRAM sub-blocks are configured to store data with a distribution density of the matching strings smaller than a second threshold, each second SRAM sub-block has a fifth number of second ports, one matching string can be read at a time through two adjacent second ports, the fifth number is equal to twice the number of matching strings to be read from the second SRAM sub-block, and Q is a positive integer.

Optionally, the second sub-block of SRAM comprises a fifth number of SRAM grains, and the capacity of the SRAM grains is greater than or equal to 0.5K.

(III) advantageous effects

The invention provides a memory for a lossless compression hardware circuit, which is constructed by combining a register module and an SRAM module according to the distribution characteristics of matched character strings in compressed data. The register module is used for storing compressed data containing matching character string distribution density larger than or equal to a first threshold value, the SRAM module is used for storing compressed data containing matching character string distribution density smaller than the first threshold value, so that the requirement that different storage intervals of the LZ77 compression algorithm have different data reading groups in the search buffer is met, and further the data reading and writing efficiency and the data compression speed in the lossless compression process are improved. In addition, according to the memory provided by the invention, a higher data reading speed can be realized by using a smaller circuit area, and the manufacturing cost of hardware is further reduced.

Drawings

FIG. 1 is a diagram illustrating the distribution of matching strings in a look-up buffer;

FIG. 2 is a schematic diagram of a memory structure for lossless compression hardware circuitry in an embodiment of the invention;

FIG. 3 is a diagram illustrating a distribution of the number of matching strings in an embodiment of the present invention;

FIG. 4 is a diagram illustrating a register module according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating the distribution of the number of matching strings in another embodiment of the present invention;

FIG. 6 is a schematic structural diagram of an SRAM module according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.

In the implementation of a lossless data compression process based on the compression algorithm LZ77, the inventors found that the distribution of matching strings in compressed data is characterized by: for a target string that needs to be compression encoded, it is easier to find a matching string at a position in the look-up buffer that is closer to it.

For example, as shown in the distribution diagram of the matching character strings in the search buffer of fig. 1, the target character string is used as an origin, the horizontal axis represents the relative distance between the storage location in the search buffer and the target character string, and the vertical axis represents the distribution ratio of the matching character strings. When the storage capacity of the search buffer is 31K, the distribution proportion of the matching character strings in different unit storage intervals is different, namely the distribution density of the matching character strings in the search buffer is different. The search buffer can be divided into a plurality of unit storage intervals with equal size, and the number of the matching character strings contained in each unit storage interval is called as the distribution density of the matching character strings. Therefore, the number of the matched character string groups which need to be read from different storage spaces of the search buffer in unit time is different, and a memory aiming at an LZ77 algorithm in a traditional GZIP hardware circuit in a compression mode often cannot well adapt to the characteristics of the LZ77 algorithm. The traditional memory is built by using an SRAM (static random access memory), usually only 2 ports are supported, the requirement of multi-port data reading cannot be met, and the data reading efficiency is low. If the register is used for building the memory, the requirement of multi-port data reading can be met, but the area of a hardware circuit is large. Therefore, a memory applied to the technical field of lossless compression in the prior art cannot meet the requirement of the LZ77 algorithm on the port reading rate, and cannot simultaneously take into account the influence on the hardware circuit area and the control on the cost and the like.

In order to solve the above problems, the present invention provides a new memory structure for storing compressed data, so as to implement the data access function of the lookup buffer. As shown in fig. 2, a schematic diagram of a memory structure for lossless compression hardware circuit according to an embodiment of the present invention, according to distribution characteristics of matching strings in compressed data, a memory 201 according to the present invention is constructed by combining a register module 210 and an SRAM module 220. The register module 210 is configured to store compressed data having a matching string distribution density greater than or equal to a first threshold, and the SRAM module 220 is configured to store compressed data having a matching string distribution density less than the first threshold. It should be understood that the number of matching strings contained in a single data amount in compressed data is referred to as the distribution density of the matching strings. It will also be appreciated that the division of the compressed data within the memory (i.e. the determination of the first threshold) needs to be determined based on the statistical properties of the matching strings in the compressed data and the capacity of the memory.

The register module includes a basic module that can realize the function of a register, and the SRAM module includes a module that can store data through a transistor. In the embodiment of the invention, both the register module and the SRAM module can realize the read-write operation of the compressed data in the memory so as to finish the storage and the data read-write of the compressed data in the memory. The register module can realize high read-write speed of the data port; the SRAM module can ensure that the SRAM memory area of unit memory capacity is smaller under the condition of larger memory capacity. For example, in the embodiment of the present invention, during the data compression process of the character string to be compressed (i.e., the target character string) in the look-ahead buffer, according to the storage address where each character string (i.e., the matching character string) that is the same as the first 3 or more characters of the target character string (i.e., the target character string) is located in the memory, the matching character strings matched with each target character string are respectively read from the corresponding storage addresses, so as to obtain the matching character string with the largest number of identical characters.

According to the technical scheme of the embodiment of the invention, the requirements of different data reading groups of the LZ77 compression algorithm in different storage intervals of the search buffer are met through the combination of the register module and the SRAM module, and the data reading and writing efficiency and the data compression speed in the lossless compression process can be improved.

And dividing the memory into a plurality of storage subintervals according to the distance relationship between the storage position of the compressed data in the memory and the target character string to be compressed, so as to conveniently store the compressed data of the memory in the subareas. The distribution density of matching strings in various portions of the memory and the method of determining the first threshold value according to an embodiment of the present invention will be described in detail below with reference to fig. 3.

FIG. 3 is a diagram illustrating a distribution of the number of matching strings according to an embodiment of the present invention. As shown in fig. 3, the horizontal axis represents the relative distance (hereinafter, simply referred to as the relative distance) between the storage location in the memory and the target character string location in the look-ahead buffer, and the vertical axis represents the number of matching character strings corresponding to the relative distance. Where a and b are positive numbers and are related to the size of the look-up buffer. As can be seen from fig. 3, the number of matching distribution character strings in the unit storage section having the relative distance of less than or equal to 2aK is significantly larger than the number of matching distribution character strings in the unit storage section having the relative distance of more than 2aK, that is, the distribution density of the matching character strings is abruptly decreased at the storage location having the relative distance of 2 aK. At this time, we refer to the relative distance corresponding to the position where the sudden decrease occurs as the first distance, and the distribution density of the matching character string corresponding to the first distance as the first threshold. As can be seen from fig. 3, at this time, the first distance is 2aK, and the distribution density of the matching character strings corresponding to the first distance is the first threshold. After the first threshold is determined, the compressed data in the memory may be divided into a first portion having a distribution density greater than or equal to the first threshold and a second portion having a distribution density less than the first threshold. At this time, the memory (i.e., register module) built by the register stores the compressed data of the first part, and the memory (i.e., SRAM module) built by the SRAM stores the compressed data of the second part.

The memory is constructed by combining a register module and an SRAM module. The register module is used for storing compressed data with the matching character string distribution density being larger than or equal to a first threshold value so as to meet the requirement that the LZ77 compression algorithm has different data reading groups in different storage intervals of the search buffer. The SRAM module is used for storing compressed data with the distribution density of the matching character strings smaller than a first threshold value, can realize higher data reading speed by using smaller circuit area, and can realize control on the manufacturing cost of hardware.

In one embodiment of the present invention, the register module includes M register sub-blocks, each having a first number of first ports, wherein one match string can be read at a time through one first port, the first number is equal to the number of match strings to be read from the register sub-block, and M is a positive integer. The number of matching strings in the register sub-block can be predicted approximately according to the statistical characteristics of the matching strings in the compressed data, and the number of the matching strings to be read from the register sub-block is approximately equal to the number of the matching strings in the register sub-block. For example, in implementing the technical solution of the present invention, the value of the first number may be predicted and set so as to be approximately equal to the number of matching strings stored in the register subblock revealed by statistical experience, based on the statistical experience of the distribution density of the matching strings in the past.

Specifically, in an embodiment of the present invention, if the compressed data of the lookup buffer is divided into two parts according to a first threshold as a boundary, a register having a first number of first ports is constructed as a register module, and the register module is configured to store a first part of the compressed data. When the register module is constructed with M register sub-blocks to store the first portion of compressed data, the register sub-blocks have a first number of first ports. The first port can read one matching character string at a time, and the first number is equal to the number of the matching character strings to be read from the register sub-blocks. Namely, equivalently, a port is correspondingly arranged for each group of matched character strings, so that the data reading and writing efficiency can be greatly improved. First register sub-block 410 in one embodiment of the invention, the capacity of the register sub-block is greater than or equal to 1K. As shown in table 1, the relationship between the register capacity R, the number P of register ports, and the register area S in the embodiment of the present invention is a positive correlation between the register area S, the register capacity R, and the number P of register ports. By combining the distribution characteristics of the matched character strings, when the capacity of the register subblocks is larger than or equal to 1K, the port number of each register subblock can better cope with the fluctuation of character string distribution, and the overall reading efficiency of the memory is improved.

Table 1

FIG. 4 is a diagram illustrating a structure of a register module according to an embodiment of the present invention. As shown in FIG. 4, in one embodiment of the present invention, when M equals 2, the register module includes a first register sub-block 410 and a second register sub-block 420. The first register sub-block 410 has a capacity of 1K, and the first register sub-block 410 has 32 first ports. The second register sub-block 420 has a capacity of 2K, and the second register sub-block 420 has 16 first ports. Specifically, in the embodiment of the present invention, the first distance is 3K, the first threshold is 6 groups/K, and the register module is built as follows:

in a storage sub-interval from 0 to 1K of the target character string, the distribution density of the matching character string in the interval is about 32 groups/K, and 32 groups of matching characters need to be read in one period of the storage sub-interval, that is, at least 32 ports need to be set for the storage sub-interval. According to the relationship between the register area S, the register capacity R, and the number P of register ports shown in table 1, in order to make the memory construction area S as small as possible and satisfy the requirement of the number P of ports, a first register sub-block 410 is constructed with R being 1K and P being 32. Correspondingly, in a storage subinterval 1-3K away from the target character string, the distribution density of the matching character string in the interval is about 6 groups/K, and 12 groups of matching characters need to be read in one cycle of the storage subinterval, that is, at least 12 ports need to be set for the storage subinterval, so that the second register subinterval 420 with R being 2 and P being 16 is used for building. The register module is constructed by combining a first register sub-block with the capacity of 1K and the number of ports of 32 with a second register sub-block with the capacity of 2K and the number of ports of 16, so that the requirements of different data reading groups of different storage intervals by an LZ77 compression algorithm are met.

In one embodiment of the invention, the SRAM module comprises N SRAM sub-blocks having a second number of second ports, wherein one matching string can be read at a time through two adjacent second ports, the second number being equal to twice the number of matching strings to be read from the SRAM sub-blocks, N being a positive integer. Specifically, in an embodiment of the present invention, if the compressed data in the lookup buffer is divided into two parts according to the first threshold as a boundary, the SRAM module is configured to store a second part of the compressed data, where the SRAM module is built by an SRAM sub-block, and the SRAM sub-block has a second number of second ports. It should be noted that the first 3 or more characters of the matching string may not be located at the beginning of the compressed data read from the SRAM sub-block, and the longest matching string may span the storage space of two adjacent SRAM sub-blocks. In order to read out the longest matching character string smoothly, two adjacent second ports may be provided for each group of matching character strings for reading. At this time, the number of the second ports (i.e., the second number) of the SRAM sub-block is equal to twice the number of the matching strings to be read from the SRAM sub-block. The SRAM module in the memory is constructed by combining the N SRAM subblocks, so that the requirement for reading the compressed data of the second part can be met by using a smaller circuit area, and the manufacturing cost of hardware is reduced.

In one embodiment of the invention, the SRAM sub-block includes a second number of SRAM grains, the SRAM grains being the smallest units that make up the SRAM sub-block. The capacity of the SRAM grain is greater than or equal to 0.5K in consideration of the size of the hardware area. Wherein each SRAM grain includes a second port, and the number of SRAM grains in the SRAM sub-block is equal to the number of second ports (i.e., the second number) of the SRAM sub-block.

In one embodiment of the invention, the SRAM module includes L SRAM first sub-blocks and copies of the L SRAM first sub-blocks. Each SRAM first sub-block in the L SRAM first sub-blocks is provided with one copy. The SRAM first sub-block is used for storing data of which the distribution density of the matching character strings is greater than or equal to a second threshold value and smaller than a first threshold value. The copy is used for storing the same data as the copied SRAM first sub-block, and L is a positive integer. The replica has a third number of second ports and the replicated SRAM first sub-block has a fourth number of second ports. And the matching character strings can be read one at a time through two adjacent second ports, and the sum of the third number and the fourth number is equal to twice of the number of the matching character strings to be read from the SRAM first sub-block.

When the storage space required for the second portion of the compressed data is large, setting the capacity of each SRAM granule to 0.5K does not satisfy the read requirement for the second portion of the compressed data. At this time, the second portion smaller than the first threshold may be further divided. The division method is similar to the method of dividing the compressed data into the first part and the second part according to the first threshold. FIG. 5 is a diagram illustrating the distribution of matching strings according to another embodiment of the present invention.

As shown in fig. 5, the distribution density of the matching character strings corresponding to the storage locations with the relative distance of 6aK is suddenly decreased, and the storage locations with the relative distance of 6aK are referred to as the second distance. The distribution density of the matching character strings corresponding to the second distance is a second threshold value. After the second threshold value is determined, a second part of the compressed data is divided into a part A and a part B, wherein the distribution density of the part A containing the matching character strings is greater than or equal to the second threshold value and smaller than the first threshold value, and the distribution density of the part B containing the matching character strings is smaller than the second threshold value. The part A can be constructed in a mode of matching the first SRAM sub-block with a copy of the first SRAM sub-block (hereinafter referred to as copy), and the data stored in the copy is the same as the data stored in the copied first SRAM sub-block. The replica has a third number of second ports and the replicated SRAM first sub-block has a fourth number of second ports. And considering that the longest matching character string spans the storage space of two adjacent SRAM subblocks, setting two adjacent second ports for each group of matching character strings to read. Therefore, the total port number of the copied copies and the first sub-block of the copied SRAM, i.e. the sum of the third number and the fourth number, is equal to twice the number of the matching strings to be read from the first sub-block of the SRAM. The plurality of copies may have compressed data repeated therein, and the number of copies is not limited, and when the number of copies is plural, the number of second ports of the plurality of copies is summed to a third number.

In one embodiment of the present invention, the first distance is 3K, the first threshold is 6 groups/K, the second distance is 16K, the second threshold is 2 groups/K, and the compressed data a portion contains the distribution density of the matching character strings of 2 groups/K or more and less than 6 groups/K. The SRAM module for storing the part A is built by L SRAM first sub-blocks and copies, and L is equal to 2 at the moment. FIG. 6 is a schematic structural diagram of an SRAM module according to an embodiment of the present invention. As shown in fig. 6, the SRAM module includes a first sub-block 610 of SRAM0 and 3 copies of the first sub-block 610 of SRAM0 (i.e., copy a, copy B, and copy C), and a first sub-block 620 of SRAM1 and 1 first sub-block 620 of SRAM1 (i.e., copy a).

In this case, the distribution density of the matching character strings of the compressed data in the storage subinterval from 3 to 8K of the target character string is about 4 groups/K, and 20 groups of matching characters need to be read in one period of the storage subinterval. To satisfy the reading requirement of the matching character string, the storage sub-section is implemented by using the first sub-block of SRAM0 with the capacity of 5K, wherein the number of the second ports (i.e. the fourth number) of the first sub-block 610 of SRAM0 is 10. The first sub-block of the 3-bank SRAM0 is copied as copy a611, copy B612, copy C613 at the same time, and the number of second ports (i.e., the third number) of the 3 copies is 30. Two adjacent second ports can read one of the matching strings at a time. Therefore, when the sum of the third number and the fourth number is 40, the requirement that 20 sets of matching character strings need to be read in one cycle is satisfied.

In a storage sub-interval 8-16K away from the target character string, the distribution density of the matching character strings of the compressed data in the storage sub-interval is about 2 groups/K, and 16 groups of matching characters need to be read in one period of the storage sub-interval. To meet the read requirement of the matching string, the storage subinterval is implemented by using the first sub-block 620 of the SRAM1 with the capacity of 8K. The number of the second ports (i.e., the fourth number) of the first sub-block 620 of the SRAM1 is 16. The first sub-block of 1 set of SRAM1 is also copied as copy a621, the second port number (i.e., the third number) of which is 16. Two adjacent second ports can read one of the matching strings at a time. Therefore, when the sum of the third number and the fourth number is 32, the requirement that 16 sets of matching character strings need to be read in one cycle is satisfied.

According to the embodiment of the SRAM module, a higher data reading rate can be realized by using a smaller circuit area, and the manufacturing cost of hardware can be controlled.

In one embodiment of the present invention, the replica of the first sub-block of SRAM comprises a third number of SRAM grains, the first sub-block of SRAM comprises a fourth number of SRAM grains, and the capacity of the SRAM grains is greater than or equal to 0.5K. Wherein each SRAM grain comprises a second port, the number of SRAM grains in the first SRAM sub-block is equal to the number of second ports (i.e., the fourth number) in the first SRAM sub-block, and the number of SRAM grains in the replica of the first SRAM sub-block is equal to the number of second ports (i.e., the third number) in the replica of the first SRAM sub-block.

In an embodiment of the present invention, the SRAM module further includes Q second SRAM sub-blocks, the second SRAM sub-blocks are configured to store data with a distribution density of the matching strings smaller than the second threshold, the second SRAM sub-blocks have a fifth number of second ports, wherein one matching string can be read at a time through two adjacent second ports, the fifth number is equal to twice the number of matching strings to be read from the second SRAM sub-block, and Q is a positive integer.

Specifically, in the embodiment of the present invention, the second distance is 16K, the second threshold is 2 groups/K, and the compressed data B portion contains the matching character strings with a distribution density less than 2 groups/K. The SRAM module for storing part B is built by Q SRAM second sub-blocks, and Q is equal to 1. In a storage sub-interval from 16K to 32K of the target character string, the distribution density of the matching character strings of the compressed data in the storage sub-interval is about 0.5 group/K, and 8 groups of matching characters need to be read in one period of the storage sub-interval. To meet the reading requirement of the matching character string, the storage subinterval is implemented by using the SRAM second sub-block 710 with the capacity of 16K, and the number of the second ports (i.e., the fifth number) of the SRAM second sub-block is 16. Two adjacent second ports can read one matching character string at a time, and when the sum of the fifth number is 16, the requirement that 8 groups of matching character strings need to be read in one period is met.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.