阅读说明：本技术 触发器电路 (Flip-flop circuit ) 是由 赖柏嘉 斯帝芬·鲁苏 于 2021-07-30 设计创作，主要内容包括：触发器电路包括第一主部分、第二主部分、至少一个判定部分和从部分。第一主部分被配置为在第一模式下操作以及接收第一输入并生成第一主输出。第二主部分被配置为在第二模式下操作以及接收第二输入并生成第二主输出。至少一个判定部分被配置为接收至少一个使能信号,并且具有判定输入和判定输出。判定输入连接到第一主输出和第二主输出。判定部分被配置为根据至少一个使能信号判定判定输出为第一主输出或第二主输出。从部分被配置为接收判定输出并生成输出信号。(The flip-flop circuit includes a first master portion, a second master portion, at least one decision portion, and a slave portion. The first primary portion is configured to operate in a first mode and to receive a first input and generate a first primary output. The second primary portion is configured to operate in a second mode and to receive a second input and generate a second primary output. The at least one decision portion is configured to receive at least one enable signal and has a decision input and a decision output. The decision input is connected to the first and second primary outputs. The determination section is configured to determine whether the determination output is the first main output or the second main output based on at least one enable signal. The slave portion is configured to receive the decision output and generate an output signal.)

1. A flip-flop circuit comprising:

a first primary section configured to operate in a first mode and to receive a first input and generate a first primary output;

a second primary portion configured to operate in a second mode and to receive a second input and generate a second primary output;

at least one decision portion configured to receive at least one enable signal and having a decision input and a decision output, the decision input being connected to the first main output and the second main output, the decision portion being configured to decide that the decision output is the first main output or the second main output depending on the at least one enable signal; and

a slave portion configured to receive the decision output and generate an output signal.

2. The flip-flop circuit of claim 1, wherein the first mode is a test mode and the second mode is a normal mode, the first input is a scan input signal and the second input is a data signal, the at least one enable signal comprising a scan enable signal and an inverted scan enable signal.

3. The flip-flop circuit of claim 1, wherein the first master portion comprises a first cross-coupled or and inverter (OAI) logic gate pair and a first master inverter, and the second master portion comprises a second cross-coupled or and inverter (OAI) logic gate pair and a second master inverter, and the slave portion comprises a cross-coupled and or inverter (AOI) logic gate pair and a slave inverter.

4. The flip-flop circuit of claim 1, wherein the first master portion comprises a first cross-coupled pair of and-inverter (AOI) logic gates and a first master inverter, and the second master portion comprises a second cross-coupled pair of and-inverter (AOI) logic gates and a second master inverter, and the slave portion comprises a cross-coupled pair of or-inverter (OAI) logic gates and a slave inverter.

5. The flip-flop circuit of claim 1, wherein the flip-flop circuit comprises a first decision portion having a first decision input connected to the first main output and a first decision output connected to the decision output, and a second decision portion having a second decision input connected to the second main output and a second decision output connected to the decision output.

6. The flip-flop circuit according to claim 5, wherein the first determination portion includes a plurality of transistors controlled by the at least one enable signal, and the second determination portion includes a plurality of transistors controlled by the at least one enable signal, the at least one enable signal including a scan enable signal and an inverted scan enable signal.

7. The flip-flop circuit of claim 1, further comprising: a time-shifting portion coupled to the first master portion and the second master portion for delaying clock signals of the first master portion and the second master portion, which are connected to the slave portion without the time-shifting portion, by a predetermined time.

8. A flip-flop circuit comprising:

a first main section configured to operate in a first mode and to receive a first input and to generate a first main output, the first main section having a first enable section for enabling the first main section in accordance with at least one enable signal;

a second main section configured to operate in a second mode and to receive a second input and to generate a second main output, the second main section having a second enable section for enabling the second main section second enable section according to the at least one enable signal; and

a slave portion configured to receive the first or second master output and generate an output signal.

9. The flip-flop circuit of claim 8, wherein the first mode is a test mode and the second mode is a normal mode, the first input is a scan signal and the second input is a data signal, the at least one enable signal comprising a scan enable signal and an inverted scan enable signal.

10. A flip-flop circuit comprising:

a main portion configured to receive at least one first input, at least one second input, and at least one enable signal, and to generate a main output, the main portion including a plurality of control portions configured to control the main portion to operate in a first mode or a second mode according to the at least one first input, the at least one second input, and the at least one enable signal; and

a slave portion configured to receive the master output and generate an output signal.

Technical Field

Embodiments of the present invention relate to a flip-flop circuit.

Background

The flip-flop circuit is used to store data. By controlling the power, performance, and manufacturing area characteristics of the flip-flop (e.g., by limiting the number of components used to implement the flip-flop), faster, more power efficient flip-flops may be implemented using less circuit manufacturing space.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided a flip-flop circuit including: a first primary section configured to operate in a first mode and to receive a first input and generate a first primary output; a second primary portion configured to operate in a second mode and to receive a second input and generate a second primary output; at least one decision section configured to receive at least one enable signal and having a decision input and a decision output, the decision input being connected to the first main output and the second main output, the decision section being configured to decide the decision output as the first main output or the second main output depending on the at least one enable signal; and a slave portion configured to receive the decision output and generate an output signal.

According to another aspect of an embodiment of the present invention, there is provided a flip-flop circuit including: a first main section configured to operate in a first mode and to receive a first input and to generate a first main output, the first main section having a first enable section for enabling the first main section in accordance with at least one enable signal; a second main section configured to operate in a second mode and to receive a second input and to generate a second main output, the second main section having a second enable section for enabling the second main section second enable section according to at least one enable signal; and a slave portion configured to receive the first or second master output and generate an output signal.

According to still another aspect of an embodiment of the present invention, there is provided a flip-flop circuit including: a main section configured to receive at least one first input, at least one second input, and at least one enable signal, and generate a main output, the main section including a plurality of control sections configured to control the main section to operate in a first mode or a second mode according to the at least one first input, the at least one second input, and the at least one enable signal; and a slave portion configured to receive the master output and generate an output signal.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates a gate level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure.

Fig. 2 illustrates an exemplary circuit diagram of an or-inverter (OAI) logic gate and an and-inverter (AOI) logic gate and corresponding truth table according to some embodiments of the present disclosure.

Fig. 3 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure.

Fig. 4 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure.

Fig. 5 illustrates a transistor-level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure.

Fig. 6 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure.

Fig. 7 illustrates a transistor-level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure.

Fig. 8 illustrates a transistor level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure.

Fig. 9 illustrates a transistor level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure.

Fig. 10 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure.

Fig. 11 illustrates a transistor level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure.

Fig. 12 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure.

Fig. 13 is a flow diagram illustrating a method for operating a flip-flop circuit, according to some embodiments of the present disclosure.

Fig. 14 is a flow diagram illustrating a method for operating a flip-flop circuit, according to some embodiments of the present disclosure.

Fig. 15 is a flow diagram illustrating a method for operating a flip-flop circuit, according to some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, for ease of description, spaced relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. The term spaced relationship is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relationship descriptors used herein interpreted accordingly as such.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the term "about" generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Except in the operating/working examples, or where otherwise expressly indicated, all numerical ranges, amounts, values and percentages, such as those for amounts of materials, durations, temperatures, operating conditions, quantitative ratios, and the like, are to be understood as modified in any instance by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary depending upon the desired properties. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to another end point or between two end points. All ranges disclosed herein are inclusive of the endpoints unless otherwise indicated.

A flip-flop circuit implementation may use one or more signal inversions from a scan multiplexer that is multiplexed to select the scan input and the data input. This inversion of the scan multiplexer takes time and effort to complete, while the components used to implement these inversions and the pass gates used to implement the flip-flops require circuit area. Limiting circuit components may improve circuit power, performance, and area characteristics. According to some embodiments of the present disclosure, a flip-flop circuit may reduce signal inversion on a signal path by replacing or merging scan multiplexers to make the flip-flop circuit faster and reduce power consumption and design complexity.

Fig. 1 illustrates a gate level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure. Referring to fig. 1, the flip-flop circuit 10 includes a first master portion 11, a second master portion 12, at least one decision portion 13, 14, and a slave portion 15. The first main section 11 is configured to operate in a first mode and receive a first input 111 and generate a first main output 112. The second main section 12 is configured to operate in a second mode and receive a second input 121 and generate a second main output 122. According to some embodiments of the present disclosure, the first mode may be a test mode and the second mode may be a normal mode. The first input 111 may be a scan Signal (SI) and the second input 121 may be a data signal (D).

According to some embodiments of the present disclosure, when the first main portion 11 operates in the test mode, the first main portion 11 receives the scan input signal 111 and generates the first main output 112 (scan output signal). In some embodiments, a failure of one or more flip-flop circuits (i.e., one or more failing flip-flop circuits) may be detected by comparing one or more differences between the scan-in signal 111 and the scan-out signal 112. Such a fail flip-flop circuit may be used to ascertain which respective subset of logic gates is failing. According to some embodiments of the present disclosure, the scan in signal 111 may be used to provide the scan test described above. In some embodiments, as described above, the scan input signal 111 may include one or more test patterns for detecting a failure of the flip-flop circuit. Such a scan input signal 111 may be provided by an Automatic Test Pattern Generation (ATPG) technique.

According to some embodiments of the present disclosure, when the second main part 12 operates in the normal mode, the second main part 12 receives data signals 121 provided from a respective subset of logic gates of the circuit under test. According to some embodiments of the present disclosure, data signals 121 may include data generated based on the logical operations of a respective subset of logic gates.

According to some embodiments of the present disclosure, the first master portion 11 comprises a first cross-coupled or and inverter (OAI) logic gate pair 113 and a first master inverter 114, and the second master portion 12 comprises a second cross-coupled or and inverter (OAI) logic gate pair 123 and a second master inverter 124, and the slave portion 15 comprises a cross-coupled and or inverter (AOI) logic gate pair 153 and a slave inverter 154. The term "cross-coupled" as used herein means that the two OAIs of the first pair of cross-coupled or inverter (OAI) logic gates 113 each include an output coupled to an input of the other. Similarly, two of the second cross-coupled or inverter (OAI) pair of logic gates 123 each include an output coupled to the other input, and the cross-coupled or inverter (AOI) pair of logic gates 153 each include an output coupled to the other input.

According to some embodiments of the present disclosure, a first cross-coupled or inverter (OAI) logic gate pair 113 is coupled to the first input (scan input signal) 111, the output of the first inverter 114, and the clock signal CP. Similarly, a second cross-coupled or inverter (OAI) pair of logic gates 123 is coupled to the second input (data signal) 121, the output of the first inverter 124, and the clock signal CP. The first pair of cross-coupled or inverter (OAI) logic gates 113 and the second pair of cross-coupled or inverter (OAI) logic gates 123 are configured to perform an "OAI" logic function. A cross-coupled and or inverter (AOI) logic gate pair 153 is coupled to the slave input 151 and the clock signal CP. The cross-coupled and-or inverter (AOI) logic gate pair 153 is configured to perform an AOI logic function.

Fig. 2 illustrates an exemplary circuit diagram of an or-inverter (OAI) logic gate and an and-inverter (AOI) logic gate and corresponding truth table according to some embodiments of the present disclosure. In FIG. 2, the OAI and AOI are shown along with their respective truth tables (OAI truth table and AOI truth table). According to some embodiments of the present disclosure, the two OAIs of the first cross-coupled or inverter (OAI) logic gate pair 113 each have substantially similar functionality to the OAIs of fig. 2. As shown in fig. 2, both OAIs of the second cross-coupled or inverter (OAI) logic gate pair 123 each have substantially similar functionality to the OAIs of fig. 2. Thus, each OAI may perform the above-described OAI logic functions using a corresponding truth table (i.e., an "OAI truth table") as shown in fig. 2. Similarly, each of the pair of cross-coupled and-or inverter (AOI) logic gates 153 has a substantially similar function to the AOI in fig. 2. Thus, each AOI may perform the AOI logic function described above using a truth table (i.e., an "AOI truth table") as shown in FIG. 2.

Referring to fig. 1 and 2, according to some embodiments of the present disclosure, one of a first cross-coupled or inverter (OAI) logic gate pair may use a first input (scan signal) 111 as a₁₁Using the clock signal CP as A₁₂And one of the main outputs 112 as B₁₁And the other is as followsA main output 112 as output C₁₁The logic state of the other first main output 112 is determined by the OAI truth table and the combination of the logic states of signals 111, CP and 112. For example, according to the OAI truth table, when the logic states of the signals 111, CP and 112 are logic "1", logic "0" and logic "1", respectively, the other main output 112 is logic "0". One of the second cross-coupled and inverter (OAI) pair of logic gates 123 may use the second input (data signal) 121 as a₁₁Using the clock signal CP as A₁₂And one of the second main outputs 122 is used as B₁₁And another second main output 122 as output C₁₁The logic state of the other second main output 122 is determined by the OAI truth table and the combination of the logic states of signals 121, CP and 122. The AOI of a cross-coupled AND-OR inverter "(AOI) logic gate pair 153 may use one slave input 151 as A₂₁Using the clock signal CP as A₂₂Using a slave output 155 as B₂₁And the other using slave output 155 as output C₂₁The logic state of the other slave output 155 is determined by the AOI truth table and the combination of the logic states of signals 151, CP, and 155.

According to some embodiments of the present disclosure, the at least one decision section 13, 14 is configured to receive the at least one enable signal SE/seb and has a decision input and a decision output. The decision input is connected to the first and second primary outputs. The at least one decision section is configured to decide whether the decision output is the first main output or the second main output in accordance with the at least one enable signal SE/seb.

According to some embodiments of the present disclosure, the flip-flop circuit 10 includes a first decision portion 13 and a second decision portion 14. The first decision section 13 has a first decision input 131 and a first decision output 132. The first decision input 131 is connected to the first main output 112. The first decision output 132 is connected to the decision output EO. The second decision section 14 has a second decision input 141 and a second decision output 142. The second decision input 141 is connected to the second main output 122. The second decision output 142 is connected to the decision output EO.

According to some embodiments of the present disclosure, the at least one enable signal includes a scan enable Signal (SE) and an inverted scan enable signal (seb).

According to some embodiments of the present disclosure, the first determination portion 13 includes a plurality of transistors controlled by a scan enable Signal (SE) and an inverted scan enable signal (seb). The second determination section 14 includes a plurality of transistors controlled by the scan enable Signal (SE) and the inverted scan enable signal (seb). Therefore, the first and second determination portions 13 and 14 are configured to determine the determination output EO as the first or second main output 112 or 122 from the scan enable Signal (SE) and the inverted scan enable signal (seb). For example, the first decision portion 13 may couple the first primary output 112 to the first decision output 132 when the scan enable Signal (SE) is asserted to a logic high state (e.g., a logic "1"). The second decision section 14 is deactivated. Therefore, the determination output EO is the first main output 112. When the scan enable Signal (SE) is asserted to a logic low state (e.g., a logic "0"), the second decision portion 14 may couple the second main output 122 to the second decision output 142. The first decision section 13 is deactivated. Therefore, the determination output EO is the second main output 122.

According to some embodiments of the present disclosure, the decision output EO is connected to the slave input 151 of the slave portion 15. The slave portion 15 is configured to generate an output signal 152 based on the slave input 151 and the clock signal CP.

According to some embodiments of the present disclosure, the AOIs of the first cross-coupled or inverter (OAI) logic gate pair 113 and the second cross-coupled or inverter (OAI) OAI logic gate pair 123 and the cross-coupled and or inverter (AOI) logic gate pair 153 may be complementarily activated according to the clock signal CP. When the clock signal CP transitions from a low logic state to a high logic state (i.e., the clock signal CP is in a high logic state), the first pair of cross-coupled or and inverter (OAI) logic gates 113 and the second pair of cross-coupled or and inverter (OAI) logic gates 123 are activated, while the pair of cross-coupled or and inverter (AOI) logic gates 153 is deactivated. In this way, the first main part 11 may latch the first input (scan signal) 111 to the output signal 152, or the second main part 12 may latch the second input (data signal) 121 to the output signal 152. The cross-coupled and or inverter (AOI) logic gate pair 153 may be used as a transparent circuit. When the clock signal CP transitions from a high logic state to a low logic state (i.e., the clock signal CP is in a low logic state), the first pair of cross-coupled or and inverter (OAI) logic gates 113 and the second pair of cross-coupled or and inverter (OAI) logic gates 123 are deactivated, and on the other hand, the pair of cross-coupled or and inverter (AOI) logic gates 153 is activated. In this way, the slave portion 15 can latch the first input (scan signal) 111 or the second input (data signal) 121 directly to the output signal 152, and the first main portion 11 and the second main portion 12 can function as a transparent circuit.

According to some embodiments of the present disclosure, by using a first cross-coupled or inverter (OAI) logic gate pair 113, a second cross-coupled or inverter (OAI) logic gate pair 123, and a cross-coupled and or inverter (AOI) logic gate pair 153 in the flip-flop circuit 10, the clock signal CP of the flip-flop circuit 10 may be used by the first cross-coupled or inverter (OAI) logic gate pair 113, the second cross-coupled or inverter (OAI) logic gate pair 123, and the cross-coupled or inverter (AOI) logic gate pair 153. In this way, a logical inverted clock signal and corresponding components (e.g., one or more inverters) for generating such a logical inverted clock signal may not be required, which may advantageously reduce power consumption and design complexity of the flip-flop circuit 10. Further, as shown in fig. 1, the first cross-coupled or and inverter (OAI) logic gate pair 113 is symmetrical to each other, the second cross-coupled or and inverter (OAI) logic gate pair 123 is also symmetrical to each other, and the cross-coupled and or inverter (AOI) logic gate pair 153 is also symmetrical to each other. By using this symmetrical characteristic of the cross-coupled OAI and AOI of the flip-flop circuit 10, respectively, the number of transistors used to implement the OAI and AOI, respectively, can be greatly reduced compared to conventional flip-flop circuits using transmission gates. The reduced number of transistors may further reduce the power consumption and design complexity of the flip-flop circuit 10.

According to some embodiments of the present disclosure, by using the first and second decision parts 13 and 14, the first main output 112 from the first main part 11 or the second main output 122 from the second main part 12 may be decided. Thus, a conventional multiplexer disposed before a conventional master latch circuit may not be required, which may advantageously allow for faster speed (e.g., approximately 7%) of the flip-flop circuit 10.

Fig. 3 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure. Referring to fig. 3, the flip-flop circuit 20 includes a first main portion 21, a second main portion 22, a first decision portion 23, a second decision portion 24, and a slave portion 25. The first main section 21 is configured to operate in a first mode and receive a first input 211 and generate a first main output 212. The second main section 22 is configured to operate in a second mode and receive a second input 221 and generate a second main output 222. The first mode may be a test mode and the second mode may be a normal mode. The first input 211 may be a scan Signal (SI) and the second input 221 may be a data signal (D). Referring to fig. 1 and 3, each gate-level component (11, 12, and 15) of the flip-flop circuit 10 in fig. 1 is configured to correspond to each gate-level component (11, 12, and 15) in fig. 3. The embodiment of fig. 1 may be implemented by one or more transistors in fig. 3. It will be appreciated that the circuit diagram shown in fig. 3 is merely an example of a gate level component that implements the flip-flop circuit 10. Each gate-level component of the flip-flop circuit 10 may be implemented by any of a variety of circuit designs while remaining within the scope of the present invention.

According to some embodiments of the present disclosure, the first master portion 21 comprises a first cross-coupled or and inverter (OAI) logic gate pair 213 and a first master inverter 214, and the second master portion 22 comprises a second cross-coupled or and inverter (OAI) logic gate pair 223 and a second master inverter 224, and the slave portion 25 comprises a cross-coupled and or inverter (AOI) logic gate pair 253 and a slave inverter 254. The first cross-coupled or inverter (OAI) logic gate pair 213 may be implemented by a plurality of transistors to perform an "OAI" logic function, and the first master inverter 214 may be implemented by two slave transistors 254 to perform an "inverter" logic function. For example, the two transistors of the first master inverter 214 are connected in series between a first supply voltage (e.g., Vdd) and a second supply voltage (e.g., ground). In some embodiments, one of the two transistors comprises a p-type metal oxide semiconductor (PMOS) transistor and the other transistor comprises an n-type metal oxide semiconductor (NMOS) transistor. Further, the gates of the transistors are commonly coupled to the first input 211 (scan signal SI), and the common node coupled to the respective drains of the transistors is configured to provide a signal that is logically inverted from the first input 211.

Similarly, the second cross-coupled or inverter (OAI) logic gate pair 223 may be implemented by a plurality of transistors to perform an "OAI" logic function, and the second master inverter 224 may be implemented by two transistors to perform an "inverter" logic function, according to some embodiments of the present disclosure. Further, the cross-coupled and-or inverter (AOI) logic gate pair 253 can be implemented by multiple transistors to perform an "AOI" logic function, and the slave inverter 254 can be implemented by two transistors to perform an "inverter" logic function.

According to some embodiments of the present disclosure, the first decision section 23 has a first decision input 231 and a first decision output 232. The first decision input 231 is connected to the first main output 212. The first decision output 232 is connected to the decision output EO. The second decision part 24 has a second decision input 241 and a second decision output 242. The second decision input 241 is connected to the second main output 222. The second decision output 242 is connected to the decision output EO.

According to some embodiments of the present disclosure, the first determination section 23 includes a plurality of transistors controlled by a scan enable Signal (SE) and an inverted scan enable signal (seb). The second decision part 24 includes a plurality of transistors controlled by the scan enable Signal (SE) and the inverted scan enable signal (seb). Accordingly, the first and second determination portions 23 and 24 are configured to determine whether the determination output EO is the first main output 212 or the second main output 222 based on the scan enable Signal (SE) and the inverted scan enable signal (seb). For example, when the scan enable Signal (SE) is asserted to a logic high state (e.g., a logic "1"), the first decision section 23 may couple the first main output 212 to the first decision output 232. Therefore, the determination output EO is the first main output 212. When the scan enable Signal (SE) is asserted to a logic low state (e.g., a logic "0"), the second decision portion 24 may couple the second main output 222 to the second decision output 242. Therefore, the determination output EO is the second main output 222.

According to some embodiments of the present disclosure, the decision output EO is connected to the slave input 251 of the slave portion 25. The slave portion 25 is configured to generate an output signal 252 based on the slave input 251 and the clock signal CP.

According to some embodiments of the present disclosure, by using the first and second decision parts 23 and 24, the first main output 212 from the first main part 21 or the second main output 222 from the second main part 22 may be decided. Thus, a conventional multiplexer disposed before a conventional master latch circuit may not be required, which may advantageously allow the speed of the flip-flop circuit 20 to be faster, e.g., about 7%.

Note that the above-described structures and other structures described herein are exemplary, and the scope of the present disclosure includes other examples. For example, an inverter (OAI) logic gate may be implemented as described at 213, 223, or may be implemented using other structures such as described in U.S. patent application No. 15/485,595 entitled "low power flip-flop circuit" or U.S. patent application No. 16/870,001 entitled "low power AOI based flip-flop," which are incorporated herein by reference in their entirety. And-or inverter (AOI) logic gates may be similarly implemented as depicted herein or described in the above-mentioned application.

For example, in U.S. patent application No. 15/485,595, a flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit comprises: a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated to latch the input signal to the output signal, and the first and second latch circuits respectively include at most two transistors configured to receive the clock signal. The first latch circuit comprises a pair of cross-coupled and-or-inverter (AOI) logic gates and the second latch circuit comprises a pair of cross-coupled or-and-inverter (OAI) logic gates.

For example, in U.S. patent application No. 16/870,001, a flip-flop circuit using an and or not (AOI) gate and an or not and (OAI) gate is disclosed, the circuit comprising: a multiplexer unit having a multiplexer that selects between a first signal and a second signal; a master unit having two or-not-and (OAI) gates, wherein a first one of the two or-not-and (OAI) gates is coupled between a first node (N1) and a third node (N3), and a second one of the two or-not-and (OAI) gates is coupled between a second node (N2) and a fourth node (N4); a slave cell having two AND-NOR (AOI) gates, wherein a first and NOR gate of the two AND-NOR (AOI) gates is coupled between the third node (N3) and a fifth node (N5), and a second and NOR gate of the two AND-NOR (AOI) gates is coupled between the fourth node (N4) and a sixth node (N6); and a clock for controlling the two AND-NOR gates and the two OR-NAND gates, wherein the clock is connected to the first and second AND-NOR gates and the first and second OR-NAND gates.

Fig. 4 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure. Referring to fig. 4, the flip-flop circuit 30 includes a first master portion 31, a second master portion 32, a first decision portion 33, a second decision portion 34, and a slave portion 35. The first main section 31 is configured to operate in a first mode and receive a first input 311 and generate a first main output 312. The second primary portion 32 is configured to operate in a second mode and receive a second input 321 and generate a second primary output 322. The first mode may be a test mode and the second mode may be a normal mode. The first input 311 may be a scan Signal (SI) and the second input 321 may be a data signal (D).

According to some embodiments of the present disclosure, the first master portion 31 comprises a first cross-coupled and-inverter (AOI) logic gate pair 313 and a first master inverter 314, and the second master portion 32 comprises a second cross-coupled and-inverter (AOI) logic gate pair 323 and a second master inverter 324, and the slave portion 35 comprises a cross-coupled or-inverter (OAI) logic gate pair 353 and a second pair of master inverters. The first cross-coupled and-or inverter (AOI) logic gate pair 313 may be implemented by a plurality of transistors to perform an "AOI" logic function, and the first master inverter 314 may be implemented by a plurality of slave transistors 354 to perform an "inverter" logic function. Similarly, the second cross-coupled and-or inverter (AOI) logic gate pair 323 may be implemented by a plurality of transistors to perform an "AOI" logic function, and the second master inverter 324 may be implemented by two transistors to perform an "inverter" logic function. Further, cross-coupled or inverter (OAI) logic gate pair 353 may be implemented by a plurality of transistors to perform an "OAI" logic function, and slave inverter 354 may be implemented by two transistors to perform an "inverter" logic function.

According to some embodiments of the present disclosure, referring to fig. 3 and 4, the flip-flop circuit 30 is substantially similar to the flip-flop circuit 20 except that the first master portion 31 of the flip-flop circuit 30 includes a first cross-coupled and-inverter (AOI) logic gate pair 313, the second master portion 32 of the flip-flop circuit 30 includes a second cross-coupled and-inverter (AOI) logic gate pair 314, and the slave portion 35 of the flip-flop circuit 30 includes a cross-coupled or-inverter (OAI) logic gate pair 353. In other words, the cross-coupled or inverter (OAI) logic gate pair 353 in fig. 4 may be substantially similar to the first cross-coupled or inverter (OAI) logic gate pair 213 or the second cross-coupled or inverter (OAI) logic gate pair 223 in fig. 3. Therefore, discussion of the first main portion 31, the second main portion 32, and the slave portion 35 is omitted for clarity. By arranging the AOI to the first and second master portions 31, 32 and the OAI to the slave portion 35 (i.e. swapping the AOI and OAI), one or more additional clock buffer circuits may be integrated into the flip-flop circuit. Thereby reducing the burden on the clock circuit 30 and thus on the clock circuit (i.e., the circuit that supplies the clock signal CP).

According to some embodiments of the present disclosure, to implement the first and second master portions 31 and 32 by AOI and the slave portion 35 by OAI, the flip-flop circuit 30 further comprises an inverter 36 configured to receive the clock signal CP and provide a logically inverted signal to the first and second master portions 31 and 32 and the slave portion 35, respectively.

According to some embodiments of the present disclosure, the first decision portion 33 has a first decision input 331 and a first decision output 332. The first decision input 331 is connected to the first main output 312. The first decision output 332 is connected to the decision output EO. The second decision part 34 has a second decision input 341 and a second decision output 342. The second decision input 341 is connected to the second main output 322. The second decision output 342 is connected to the decision output EO.

According to some embodiments of the present disclosure, the first determination part 33 includes a plurality of transistors controlled by the scan enable Signal (SE) and the inverted scan enable signal (seb). The second decision part 34 includes a plurality of transistors controlled by the scan enable Signal (SE) and the inverted scan enable signal (seb). Accordingly, the first and second decision parts 33 and 34 are configured to decide the decision output EO to be the first main output 312 or the second main output 322 according to the scan enable Signal (SE) and the inverted scan enable signal (seb). For example, the first decision portion 33 may couple the first primary output 312 to the first decision output 332 when the scan enable Signal (SE) is asserted to a logic high state (e.g., a logic "1"). Therefore, the determination output EO is the first main output 312. When the scan enable Signal (SE) is asserted to a logic low state (e.g., a logic "0"), the second decision portion 34 may couple the second main output 322 to the second decision output 342. Therefore, the determination output EO is the second main output 322.

According to some embodiments of the present disclosure, by using the first and second decision parts 33 and 34, the first main output 312 from the first main part 31 or the second main output 322 from the second main part 32 may be decided. Thus, a conventional multiplexer disposed before a conventional master latch circuit may not be required, which may advantageously allow for faster speed (e.g., approximately 7%) of the flip-flop circuit 30.

Fig. 5 illustrates a transistor-level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure. Refer to the figures. Referring to fig. 3 and 5, a flip-flop circuit 20A is substantially similar to the flip-flop circuit 20 of fig. 1, except that the flip-flop circuit 20A further includes a time shift circuit 26. The time shift section 26 is coupled to the first and second master sections 21, 22 for delaying a clock signal CP of the first and second master sections 21, 22 by a predetermined time, the clock signal CP being connected to the slave section 25 without the time shift section 26. For clarity, the discussion of the components of flip-flop circuit 20A is substantially similar to those of flip-flop circuit 20 (e.g., 21, 22, and 25), which are omitted.

According to some embodiments of the present disclosure, the time shift circuit 26 includes one or more inverters coupled in series with each other. Although fig. 5 illustrates the time shift circuit 26 as including 4 inverters, any desired number of inverters (e.g., 2-8) may be included in the time shift circuit 26 while remaining within the scope of the present disclosure. The time shift circuit 26 is included in the flip-flop circuit 20A, and the clock signal CP to be received by the first and second master portions 21 and 22 can be delayed by a plurality of gate delays corresponding to the number of inverters included in the time shift circuit 26, while the slave portion 25 receives the clock signal CP without delay. Delaying the clock signal CP of the first and second main portions 21, 22 may advantageously reduce the setup time of the flip-flop circuit 20A, according to some embodiments of the present disclosure. Since the clock signal CP is delayed to be received by the first and second master portions 21, 22 and the clock signal CP is received immediately by the slave portion 25 without delay, in some embodiments the slave portion 25 may provide a transparent window and release data earlier, which results in the first and second master portions 21, 22 having more time to receive input data in the current cycle, thereby reducing the setup time.

According to some embodiments of the present disclosure, time shift circuit 26 includes 4 inverters, and each inverter of time shift circuit 26 is substantially similar to inverters 214, 224, and 252. Therefore, discussion of the inverter of the shift circuit 26 will be omitted. Thus, the delayed clock signals received by the first and second main sections 21 and 22 may have about four gate delays after the clock signal CP.

Fig. 6 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure. Referring to fig. 6, the flip-flop circuit 40 includes a first master portion 41, a second master portion 42, and a slave portion 43. The first main part 41 is configured to operate in a first mode and receive a first input 411 and generate a first main output 412. The second main section 42 is configured to operate in a second mode and receive a second input 421 and generate a second main output 422. According to some embodiments of the present disclosure, the first mode may be a test mode, and the second mode may be a normal mode. The first input 411 may be a scan Signal (SI) and the second input 421 may be a data signal (D).

According to some embodiments of the present disclosure, when the first main portion 41 operates in the test mode, the first main portion 41 receives the scan input signal 411 and generates the first main output 412 (scan output signal). In some embodiments, a failure of one or more flip-flop circuits (i.e., one or more failing flip-flop circuits) may be detected by comparing one or more differences between scan-in signal 411 and scan-out signal. Such a fail-trigger circuit may be used to ascertain which respective subset of logic gates is failing. According to some embodiments of the present disclosure, the first main portion 41 has a first enable portion 413 for enabling the first main portion 41 according to at least one enable signal. The at least one enable signal includes a scan enable Signal (SE) and an inverted scan enable signal (seb).

According to some embodiments of the present disclosure, when the second main section 42 operates in the normal mode, the second main section 42 receives data signals 421 provided from a respective subset of logic gates of the circuit under test. According to some embodiments of the present disclosure, the data signal 421 may include data generated based on the logical operations of the respective subset of logic gates. According to some embodiments of the present disclosure, the second main portion 42 has a second enable portion 423, the second enable portion 423 being configured to enable the second main portion 42 according to at least one enable signal. The at least one enable signal includes a scan enable Signal (SE) and an inverted scan enable signal (seb).

According to some embodiments of the present disclosure, the slave portion 43 is configured to receive the first master output 412 or the second master output 422 and generate the output signal 432. The slave portion 43 includes a first master output 412 and a second master output 422 connected to the first master output 412.

According to some embodiments of the present disclosure, the first master portion 41 comprises a first cross-coupled or and inverter (OAI) logic gate pair 414 and a first master inverter 415, and the second master portion 42 comprises a second cross-coupled or and inverter (OAI) logic gate pair 424 and a second master inverter 425, and the slave portion 45 comprises a cross-coupled and or inverter (AOI) logic gate pair 453 and a slave inverter 454.

According to some embodiments of the present disclosure, the first enable part 413 includes a plurality of transistors controlled by a scan enable Signal (SE) and an inverted scan enable signal (seb) to enable the first main part 41. The first enable portion 413 is provided in the first main portion 21. The second enable part 423 includes a plurality of transistors controlled by the scan enable Signal (SE) and the inverted scan enable signal (seb) to enable the second main part 42. The second enabling portion 423 is provided in the second main portion 42. Accordingly, the first and second enable portions 413 and 423 are configured to determine whether the slave input 431 is the first or second master output 112 or 122 according to the scan enable Signal (SE) and the inverted scan enable signal (seb). For example, when the scan enable Signal (SE) is asserted to a logic high state (e.g., a logic "1"), the first cross-coupled or and inverter (OAI) logic gate pair 414 is activated and the second cross-coupled or and inverter (OAI) logic gate pair 424 is deactivated. Thus, the slave input 431 is the first master output 412. When the scan enable Signal (SE) is asserted to a logic low state (e.g., a logic "0"), the first cross-coupled or and inverter (OAI) logic gate pair 414 is deactivated and the second cross-coupled or and inverter (OAI) logic gate pair 424 is activated. Thus, the slave input 431 is the second master output 422.

According to some embodiments of the present disclosure, by using the first enable portion 413 and the second enable portion 423, the first master output 412 from the first master portion 41 or the second master output 422 from the second master portion 42 may be determined to be sent to the slave input 431. Accordingly, a conventional multiplexer disposed before a conventional master latch circuit may not be required, which may advantageously improve the performance of the flip-flop circuit 40.

Fig. 7 illustrates a transistor-level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure. Refer to the figures. Referring to fig. 7, the flip-flop circuit 50 includes a first master portion 51, a second master portion 52, and a slave portion 53. The first main part 51 is configured to operate in a first mode and receive a first input 511 and generate a first main part. The second main section 52 is configured to operate in a second mode and receive a second input 521 and generate a second main output 522. According to some embodiments of the present disclosure, the first mode may be a test mode, and the second mode may be a normal mode. The first input 511 may be a scan Signal (SI) and the second input 421 may be a data signal (D).

According to some embodiments of the present disclosure, the first master portion 51 comprises a first cross-coupled and-inverter (AOI) logic gate pair 514 and a first master inverter 515, and the second master portion 52 comprises a second cross-coupled and-inverter (AOI) logic gate pair 524 and a second master inverter 525, while the slave portion 53 comprises a cross-coupled or-inverter (OAI) logic gate pair 533 and a second pair. The first cross-coupled and-or inverter (AOI) logic gate pair 514 may be implemented by a plurality of transistors to perform an "AOI" logic function, and the first master inverter 515 may be implemented by two transistors to perform an "inverter" logic function. Similarly, the second cross-coupled and-or inverter (AOI) logic gate pair 524 may be implemented by a plurality of transistors to perform an "AOI" logic function, and the second master inverter 525 may be implemented by two transistors to perform an "inverter" logic function. Furthermore, cross-coupled or inverter (OAI) logic gate pair 533 may be implemented with multiple transistors to perform an "OAI" logic function, and slave inverter 534 may be implemented with two transistors to perform an "inverter" logic function.

According to some embodiments of the present disclosure, referring to fig. 6 and 7, the flip-flop circuit 50 is substantially similar to the flip-flop circuit 40, except that the first main portion 51 of the flip-flop circuit 50 comprises a first cross-coupled and-or inverter (AOI) logic gate pair, the second main portion 52 of the flip-flop circuit 50 comprises a second cross-coupled and-or inverter (AOI) logic gate pair 524, and the slave portion 53 of the flip-flop circuit 50 comprises a cross-coupled or-inverter (OAI) logic gate pair 533. In other words, the cross-coupled or inverter (OAI) logic gate pair 533 in fig. 7 is substantially similar to the first cross-coupled or inverter (OAI) logic gate pair 414 or the second cross-coupled or inverter (OAI) logic gate pair 424 in fig. 6. Further, the first cross-coupled pair of and inverter (AOI) logic gates 514 or the second cross-coupled pair of and inverter (AOI) logic gates 524 in fig. 7 are substantially similar to the cross-coupled pair of and inverter (AOI) logic gates 433 in fig. 6. Therefore, discussion of the first main portion 51, the second main portion 52, and the slave portion 55 is omitted for clarity. One or more additional clock buffer circuits may be integrated into the flip-flop circuit 50 by setting AIO for the first and second master portions 51, 52 and OAI for the slave portion 53 (i.e., swapping AOI and OAI). Thereby reducing the burden on the clock circuit (i.e., the circuit that provides the clock signal CP).

According to some embodiments of the present disclosure, to implement the first and second master portions 51 and 52 by AOI and the slave portion 53 by OAI, the flip-flop circuit 50 further comprises an inverter 54, the inverter 54 being configured to receive the clock signal CP and to provide a logically inverted signal to the first and second master portions 51 and 52 and the slave portion 53, respectively.

According to some embodiments of the present disclosure, the first main portion 51 has a first enable portion 513 for enabling the first main portion 51 according to at least one enable signal. According to some embodiments of the present disclosure, the second main portion 52 has a second enable portion 523 for enabling the second main portion 52 according to at least one enable signal. The at least one enable signal includes a scan enable Signal (SE) and an inverted scan enable signal (seb).

According to some embodiments of the present disclosure, the slave portion 53 is configured to receive the first or second primary output 512, 522 and generate an output signal 532. The slave portion 53 includes a slave input 531 connected to the first and second master outputs 512, 522.

According to some embodiments of the present disclosure, the first enable part 513 includes a plurality of transistors controlled by a scan enable Signal (SE) and an inverted scan enable signal (seb) to enable the first main part 51. The first enable portion 513 is provided in the first main portion 51. The second enable part 523 includes a plurality of transistors controlled by the scan enable Signal (SE) and the inverted scan enable signal (seb) to enable the second main part 52. The second enabling part 523 is provided in the second main part 52. Accordingly, the first and second enable sections 513 and 523 are configured to determine whether the slave input 531 is the first or second master output 512 or 522 according to the scan enable Signal (SE) and the inverted scan enable signal (seb). For example, when the scan enable Signal (SE) is asserted to a logic high state (e.g., a logic "1"), the first cross-coupled or and inverter (OAI) logic gate pair 514 is activated and the second cross-coupled or and inverter (OAI) logic gate pair 524 is deactivated. Thus, the slave input 431 is the first master output 512. When the scan enable Signal (SE) is asserted to a logic low state (e.g., a logic "0"), the first cross-coupled or inverter (OAI) pair of logic gates 514 is deactivated and the second cross-coupled or inverter (OAI) pair of logic gates 524 is activated. Thus, the slave input 531 is the second master output 522.

According to some embodiments of the present disclosure, by using the first enabling part 513 and the second enabling part 523, the first primary output 512 from the first primary part 51 or the second primary output 522 from the second primary part 52 may be decided to be sent to the slave input 531. Accordingly, a conventional multiplexer disposed before a conventional master latch circuit may not be required, which may advantageously improve the performance of the flip-flop circuit 50.

Fig. 8 illustrates a transistor level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure. Referring to fig. 6 and 8, a flip-flop circuit 40A is substantially similar to the flip-flop circuit 40 of fig. 6, except that the flip-flop circuit 40A further includes a time shift circuit 44. The time shift section 44 is coupled to the first and second main sections 41 and 42 for delaying the clock signal CP to the first and second main sections 41 and 42 by a predetermined time. And the clock signal CP is connected to the slave portion 43 without the time shift portion 44. For clarity, the discussion of the components of flip-flop circuit 40A is substantially similar to those of flip-flop circuit 40 (e.g., 41, 42, and 43), which are omitted.

According to some embodiments of the present disclosure, the time shift circuit 44 includes one or more inverters coupled in series with each other. Although the embodiment of FIG. 8 shows the time shift circuit 44 including 4 inverters, any desired number of inverters (e.g., 2-8) may be included in the time shift circuit 44 while remaining within the scope of the present disclosure. The inclusion of such a time shift circuit 44 in the flip-flop circuit 40A makes it possible to delay the clock signal CP to be received by the first and second master portions 41 and 42 by a plurality of gate delays corresponding to the number of inverters included in the time shift circuit 44, while the slave portion 43 receives the clock signal CP without delay. According to some embodiments of the present disclosure, the clock signal CP delayed to the first and second main portions 41 and 42 may advantageously reduce the setup time of the flip-flop circuit 40A. Since the clock signal CP is delayed to be received by the first and second master portions 41, 42 and the clock signal CP is received immediately by the slave portion 43 without delay, in some embodiments the slave portion 43 may provide a transparent window and release data earlier, which results in the first and second master portions 41, 42 having more time to receive input data in the current cycle, thereby reducing the setup time.

According to some embodiments of the present disclosure, time-shift circuit 44 includes 4 inverters, and each inverter of time-shift circuit 44 is substantially similar to inverters 415, 425, and 434. Therefore, discussion of the inverter of the shift circuit 44 will be omitted. In this way, the delayed clock signals received by the first and second main sections 41 and 42 may have about four gate delays after the clock signal CP.

Fig. 9 illustrates a transistor level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure. Referring to fig. 9, the flip-flop circuit 60 includes a master portion 61 and a slave portion 62. The main portion 61 is configured to receive at least one first input, at least one second input and at least one enable signal and to generate a main output 615, the main portion 61 comprising a plurality of control portions 611, 612, 613, 614, the plurality of control portions 611, 612, 613, 614 being configured to control the main portion 61 to operate in a first mode or a second mode depending on the at least one first input, the at least one second input and the at least one enable signal. According to some embodiments of the present disclosure, the first mode may be a test mode, and the second mode may be a normal mode. The at least one first input includes a scan input Signal (SI) and an inverted scan input signal (SIb), and the at least one second input includes a data signal (D) and an inverted data signal (Db). The at least one enable signal includes a scan enable Signal (SE) and an inverted scan enable signal (seb).

According to some embodiments of the present disclosure, the slave portion 62 is configured to receive the master output 615 and generate an output signal 622. The slave portion 62 includes a slave input 621 connected to the master output 615.

According to some embodiments of the present disclosure, the main section 61 includes a first control section 611, a second control section 612, a third control section 613 and a fourth control section 614. The first control part 611 includes a plurality of transistors controlled by an inverted scan input signal (SIb), an inverted data signal (Db), a scan enable Signal (SE), and an inverted scan enable signal (SEb). That is, the first control part 611 may include four PMOS transistors, the gates of which are controlled by the inverted scan input signal (SIb), the inverted data signal (Db), the scan enable Signal (SE), and the inverted scan enable signal (SEb). The second control part 612 includes a plurality of transistors controlled by the inverted scan input signal (SIb), the inverted data signal (Db), the scan enable Signal (SE), and the inverted scan enable signal (SEb). That is, the second control section 612 may include four NMOS transistors whose gates are controlled by the inverted scan input signal (SIb), the inverted data signal (Db), the scan enable Signal (SE), and the inverted scan enable signal (SEb). The third control part 613 includes a plurality of transistors controlled by the scan input Signal (SI), the data signal (D), the scan enable Signal (SE), and the inverted scan enable signal (SEb). That is, the third control part 613 may include four PMOS transistors whose gates are controlled by the scan input Signal (SI), the data signal (D), the scan enable Signal (SE), and the inverted scan enable signal (SEb). The fourth control part 614 may include a plurality of transistors controlled by the scan input Signal (SI), the data signal (D), the scan enable Signal (SE), and the inverted scan enable signal (SEb). That is, the fourth control part 614 may include four NMOS transistors, the gates of which are controlled by the scan input Signal (SI), the data signal (D), the scan enable Signal (SE), and the inverted scan enable signal (SEb).

According to some embodiments of the present disclosure, the master portion 61 includes a cross-coupled or-inverter (OAI) pair of logic gates 616, and the slave portion 62 includes a cross-coupled and-or-inverter (AOI) pair of logic gates 623 and a slave inverter 624. The cross-coupled or inverter (OAI) logic gate pair 616 may be implemented by a plurality of transistors to perform an "OAI" logic function. Further, the cross-coupled and-or inverter (AOI) logic gate pair 623 may be implemented by a plurality of transistors to perform an "AOI" logic function, and the slave inverter 624 may be implemented by two transistors to perform an "inverter" logic function.

According to some embodiments of the present disclosure, the first control part 611, the second control part 612, the third control part 613, and the fourth control part 614 may determine that the main part 61 operates in the test mode or the normal mode. When the main portion 61 operates in the test mode, the scan enable Signal (SE) is asserted to a logic high state (e.g., logic "1"), and the scan input Signal (SI) and inverted scan input signal (SIb) are input to a cross-coupled or inverter "(OAI) logic gate pair 616. Thus, the main portion 61 generates a main output 615 (scan output signal). When the main portion 61 operates in the normal mode, the scan enable Signal (SE) is asserted to a logic low state (e.g., logic "0"), and the data signal (D) and the inverted data signal (Db) are input to the cross-coupled or and inverter (OAI) logic gate pair 616.

According to some embodiments of the present disclosure, the clock signal CP of the flip-flop circuit 60 may be used by or in common with a pair of cross-coupled or inverter (OAI) logic gates 616 and a pair of cross-coupled or inverter (AOI) logic gates 623, respectively. In this way, a logical inverted clock signal and corresponding components (e.g., one or more inverters) for generating such a logical inverted clock signal may not be required, which may advantageously reduce power consumption and design complexity of the flip-flop circuit 60.

According to some embodiments of the present disclosure, the main part 61 may be operated in a test mode or a normal mode by using the first control part 611, the second control part 612, the third control part 613, and the fourth control part 614. Thus, a conventional multiplexer disposed before a conventional master latch circuit may not be required, which may advantageously allow for faster speed of the flip-flop circuit 60 and reduce power consumption of the flip-flop circuit 60, e.g., by about 17%.

Fig. 10 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure. Referring to fig. 10, the flip-flop circuit 70 includes a master portion 71 and a slave portion 72. The main portion 71 is configured to receive at least one first input, at least one second input, and at least one enable signal, and to generate a main output 715. The main part 71 comprises a plurality of control parts 711, 712, 713, 714, the plurality of control parts 711, 712, 713, 714 being configured to control the main part 71 to operate in the first mode or the second mode depending on at least one first input, at least one second input and at least one enabling signal. According to some embodiments of the present disclosure, the first mode may be a test mode, and the second mode may be a normal mode. The at least one first input includes a scan input Signal (SI) and an inverted scan input signal (SIb), and the at least one second input includes a data signal (D) and an inverted data signal (Db). The at least one enable signal includes a scan enable Signal (SE) and an inverted scan enable signal (seb).

According to some embodiments of the present disclosure, the slave portion 72 is configured to receive the master output 715 and generate an output signal 722. The slave portion 72 includes a slave input 721 connected to a master output 715.

According to some embodiments of the present disclosure, the master portion 71 includes a cross-coupled and or inverter (AOI) logic gate pair 716, while the slave portion 72 includes a cross-coupled or and inverter (OAI) logic gate pair 723 and a slave inverter 724. The cross-coupled and or inverter (AOI) logic gate pair 716 may be implemented by multiple transistors to perform an "AOI" logic function. Further, cross-coupled or inverter (OAI) logic gate pair 723 may be implemented with multiple transistors to perform an "OAI" logic function, and slave inverter 724 may be implemented with two transistors to perform an "inverter" logic function.

According to some embodiments of the present disclosure, referring to fig. 9 and 10, the flip-flop circuit 70 is substantially similar to the flip-flop circuit 60, except that the master portion 71 of the flip-flop circuit 70 includes a cross-coupled and or inverter (AOI) logic gate pair 716 and the slave portion 72 of the flip-flop circuit 70 includes a cross-coupled or and inverter (OAI) logic gate pair 723. In other words, the cross-coupled or inverter (OAI) logic gate pair 723 in fig. 10 is substantially similar to the cross-coupled or inverter (OAI) logic gate pair 616 in fig. 9. Further, cross-coupled and-or inverter (AOI) logic gate pair 716 in fig. 10 is substantially similar to cross-coupled and-or inverter (AOI) logic gate pair 623 in fig. 9. Thus, by arranging the AOI to the first master portion 71 and the OAI to the slave portion 72 (i.e. exchanging the AOI and the OAI), one or more additional clock buffer circuits may be integrated into the flip-flop circuit 70, thus reducing the load on the clock circuit (i.e. the circuit providing the clock signal CP).

According to some embodiments of the present disclosure, to implement the master portion 71 by AOI and the slave portion 72 by OAI, the flip-flop circuit 70 further comprises an inverter 74, the inverter 74 being configured to receive the clock signal CP and to provide logically inverted signals to the master portion 71 and the slave portion 72, respectively.

According to some embodiments of the present disclosure, the first control section 711, the second control section 712, the third control section 713, and the fourth control section 714 may determine that the main section 71 operates in the test mode or the normal mode. When the main portion 71 operates in the test mode, the scan enable Signal (SE) is asserted to a logic high state (e.g., logic "1"), and the scan input Signal (SI) and the inverted scan input signal (SIb) are input to a cross-coupled and or inverter (AOI) logic gate pair 716. Thus, the main section 71 generates a main output 715 (scan output signal). When the main section 71 operates in the normal mode, the scan enable Signal (SE) is asserted to a logic low state (e.g., logic "0"), and the data signal (D) and the inverted data signal (Db) are input to a cross-coupled and or inverter (AOI) logic gate pair 716.

According to some embodiments of the present disclosure, the main part 71 may be operated in a test mode or a normal mode by using the first control part 711, the second control part 712, the third control part 713, and the fourth control part 714. Thus, a conventional multiplexer disposed before a conventional master latch circuit may not be required, which may advantageously allow for faster speed of the flip-flop circuit 70 and reduced power consumption (e.g., approximately 17%) of the flip-flop circuit 70.

Fig. 11 illustrates a transistor level circuit diagram of a flip-flop circuit according to some embodiments of the present disclosure. Refer to the figures. Referring to fig. 9 and 11, a flip-flop circuit 60A is substantially similar to the flip-flop circuit 60 of fig. 9, except that the flip-flop circuit 60A further includes a time shift circuit 63. The time shift section 63 is coupled to the main section 61 to delay the clock signal CP to the main section 61 by a predetermined time. The signal CP is connected to the slave part 62 without the time shift part 63. For clarity, the discussion of the components of flip-flop circuit 60A is substantially similar to those of flip-flop circuit 60 (e.g., 61 and 62), which are omitted.

According to some embodiments of the present disclosure, the time shift circuit 63 includes one or more inverters coupled in series with each other. Although FIG. 11 illustrates the time shift circuit 63 as including 4 inverters, any desired number of inverters (e.g., 2-8) may be included in the time shift circuit 63 while remaining within the scope of the present disclosure. Such a time shift circuit 63 is included in the flip-flop circuit 60A to delay the clock signal CP to be received by the master portion 61, and the slave portion 62 receives the clock signal CP without delay. According to some embodiments of the present disclosure, delaying the clock signal CP to the main portion 61 may advantageously reduce the setup time of the flip-flop circuit 60A. Since clock signal CP is delayed to be received by master portion 61 and clock signal CP is received immediately from slave portion 62 without delay, in some embodiments slave portion 62 may provide a transparent window and release data earlier, which allows master portion 61 more time to receive input data in the current cycle, thereby reducing setup time.

According to some embodiments of the present disclosure, time shifting circuit 63 includes 4 inverters, and each inverter of time shifting circuit 63 is substantially similar to inverter 624. The main section 61 may have about four gate delays after the clock signal CP.

Fig. 12 illustrates a transistor-level circuit diagram of a flip-flop circuit, according to some embodiments of the present disclosure. Refer to the figures. Referring to fig. 9 and 12, the flip-flop circuit 80 may be a multi-bit flip-flop circuit. Flip-flop circuit 80 may include a first bit flip-flop circuit 81 and a second bit flip-flop circuit 86. The second bit flip-flop circuit 86 is a replica of the first bit flip-flop circuit 81. The flip-flop circuit 81 includes a master portion 82 and a slave portion 83. The main portion 82 is the same as the main portion 61 in fig. 9. The slave portion 83 is the same as the slave portion 62 in fig. 9. The first bit flip-flop circuit 81 includes a master portion 82 and a slave portion 83. The main portion 82 is the same as the main portion 61 in fig. 9. The slave 83 is the same as the slave 62 in fig. 9. The second bit flip-flop circuit 86 includes a master portion 87 and a slave portion 88. The main portion 87 is the same as the main portion 61 in fig. 9. The slave 88 is the same as the slave 62 in fig. 9. The clock signal CP of the flip-flop circuit 80 can be commonly used by the first bit flip-flop circuit 81 and the second bit flip-flop circuit 86, respectively.

Fig. 13 is a flow diagram illustrating a method for operating a flip-flop circuit, according to some embodiments of the present disclosure. While the process of the figure may use various structures to implement the structure of figure 13, for ease of understanding, reference is made to existing structures described herein. Referring to fig. 13, the method for operating the flip-flop includes: a first step 1301 of deploying a first master part 11 configured to operate in a first mode and receive a first input and generate a first master output, a second step 1302 of deploying a second master part 12 configured to operate in a second mode and receive a second input and generate a second master output, a third step 1303 of deploying at least one decision part 13, 14 configured to receive at least one enable signal and having a decision input and a decision output, the decision input being connected to the first master output and the second master output, the decision part being configured to decide the decision output as the first master output or the second master output depending on the at least one enable signal, a fourth step 1304 of deploying a slave part 15 configured to receive the decision output and generate an output signal.

Fig. 14 is a flow diagram illustrating a method for operating a flip-flop circuit, according to some embodiments of the present disclosure. While the process of the figure may use a variety of structures to implement the structure of figure 14, for ease of understanding, reference is made to existing structures described herein. Referring to fig. 14, a method for operating a flip-flop includes a first step 1401 of deploying a first master portion 41 configured to operate in a first mode and to receive a first input and to generate a first master output, the first master portion having a first enable portion 413, the first enable portion 413 being for enabling the first master portion according to at least one enable signal, a second step 1402 of deploying a second master portion 42 configured to operate in a second mode and to receive a second input and to generate a second master output, the second master portion having a second enable portion 423, the second enable portion 423 being for enabling the second master portion according to at least one enable signal, and a third step 1403 of deploying a slave portion 43 configured to receive the first master output or the second master output and to generate an output signal.

Fig. 15 is a flow diagram illustrating a method for operating a flip-flop circuit, according to some embodiments of the present disclosure. Referring to fig. 15, a method for operating a flip-flop comprises a first step 1501 of deploying a master portion 61 configured to receive at least one first input, at least one second input and at least one enable signal and generate a master output, the master portion comprising a plurality of control components 611, 612, 613, 614, the plurality of control components 611, 612, 613, 614 configured to control the master portion to operate in a first mode or a second mode depending on the at least one first input, the at least one second input and the at least one enable signal, a second step 1502 of deploying a slave portion 62 configured to receive the master output and generate an output signal.

In some embodiments, a flip-flop circuit is disclosed that includes a first master portion, a second master portion, at least one decision portion, and a slave portion. The first primary portion is configured to operate in a first mode and receive a first input and generate a first primary output. The second main portion is configured to operate in a second mode and receive a second input and generate a second main output. The at least one decision portion is configured to receive at least one enable signal and has a decision input and a decision output. The decision input is connected to the first and second primary outputs. The determination section is configured to determine whether the determination output is the first main output or the second main output based on at least one enable signal. The slave portion is configured to receive the decision output and generate an output signal.

In the above-described flip-flop circuit, the first mode is a test mode, and the second mode is a normal mode, the first input is a scan input signal, and the second input is a data signal, the at least one enable signal including a scan enable signal and an inverted scan enable signal.

In the above-described flip-flop circuit, the first master portion includes a first pair of cross-coupled or and inverter (OAI) logic gates and a first master inverter, and the second master portion includes a second pair of cross-coupled or and inverter (OAI) logic gates and a second master inverter, and the slave portion includes a pair of cross-coupled and or inverter (AOI) logic gates and a slave inverter.

In the above-described flip-flop circuit, the first master portion includes a first pair of cross-coupled and-inverter (AOI) logic gates and a first master inverter, and the second master portion includes a second pair of cross-coupled and-inverter (AOI) logic gates and a second master inverter, and the slave portion includes a pair of cross-coupled or-inverter (OAI) logic gates and a slave inverter.

In the above-described flip-flop circuit, the flip-flop circuit includes a first decision portion having a first decision input connected to the first main output and a first decision output connected to the decision output, and a second decision portion having a second decision input connected to the second main output and a second decision output connected to the decision output.

In the above-described flip-flop circuit, the first determination section includes a plurality of transistors controlled by at least one enable signal, and the second determination section includes a plurality of transistors controlled by at least one enable signal, the at least one enable signal including a scan enable signal and an inverted scan enable signal.

In the above-described flip-flop circuit, further comprising: a time shift section coupled to the first and second main sections for delaying a predetermined time of the clock signals to the first and second main sections. The signal is connected to the slave part without a time-shifted part.

In some embodiments, a flip-flop circuit is disclosed, comprising: a first master portion, a second master portion, and a slave portion. The first primary portion is configured to operate in a first mode and receive a first input and generate a first primary output. The first main section has a first enable section for enabling the first main section in accordance with at least one enable signal. The second main portion is configured to operate in a second mode and receive a second input and generate a second main output. The second main section has a second enable section for enabling the second main section in accordance with at least one enable signal. The slave portion is configured to receive the first or second master output and generate an output signal.

In the above-described flip-flop circuit, the first mode is a test mode, and the second mode is a normal mode, the first input is a scan signal, and the second input is a data signal, the at least one enable signal including a scan enable signal and an inverted scan enable signal.

In the above-described flip-flop circuit, the first master portion includes a first pair of cross-coupled or and inverter (OAI) logic gates and a first master inverter, and the second master portion includes a second pair of cross-coupled or and inverter (OAI) logic gates and a second master inverter, and the slave portion includes a pair of cross-coupled and or inverter (AOI) logic gates and a slave inverter.

In the above-described flip-flop circuit, the first master portion includes a first pair of cross-coupled and-inverter (AOI) logic gates and a first master inverter, and the second master portion includes a second pair of cross-coupled and-inverter (AOI) logic gates and a second master inverter, and the slave portion includes a pair of cross-coupled or-inverter (OAI) logic gates and a slave inverter.

In the above-described flip-flop circuit, the first enable section includes a plurality of transistors controlled by at least one enable signal, and the at least one enable signal includes a scan enable signal and an inverted scan enable signal.

In the above-described flip-flop circuit, the second enable portion includes a plurality of transistors controlled by at least one enable signal.

In the above-described flip-flop circuit, further comprising: and a time shifting section coupled to the first and second master sections for delaying a predetermined time of clock signals to the first and second master sections, the clock signals being connected to the slave sections without the time shifting section.

In some embodiments, a flip-flop circuit is disclosed, comprising: a main section configured to receive at least one first input, at least one second input, and at least one enable signal, and generate a main output, the main section including a plurality of control sections configured to control the main section to operate in a first mode or a second mode according to the at least one first input, the at least one second input, and the at least one enable signal; and a slave portion configured to receive the master output and generate an output signal.

In the above-described flip-flop circuit, the first mode is a test mode, and the second mode is a normal mode, the at least one first input includes a scan input signal and an inverted scan input signal, and the at least one second input includes a data signal and an inverted data signal, and the at least one enable signal includes a scan enable signal and an inverted scan enable signal.

In the above-described flip-flop circuit, the main section includes a first control section including a plurality of transistors controlled by an inverted scan signal, an inverted data signal, a scan enable signal, and an inverted scan enable signal, a second control section including a plurality of transistors controlled by an inverted scan input signal, an inverted data signal, a scan enable signal, and an inverted scan enable signal, a third control section including a plurality of transistors controlled by a scan input signal, a data signal, a scan enable signal, and an inverted scan enable signal, and a fourth control section including a plurality of transistors controlled by a scan input signal, a data signal, a scan enable signal, and an inverted scan enable signal.

In the above-described flip-flop circuit, the master portion includes a cross-coupled or and inverter (OAI) pair of logic gates, and the slave portion includes a cross-coupled and or inverter "(AOI) pair of logic gates and a slave inverter.

In the above-described flip-flop circuit, the master portion includes a cross-coupled and-or inverter (AOI) logic gate pair, and the slave portion includes a cross-coupled or-inverter (OAI) logic gate pair and a slave inverter.

In the above-described flip-flop circuit, further comprising: and a time shift section coupled to the master section for delaying a predetermined time of a clock signal to the master section, the clock signal being connected to the slave section without the time shift section.

One skilled in the relevant art will readily recognize that one or more of the embodiments disclosed may be implemented with one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents, and various other embodiments as broadly disclosed herein. Accordingly, it is intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.