阅读说明：本技术 半导体器件及其制备方法 (Semiconductor device and method for manufacturing the same ) 是由 方冬 肖魁 卞铮 胡金节 于 2020-05-18 设计创作，主要内容包括：本申请涉及一种半导体器件及其制备方法,器件包括：漂移区、形成于漂移区内的体区和形成于体区内的第一掺杂区和第二掺杂区；第一沟槽穿透第一掺杂区、体区并延伸至漂移区内,扩展区与漂移区导电类型相反且包围第一沟槽的底壁,第一沟槽内填充有位于底部的第一导电结构和位于顶部的第二导电结构,第一导电结构和第二导电结构相互隔离；第二导电结构与第一沟槽的内壁之间以及第一导电结构与第一沟槽未被扩展区包围的内壁之间形成有介质层；第二沟槽穿透第一掺杂区和体区,第二沟槽内填充有第三导电结构以及位于第三导电结构和第二沟槽的内壁之间的介质层。通过第一沟槽和扩展区的作用,可增强漂移区的耗尽,提高器件耐压。(The application relates to a semiconductor device and a preparation method thereof, wherein the device comprises: the drift region, a body region formed in the drift region, and a first doped region and a second doped region formed in the body region; the first groove penetrates through the first doping region and the body region and extends into the drift region, the conduction type of the extension region is opposite to that of the drift region and surrounds the bottom wall of the first groove, a first conductive structure located at the bottom and a second conductive structure located at the top are filled in the first groove, and the first conductive structure and the second conductive structure are isolated from each other; dielectric layers are formed between the second conductive structure and the inner wall of the first groove and between the first conductive structure and the inner wall of the first groove, which is not surrounded by the extension area; the second groove penetrates through the first doping area and the body area, and a third conductive structure and a dielectric layer located between the third conductive structure and the inner wall of the second groove are filled in the second groove. Through the action of the first groove and the extension region, the depletion of the drift region can be enhanced, and the withstand voltage of the device is improved.)

1. A semiconductor device, comprising:

a drift region having a first conductivity type;

a body region having a second conductivity type formed within the drift region;

a first doped region and a second doped region respectively formed in the body region, the first doped region having a first conductivity type, the second doped region having a second conductivity type;

the first trench gate is formed by filling a first trench, and the first trench penetrates through the first doped region and the body region and extends into the drift region; the extension region is of a second conductivity type, is formed in the drift region below the first trench and surrounds the bottom wall of the first trench, and is filled with a first conductive structure at the bottom and a second conductive structure at the top, and the first conductive structure and the second conductive structure are isolated from each other; dielectric layers are formed between the second conductive structure and the inner wall of the first groove and between the first conductive structure and the inner wall of the first groove, which is not surrounded by the extension region;

the second trench gate is formed by filling a second trench, the second trench penetrates through the first doped region and the body region, and a third conductive structure and a dielectric layer located between the third conductive structure and the inner wall of the second trench are filled in the second trench;

a gate electrically connected to the second and third conductive structures;

a first electrode electrically connected to the first doped region and the second doped region;

a second electrode lead-out region in contact with the drift region;

and the second electrode is electrically connected with the second electrode lead-out area.

2. The semiconductor device of claim 1, wherein the first trench gate and the second trench gate are alternately arranged side by side with equal spacing between adjacent trench gates.

3. The semiconductor device of claim 1, wherein a bottom of the second trench is flush with a top of the first conductive structure.

4. The semiconductor device of claim 1, wherein the first doped region is formed on an upper surface of the body region, the second doped region is formed under the first doped region, the first doped region has a contact hole formed therein to penetrate the first doped region and expose the second doped region, and the first electrode is electrically connected to the first doped region and the second doped region through the contact hole, respectively.

5. The semiconductor device according to any one of claims 1 to 4, wherein the first conductive structure is electrically connected to the first electrode or is a floating structure. .

6. The semiconductor device according to any one of claims 1 to 4, wherein at least a portion of a bottom wall of the first trench surrounded by the extension region is not formed with a dielectric layer, the extension region is in contact with the first conductive structure, or a whole bottom wall of the first trench surrounded by the extension region is formed with a dielectric layer, and the extension region is isolated from the first conductive structure. .

7. The semiconductor device according to claim 1, wherein the semiconductor device is an IGBT, the first electrode is an emitter, the second electrode lead-out region includes a buffer region formed between the collector region and the drift region, the buffer region has a first conductivity type, the collector region has a second conductivity type, a doping concentration of the buffer region is greater than a doping concentration of the drift region, and the second electrode is a collector.

8. The semiconductor device according to claim 1, wherein the semiconductor device is a MOS transistor, the first electrode is a source electrode, the second electrode lead-out region has the first conductivity type, and the second electrode is a drain electrode.

9. A method for manufacturing a semiconductor device, comprising:

forming a drift region with a first conductivity type, forming a first groove on the drift region, and forming a dielectric layer on the inner wall of the first groove;

doping impurities with a second conduction type into the drift region at the bottom of the first groove through the first groove to form an expansion region surrounding the bottom wall of the first groove;

filling a first conductive structure into the first groove;

simultaneously etching the first conductive structure in the first groove and the drift regions on two sides of the first groove, removing the first conductive structure on the top of the first groove and reserving the first conductive structure at the bottom of the first groove, and simultaneously forming second grooves on two sides of the first groove;

filling dielectric layers in the first groove and the second groove simultaneously;

etching and removing part of the dielectric layers at the top of the first groove and the top of the second groove, and reserving part of the dielectric layers on the first conductive structure and at the bottom of the second groove;

simultaneously forming a dielectric layer on the exposed side walls of the first groove and the second groove, and then simultaneously filling a conductive material into the first groove and the second groove to respectively form a second conductive structure positioned at the top of the first groove and a third conductive structure positioned in the second groove;

doping impurities with a second conductive type into the drift region, forming body regions on two sides of the first groove and the second groove, doping impurities with the first conductive type and doping impurities with the second conductive type into the body regions, and forming a first doped region and a second doped region respectively;

and forming a grid electrode electrically connected with the second conductive structure and the third conductive structure, a first electrode electrically connected with the first doped region and the second doped region, and leading out a second electrode through a second electrode leading-out region contacted with the drift region.

10. The method of claim 9, wherein the doping the body region with the dopant impurity having the first conductivity type and the dopant impurity having the second conductivity type to form the first doped region and the second doped region, respectively, comprises:

doping impurity with a first conductivity type into the upper surface layer of the body region to form a first doping region in contact with the first trench and the second trench;

forming a contact hole penetrating through the first doped region and exposing the body region;

doping impurities with a second conductive type into the exposed body region through the contact hole to form a second doped region, wherein the first electrode is electrically connected with the first doped region and the second doped region through the contact hole respectively.

Technical Field

The present disclosure relates to the field of semiconductors, and particularly to a semiconductor device and a method for manufacturing the same.

Background

In a MOS (Metal Oxide Semiconductor) transistor and other Semiconductor devices integrated with a MOS structure, since a certain on-resistance exists when the device is turned on, the larger the on-resistance is, the larger the power consumption of the device is, and thus the on-resistance needs to be reduced as much as possible. At present, a trench gate structure is usually adopted, and a conduction channel is changed from a transverse direction to a longitudinal direction by forming the trench gate structure, so that the density of the conduction channel is greatly improved, and the conduction resistance is reduced. However, in order to further reduce the on-resistance of the trench gate structure, the doping concentration of the drift region needs to be increased, and the increase in the doping concentration will reduce the voltage endurance of the device.

Disclosure of Invention

Therefore, it is necessary to provide a new semiconductor device and a method for manufacturing the same, aiming at the technical problem that it is difficult to further reduce the on-resistance of the conventional semiconductor device.

A semiconductor device, comprising:

a drift region having a first conductivity type;

a body region having a second conductivity type formed within the drift region;

a first doped region and a second doped region respectively formed in the body region, the first doped region having a first conductivity type, the second doped region having a second conductivity type;

the first trench gate is formed by filling a first trench, and the first trench penetrates through the first doped region and the body region and extends into the drift region; the extension region is of a second conductivity type, is formed in the drift region below the first trench and surrounds the bottom wall of the first trench, and is filled with a first conductive structure at the bottom and a second conductive structure at the top, and the first conductive structure and the second conductive structure are isolated from each other; dielectric layers are formed between the second conductive structure and the inner wall of the first groove and between the first conductive structure and the inner wall of the first groove, which is not surrounded by the extension region;

the second trench gate is formed by filling a second trench, the second trench penetrates through the first doped region and the body region, and a third conductive structure and a dielectric layer located between the third conductive structure and the inner wall of the second trench are filled in the second trench;

a gate electrically connected to the second and third conductive structures;

a first electrode electrically connected to the first doped region and the second doped region;

a second electrode lead-out region in contact with the drift region;

and the second electrode is electrically connected with the second electrode lead-out area.

In one embodiment, the first trench gate and the second trench gate are alternately distributed side by side and the intervals between the adjacent trench gates are equal.

In one embodiment, the bottom of the second trench is flush with the top of the first conductive structure.

In one embodiment, the first doped region is formed on an upper surface of the body region, the second doped region is formed below the first doped region, the first doped region is provided with a contact hole penetrating through the first doped region and exposing the second doped region, and the first electrode is electrically connected to the first doped region and the second doped region through the contact hole.

In one embodiment, the first conductive structure is electrically connected to the first electrode or is a floating structure.

In one embodiment, at least a portion of the bottom wall of the first trench surrounded by the extension region is not formed with a dielectric layer, and the extension region is in contact with the first conductive structure, or the entire bottom wall of the first trench surrounded by the extension region is formed with a dielectric layer, and the extension region is isolated from the first conductive structure.

In one embodiment, the inner walls of the first trenches are formed with dielectric layers, and the extension regions are isolated from the first conductive structures.

In one embodiment, the semiconductor device is an IGBT, the first electrode is an emitter, the second electrode lead-out region includes a collector region and a buffer region formed between the collector region and the drift region, the buffer region has a first conductivity type, the collector region has a second conductivity type, a doping concentration of the buffer region is greater than a doping concentration of the drift region, and the second electrode is a collector electrode.

In one embodiment, the semiconductor device is an MOS transistor, the first electrode is a source electrode, the second electrode lead-out region has a first conductivity type, and the second electrode is a drain electrode.

A semiconductor device manufacturing method includes:

forming a drift region with a first conductivity type, forming a first groove on the drift region, and forming a dielectric layer on the inner wall of the first groove;

doping impurities with a second conduction type into the drift region at the bottom of the first groove through the first groove to form an expansion region surrounding the bottom wall of the first groove;

filling a first conductive structure into the first groove;

simultaneously etching the first conductive structure in the first groove and the drift regions on two sides of the first groove, removing the first conductive structure on the top of the first groove and reserving the first conductive structure at the bottom of the first groove, and simultaneously forming second grooves on two sides of the first groove;

filling dielectric layers in the first groove and the second groove simultaneously;

etching and removing part of the dielectric layers at the top of the first groove and the top of the second groove, and reserving part of the dielectric layers on the first conductive structure and at the bottom of the second groove;

simultaneously forming a dielectric layer on the exposed side walls of the first groove and the second groove, and then simultaneously filling a conductive material into the first groove and the second groove to respectively form a second conductive structure positioned at the top of the first groove and a third conductive structure positioned in the second groove;

doping impurities with a second conductive type into the drift region, forming body regions on two sides of the first groove and the second groove, doping impurities with the first conductive type and doping impurities with the second conductive type into the body regions, and forming a first doped region and a second doped region respectively;

and forming a grid electrode electrically connected with the second conductive structure and the third conductive structure, a first electrode electrically connected with the first doped region and the second doped region, and leading out a second electrode through a second electrode leading-out region contacted with the drift region.

In one embodiment, the doping the body region with the doping impurities having the first conductive type and the doping impurities having the second conductive type to form a first doping region and a second doping region, respectively, includes:

doping impurity with a first conductivity type into the upper surface layer of the body region to form a first doping region in contact with the first trench and the second trench;

forming a contact hole penetrating through the first doped region and exposing the body region;

doping impurities with a second conductive type into the exposed body region through the contact hole to form a second doped region, wherein the first electrode is electrically connected with the first doped region and the second doped region through the contact hole respectively.

According to the semiconductor device and the preparation method thereof, the trench gate extending into the drift region has two different structures, wherein the second trench gate is a common trench gate, the first trench gate comprises the first conductive structure positioned at the bottom and the second conductive structure positioned at the top, the second conductive structure positioned at the top is connected with the gate to form a gate structure, the first conductive structure positioned at the bottom and the dielectric layer are equivalent to the inner field plate positioned in the drift region, and the electric field of the drift region can be adjusted through the inner field plate to enhance the depletion of the drift region. On the other hand, an extension region surrounding the bottom of the trench is formed in the drift region, the conductivity type of the extension region is opposite to that of the drift region, and the depletion of the drift region can be enhanced by the extension region. Therefore, the inner field plate and the expansion region are formed, and under the combined action of the inner field plate and the expansion region, the depletion of the drift region can be increased, and the breakdown voltage of the drift region is improved. Meanwhile, the first trench gate and the second trench gate are used in a combined mode, so that the process cost can be reduced as far as possible while the depletion of the drift region is enhanced. Therefore, under the condition of equal breakdown voltage, the drift region of the semiconductor device in the application can increase the doping concentration, so that the on-resistance is reduced, namely, under the condition of equal breakdown voltage, the semiconductor device in the application has lower on-resistance and lower on-voltage drop.

Drawings

Fig. 1 is a schematic structural view of a semiconductor device which is an IGBT and a first conductive structure in contact with an extension region;

FIG. 2 is a schematic structural view of the semiconductor structure being an IGBT with the first conductive structure isolated from the extension region;

FIG. 3 is a schematic structural diagram of a semiconductor device being a MOS transistor and a first conductive structure contacting with an extension region;

FIG. 4 is a schematic diagram of a semiconductor structure being a MOS transistor with a first conductive structure isolated from an extension region;

FIG. 5 is a flow chart of steps in a method of fabricating a semiconductor device;

fig. 6a to 6j are cross-sectional views of structures corresponding to the steps related to the method for manufacturing a semiconductor device according to an embodiment.

Description of the reference symbols

A 100 drift region; a 110 body region; 111 a first doped region; 112 a second doped region; 121 a first trench gate; 122 a second trench gate; 130 a dielectric layer; 141 a first conductive structure; 142 a second conductive structure; 143 a third conductive structure; 150 expansion zone; 160 a second electrode lead-out region; 171 a first trench; 172 a second trench; 173 contact holes; 200 interlayer dielectric layers; 310 a first electrode; 320 a second electrode.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The semiconductor device in the present application is explained below with reference to fig. 1.

The semiconductor device includes:

drift region 100, drift region 100 having a first conductivity type, drift region 100 may be specifically an epitaxial layer grown by epitaxy on a semiconductor substrate;

the body region 110, the body region 110 having the second conductivity type, is formed in the drift region 100, specifically, formed on the upper surface layer of the drift region 100.

A first doped region 111 and a second doped region 112 both formed in the body region 110, wherein the first doped region 111 has a first conductivity type, the second doped region 112 has a second conductivity type, and a doping concentration of the second doped region 112 is higher than a doping concentration of the body region 110.

A first trench gate 121 and an extension region 150, the first trench gate 121 being formed by filling the first trench. The first trench penetrates through the first doped region 111 and the body region 112 and extends into the drift region 100, i.e., the bottom of the first trench is located in the drift region 100. The extension region 150 has the second conductivity type, and the extension region 150 is formed in the drift region 100 under the first trench and surrounds the bottom wall of the first trench. The first trench is filled with a first conductive structure 141 located at the bottom of the first trench and a second conductive structure 142 located at the top of the trench, the first conductive structure 141 and the second conductive structure 142 are isolated from each other, specifically, a dielectric layer can be formed between the first conductive structure 141 and the second conductive structure 142, and the conductive structures on the upper side and the lower side are isolated by the dielectric layer; a dielectric layer 130 is formed between the second conductive structure 142 and the inner wall of the first trench, and a dielectric layer 130 is also formed between the first conductive structure 141 and the inner wall of the first trench not surrounded by the extension region 150. It is understood that the depth of the second conductive structure 142 is greater than or equal to the depth of the two side body regions 110, so as to ensure that a conduction channel can be formed in the two side body regions 110.

The second trench gate 122 is formed by filling a second trench, which penetrates the first doped region 111 and the body region 110, and further, the second trench may also extend into the drift region 100. The second trench is filled with a third conductive structure 143 and a dielectric layer 130 between the third conductive structure 143 and the inner wall of the second trench.

And a gate (not shown) electrically connected to the second conductive structure 142 and the third conductive structure 143, wherein the second conductive structure 142 and the dielectric layers 130 on the two sides of the second conductive structure 142 form a gate structure, the third conductive structure 143 and the dielectric layers 130 on the two sides of the third conductive structure 143 also form a gate structure, and the gate structure is connected to the gate, so that a conducting channel can be formed in the body region 110 on the two sides of the gate structure after obtaining a potential from the gate.

And a first electrode 310 electrically connected to the first and second doped regions 111 and 112, and a second electrode lead-out region 150 contacting the drift region 100 and leading out a second electrode 320. It is understood that an interlayer dielectric layer 200 is further formed on each of the trench gate and the doped region, and the first electrode 310 is electrically connected to the first doped region 111 and the second doped region 112 through contact holes. When a potential is applied to the gate electrode to form a conducting channel in the body region, a current path can be formed between the first electrode 310 and the second electrode 320.

Specifically, the first conductive structure 141, the second conductive structure 142, and the third conductive structure 143 may be polysilicon, and the dielectric layer may be an oxide layer. The first conductive type is a P type and the second conductive type is an N type, or the first conductive type is an N type and the second conductive type is a P type.

The trench gate structure of the semiconductor device is divided into the first trench gate 121 and the second trench gate 122, wherein the second conductive structure 142 and the dielectric layer 130 on the upper half portion of the first trench gate 121 form a gate structure, and the first conductive structure 141 and the dielectric layer 130 on the lower half portion of the first trench 121 are equivalent to inner field plates, through which the electric field in the drift region can be adjusted, and the depletion of the drift region is enhanced. The bottom of the first trench gate 121 is surrounded by an extension region 150, and the extension region 150 is opposite to the conductivity type of the drift region 100, which can further enhance the depletion of the drift region 100. Therefore, under the combined action of the inner field plate and the expansion region, the depletion of the drift region can be enhanced, and the breakdown voltage of the drift region can be improved. Therefore, under the condition of the same breakdown voltage, the drift region 100 of the semiconductor device in the present application can increase the doping concentration, thereby reducing the on-resistance, that is, under the condition of the same breakdown voltage, the semiconductor device in the present application has lower on-resistance and on-voltage drop. On the other hand, the extension region 150 surrounds the bottom of the first trench, and the breakdown position can be shifted from the trench gate to the interface between the extension region 150 and the drift region 100, so that the breakdown is more stable. Meanwhile, the first trench gate 121 and the second trench gate 122 are used in combination, so that the process cost can be reduced as much as possible while the depletion of the drift region is enhanced.

In an embodiment, as shown in fig. 1, the first trench gates 121 and the second trench gates 122 are alternately distributed side by side, and further, the intervals between adjacent trench gates are equal, so that the distribution of the inner field plates and the extension regions is uniform, and therefore, the distribution of the depletion regions in the drift region 110 is uniform, and the withstand voltage of the device is further improved.

In one embodiment, as shown in fig. 1, the depth of the second trench is smaller than the depth of the first trench, i.e. the depth of the second trench gate 122 is smaller than the depth of the first trench gate 121. Further, the bottom of the second trench is flush with the top of the first conductive structure 141. In this embodiment, since the second trench gate 122 is only used as a gate structure and does not participate in the adjustment of the drift region 100, the extension length of the second trench gate 122 in the drift region 100 can be reduced on the premise of ensuring that the second trench gate 122 penetrates through the body region 110, so that the process cost can be reduced, the occupied space of the trench gate in the drift region 100 can be reduced, and the current intensity is prevented from being influenced by current crowding in the drift region 100.

In the present application, the distribution with respect to the first and second doping regions 111 and 112 may have various forms. In an embodiment, the first doped region 111 and the second doped region 112 may be formed side by side on an upper surface of the body region 110, and the first doped region 111 and the second doped region 112 are respectively extracted through different contact holes and electrically connected to the first electrode 310. In another embodiment, as shown in fig. 1, the first doped region 111 is formed on the upper surface of the body region 110, the second doped region 112 is formed in the body region 110 under the first doped region 111 and connected to the first doped region 111, the first doped region 111 is formed with a contact hole penetrating through the first doped region 111 and exposing the second doped region 112, and at this time, the first electrode 310 can be electrically connected to the first doped region 111 and the second doped region 112 through the contact hole.

In the present application, the first conductive structure 141 may be a floating structure (not connected to a potential), and may be electrically connected to the first electrode 310 to obtain a potential of the first electrode 310. When the first conductive structure 141 is electrically connected to the first electrode 310, the first conductive structure 141 may be specifically led out from one end of the first trench, and then directly electrically connected to the first electrode 310 through the contact hole, or a dielectric layer is disposed between the first conductive structure 141 and the first electrode 310, and the thickness of the dielectric layer between the first conductive structure 141 and the first electrode 310 is such that the first conductive structure 141 can obtain an induced potential from the first electrode 310. When the first conductive structure 141 and the first electrode 310 are electrically connected in an inductive manner, the first conductive structure 141 can obtain an induced potential, and a leakage path between the first electrode 310 and the first conductive structure 141 can be cut off, thereby preventing the first electrode 310 from leaking electricity. In one embodiment, when the first conductive structure 141 is electrically connected to the first electrode 310, the parasitic capacitance between the gate electrode and the second electrode 320 can be reduced.

In the present application, the specific design of the first trench gate 121 and the extension region 150 has various forms.

In an embodiment, a dielectric layer 130 is formed between the first conductive structure 141 and the inner wall of the first trench not surrounded by the extension region 150, and no dielectric layer is formed on at least a portion of the bottom wall of the first trench surrounded by the extension region 150, i.e., the extension region 150 is in contact with the first conductive structure 141. At this time, the extension region 150 and the first conductive structure 141 have the same potential, and if the first conductive structure 141 is a floating structure, the extension region 150 is also a floating structure; if the first conductive structure 141 is electrically connected to the first electrode 310, the extension region 150 may also have a certain potential by electrically connecting the first conductive structure 141 to the first electrode 310, so that depletion of the drift region 100 may be further enhanced.

In another embodiment, as shown in fig. 2, in an embodiment, a dielectric layer 130 is formed between the first conductive structure 141 and the inner wall of the first trench not surrounded by the extension region 150, and the bottom wall of the first trench surrounded by the extension region 150 is also covered by the dielectric layer, that is, the dielectric layer 130 is formed on the entire inner wall of the first trench, and the extension region 150 is isolated from the first conductive structure 141 by the dielectric layer 130. At this time, the extension regions 150 are all floating structures regardless of whether the first conductive structures 141 are charged, thereby further preventing electrode leakage.

In one embodiment, as shown in fig. 1 and 2, the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor), wherein the first electrode 310 is an emitter, the second electrode lead-out region 160 includes a collector region 162 and a buffer region 161 between the collector region 162 and the drift region 100, wherein the buffer region 161 has a first conductivity type and a doping concentration of the buffer region 161 is greater than a doping concentration of the drift region 100, the collector region 162 has a second conductivity type, and the second electrode 320 is a collector. Specifically, the second electrode lead-out region 160 is formed on a side of the drift region 100 away from the body region 110. In this embodiment, when the semiconductor device is an IGBT, the first trench gate 121 extends into the drift region 100 and the extension region 150 surrounds the bottom of the first trench gate 121, so that not only can the electric field in the drift region be adjusted, but also the recombination of the remaining carriers in the drift region 100 can be accelerated when the IGBT is turned off, thereby increasing the switching speed of the IGBT, and adjusting the switching characteristics of the device to optimize the device performance.

In an embodiment, as shown in fig. 3 and 4, the semiconductor device may also be a MOS transistor, wherein fig. 3 corresponds to a schematic structural diagram of the first conductive structure 141 contacting the extension region 150; fig. 4 corresponds to a schematic structure of the first conductive structure 141 isolated from the extension region 150. The first electrode 310 is a source, the second electrode lead-out region 160 has a first conductive type, and may be a semiconductor substrate having the first conductive type, and the second electrode 320 is a drain.

It should be noted that "N" and "P" in fig. 1 to 4 indicate conductivity types of corresponding regions, and fig. 1 to 4 illustrate that the first conductivity type is N-type and the second conductivity type is P-type, and in other embodiments, the first conductivity type may be P-type and the second conductivity type is N-type.

The present application also relates to a method of manufacturing a semiconductor device, as shown in fig. 5, the method comprising the steps of:

step S510: forming a drift region with a first conductivity type, forming a first groove on the drift region, and forming a dielectric layer on the inner wall of the first groove.

As shown in fig. 6a, a drift region 100 having a first conductivity type may be formed on a semiconductor substrate (not shown) by epitaxial growth, a first trench 171 is opened on the drift region 100, and a dielectric layer 130 is formed on an inner wall of the first trench 171. The dielectric layer 130 may be an oxide layer, and specifically, an oxide layer may be grown on the inner wall of the first trench 171 through a thermal oxidation process.

Step S520: doping impurities with the second conductivity type into the drift region at the bottom of the first trench through the first trench to form an extension region surrounding the bottom wall of the first trench.

As shown in fig. 6b, the drift region 100 is doped with the second conductive type dopant impurities through the first trenches 171, forming extension regions 150 surrounding the bottom wall contacts of the first trenches 171.

Step S530: and filling the first conductive structure into the first groove.

As shown in fig. 6c, the first conductive structure 141 is filled into the first trench 171. Specifically, the first conductive structure 141 may be polysilicon.

In an embodiment, between step S520 and step S530, the method may further include:

and etching at least part of the dielectric layer on the bottom wall of the first groove surrounded by the extension region to expose the extension region.

Specifically, the dielectric layer 130 on the bottom wall of the first trench 171 may be dry etched to form an opening exposing the extension region 150. At this time, in step S530, after the first conductive structure 141 is filled, the first conductive structure 141 is in contact with the extension region 150.

Step S540: and simultaneously etching the first conductive structure in the first groove and the drift regions at two sides of the first groove, removing the first conductive structure at the top of the first groove and reserving the first conductive structure at the bottom of the first groove, and simultaneously forming second grooves at two sides of the first groove.

As shown in fig. 6d, the first conductive structure 130 in the first trench 171 and the drift region 100 on both sides of the first trench are etched simultaneously, the first conductive structure on the top of the first trench 171 is removed and the first conductive structure 130 on the bottom of the first trench 171 is remained, and simultaneously, the second trench 172 is formed on both sides of the first trench 171. Since the etching of the first conductive structure 130 and the etching of the drift region 100 are performed simultaneously, the etching process etches the first conductive structure 130 to the same depth as the drift region 100, i.e., the bottom of the second trench 172 is flush with the top of the remaining first conductive structure 141.

Step S550: and filling dielectric layers in the first groove and the second groove.

As shown in fig. 6e, the first trench 171 and the second trench 172 are simultaneously filled with the dielectric layer 130. Specifically, a thicker dielectric layer 130 may be deposited by a deposition process to fill the first trench 171 and the second trench 172, and then the extra dielectric layer outside the trenches is removed by a grinding process.

Step S560: and simultaneously etching and removing partial dielectric layers at the top of the first groove and the top of the second groove, and reserving partial dielectric layers on the first conductive structure and the bottom of the second groove.

As shown in fig. 6f, a portion of the dielectric layer on top of the first trench 171 and on top of the second trench 172 is etched simultaneously, leaving a portion of the dielectric layer on the first conductive structure 141 and a portion of the dielectric layer on the bottom of the second trench 172.

Step S570: and simultaneously forming a dielectric layer on the exposed side walls of the first trench and the second trench, and then simultaneously filling a conductive material into the first trench and the second trench to respectively form a second conductive structure positioned at the top of the first trench and a third conductive structure positioned in the second trench.

As shown in fig. 6g, a dielectric layer is formed on the exposed sidewalls of the first trench and the second trench, and then a conductive material is filled into the first trench and the second trench, the conductive material filled in the top of the first trench forms a second conductive structure 142, and the conductive material filled in the second trench forms a third conductive structure 143. Specifically, the conductive material may be polysilicon. At this time, the first trench gate 121 is formed by the structure filled in the first trench, the second trench gate 122 is formed by the structure filled in the second trench, the bottom of the first trench gate 121 is surrounded by the extension region 150, and the depth of the first trench gate 121 is greater than that of the second trench gate 122.

Step S580: doping impurities with a second conductive type into the drift region, forming body regions on two sides of the first trench and the second trench, doping impurities with the first conductive type and doping impurities with the second conductive type into the body regions, and forming a first doped region and a second doped region respectively.

The second doping region is higher than the body region in doping concentration and is separated from the first trench and the second trench.

In an embodiment, between step S570 and step S580, the following steps are further included:

and respectively forming dielectric layers covering the second conductive structure and the third conductive structure at the tops of the first groove and the second groove. Specifically, as shown in fig. 6e, portions of the second conductive structure 142 and the third conductive structure 143 at the top of the trench may be etched away, and then an oxide layer may be grown on top of the first conductive structure 142 and the third conductive structure 143 by thermal oxidation. In this embodiment, an oxide layer is grown on top of the first conductive structure 142 and the third conductive structure 143, and impurity doping in the second conductive structure 142 and the third conductive structure 143 of the trench may be blocked when the impurity doping is performed in step S580.

As shown in fig. 6h, after the first and second trench gates 121 and 122 are formed, the upper surface layer of the drift region 100 is doped with the doping impurities having the second conductivity type, and the body regions 110 contacting the sidewalls of the first and second trenches 121 and 122 are formed at both sides of the first and second trenches. It will be appreciated that the depth of body region 110 is less than or equal to the depth of second trench gate 122.

In an embodiment, the process of forming the body region 110 is specifically a high temperature drive-in process, wherein the temperature and time of the high temperature drive-in process can be adjusted according to the doping depth and the doping concentration of the body region, specifically, the temperature range of the high temperature drive-in process can be controlled between 900 ℃ and 1200 ℃, and the time range of the high temperature drive-in process can be controlled between 10min and 180 min. While the high temperature drive-in forms the body region 110, the dopant ions of the extension region 150 out-diffuse, causing the extension region 150 to expand outward, thereby increasing the volume of the extension region 150.

Specifically, the distribution of the first doped region 111 and the second doped region 112 has various forms, and correspondingly, the process for forming the first doped region 111 and the second doped region 112 has various options. In an embodiment, as shown in fig. 6h and 6i, the first doped region 111 overlaps the second doped region 112, and the corresponding process steps may include:

step S581: an upper surface layer of the body region 110 is doped with a doping impurity having the first conductive type to form a first doping region 111 in contact with the first and second trenches.

Step S582: contact holes 173 penetrating the first doping region 111 and exposing the body region 110 are opened, and doping impurities having the second conductivity type are doped into the exposed body region 110 through the contact holes to form a second doping region 112 under the first doping region 111. Further, the contact holes 173 may extend into the body region 110.

Step S583: the body region 110, which is body-exposed through the contact hole 173, is doped with doping impurities having the second conductive type to form the second doping region 112. Thereafter, the first electrode 310 can be electrically connected to the first and second doping regions 111 and 112 through the contact hole 173, respectively.

Further, between step S581 and step S582, the method further includes:

an interlayer dielectric layer 200 is formed on the first trench gate 121, the second trench gate 122 and the first doped region 111. In step S582, before etching the first doped region 111, the interlayer dielectric layer 200 is further etched, so that the contact hole 173 penetrates through the interlayer dielectric layer 200.

Step S590: and forming a grid electrode electrically connected with the second conductive structure and the third conductive structure, a first electrode electrically connected with the first doped region and the second doped region, and leading out a second electrode through a second electrode leading-out region contacted with the drift region.

In one embodiment, as shown in fig. 6j, a first electrode 310 and a gate electrode (not shown) are formed, and the second electrode 320 is led out through the second electrode lead-out region 160.

In an embodiment, when the first doped region 111 and the second doped region 112 are formed through the steps S581 to S583, contact holes penetrating through the first doped region 111 and extending into the second doped region 112 are simultaneously formed, and the first doped region 111 and the second doped region 112 are exposed through the contact holes, so that when the first electrode 310 is formed, only one metal layer needs to be deposited and filled in the contact holes, and the first electrode 310 can be electrically connected to the first doped region 111 and the second doped region 112.

In an embodiment, as shown in fig. 6j, the semiconductor device is specifically an IGBT, the semiconductor device is an IGBT, the first electrode 310 is an emitter, the second electrode lead-out region 160 includes a collector region 162 and a buffer region 161 located between the collector region 162 and the drift region 100, and the second electrode lead-out region 160 may be specifically formed in step S590. The buffer region 161 has a first conductivity type, the doping concentration of the buffer region 161 is greater than that of the drift region 100, the collector region 162 has a second conductivity type, and the second electrode 320 is a collector. Specifically, the second electrode lead-out region 160 is formed on a side of the drift region 100 away from the body region 110.

In an embodiment, the semiconductor device may also be a MOS transistor, as shown in fig. 3 and 4. The first electrode 310 is a source, the second electrode lead-out region 160 has a first conductive type, and may be a semiconductor substrate having the first conductive type, and the second electrode 320 is a drain.

In the above semiconductor device manufacturing method, a first trench gate 121 and a second trench gate 122 are formed in a cell region, wherein the upper half of the first trench gate 121 forms a gate structure, the lower half of the first trench gate 121 corresponds to an internal field plate, and meanwhile, the bottom of the first trench gate 121 is surrounded by an extension region 150, and the conductivity type of the extension region 150 is opposite to that of the drift region 100. Therefore, under the combined action of the inner field plate and the expansion region, the depletion of the drift region can be enhanced, and the breakdown voltage of the drift region can be improved. On the other hand, the extension region 150 surrounds the bottom of the first trench, and the breakdown position can be shifted from the trench gate to the interface between the extension region 150 and the drift region 100, so that the breakdown is more stable. Meanwhile, since the second trench gate 122 and the upper half structure of the first trench are both used as gate structures, in the process, after the first conductive structure 141 is formed and the dielectric layer is filled in the first trench, the second trench gate 122 and the structure in the first trench on the first conductive structure 141 can be synchronously formed, thereby saving the process cost.

The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.