阅读说明：本技术 一种cmos信息的清除方法、电子设备及清除芯片 (Method for clearing CMOS information, electronic equipment and clearing chip ) 是由 彭石军 于 2020-05-21 设计创作，主要内容包括：本发明实施例提供了一种CMOS信息的清除方法、电子设备及清除芯片,所述方法应用于电子设备中的清除芯片,所述电子设备还包括处理芯片,所述处理芯片包括实时时钟RTC电池的RTC重置引脚,所述清除芯片与所述RTC重置引脚电连接,所述方法包括：在所述处理芯片执行开机程序时开始计时；在计时时长达到预设时长,且未接收到开机正常信号的情况下,控制所述RTC重置引脚接地,以清除所述电子设备的CMOS信息。这样,可以在开机异常时控制RTC重置引脚接地,从而重置RTC寄存器,自动清除电子设备的CMOS信息,无需进行手动操作,便捷性大大提高。(The embodiment of the invention provides a CMOS information clearing method, electronic equipment and a clearing chip, wherein the method is applied to the clearing chip in the electronic equipment, the electronic equipment also comprises a processing chip, the processing chip comprises an RTC reset pin of a real-time clock (RTC) battery, and the clearing chip is electrically connected with the RTC reset pin, and the method comprises the following steps: starting timing when the processing chip executes a starting program; and controlling the RTC reset pin to be grounded to clear the CMOS information of the electronic equipment under the condition that the timing time reaches the preset time and a normal starting signal is not received. Therefore, the RTC reset pin can be controlled to be grounded when the starting is abnormal, so that the RTC register is reset, the CMOS information of the electronic equipment is automatically cleared, manual operation is not needed, and the convenience is greatly improved.)

1. A CMOS information clearing method is applied to a clearing chip in electronic equipment, the electronic equipment further comprises a processing chip, the processing chip comprises an RTC reset pin of a real-time clock (RTC) battery, and the clearing chip is electrically connected with the RTC reset pin, and the method comprises the following steps:

starting timing when the processing chip executes a starting program;

and controlling the RTC reset pin to be grounded to clear the CMOS information of the electronic equipment under the condition that the timing time reaches the preset time and a normal starting signal is not received.

2. The method of claim 1, wherein the clear-up chip is electrically connected to the RTC reset pin through a MOS transistor, the clear-up chip is electrically connected to a gate of the MOS transistor, the RTC reset pin is electrically connected to a drain of the MOS transistor, and a source of the MOS transistor is grounded;

the step of controlling the RTC reset pin to ground includes:

and outputting a high level to the grid electrode of the MOS tube so as to switch on the drain electrode and the source electrode of the MOS tube.

3. The method of claim 1 or 2, wherein the electronic device further comprises a switching circuit electrically connected to the processing chip, the purging chip, and a power supply, respectively;

prior to the step of controlling the RTC reset pin to ground, the method further comprises:

controlling the switch circuit to be in an off state so as to close the power supply of the processing chip;

after the step of clearing the CMOS information of the electronic device, the method further comprises:

and when the grounding time of the RTC reset pin reaches a preset value, controlling the RTC reset pin to recover a non-grounding state and controlling the switch circuit to be in a switch-on state so as to enable the processing chip to execute the starting program.

4. The method of claim 1 or 2, wherein the electronic device further comprises a power-on key electrically connected to the clear chip;

before the step of starting timing when the processing chip executes the boot program, the method further includes:

reading the stored starting-up identification when the electronic equipment is powered on;

when the starting-up mark represents power-on self-starting, executing a preset monitoring program to monitor whether a starting-up normal signal is received or not, and determining that the processing chip starts to execute the starting-up program;

when the starting-up mark shows that the power-on is not self-started, and a first starting-up signal generated when the starting-up key is triggered is received, executing a preset monitoring program to monitor whether a normal starting-up signal is received or not, and determining that the processing chip starts to execute the starting-up program.

5. The method of claim 4, wherein the electronic device further comprises a startup control chip electrically connected to the clear chip, the processing chip, and the startup key, respectively; the method further comprises the following steps:

when a first normal starting signal sent by the processing chip is received, determining that the electronic equipment is normally started, and when a starting identifier sent by the processing chip is received, updating the stored starting identifier to be the received starting identifier, wherein the first normal starting signal is sent when a starting program is executed after the processing chip is powered on, or is sent when a second starting signal sent by the starting control chip is received after the processing chip is powered on and the starting program is executed, and the second starting signal is sent when the starting control chip receives a third starting signal generated when the starting key is triggered; alternatively, the first and second electrodes may be,

when a second normal starting signal sent by the starting control chip is received, the electronic equipment is determined to be started normally, and when a starting identifier sent by the processing chip is received, the stored starting identifier is updated to be the received starting identifier, wherein the second normal starting signal is sent when a notification signal sent by the processing chip is received, and the notification signal is sent when a starting program is executed after the processing chip is powered on, or is sent when the processing chip is powered on, the second starting signal sent by the starting control chip is received and the starting program is executed.

6. An electronic device, comprising a clearing chip and a processing chip, wherein the processing chip comprises an RTC reset pin of a real-time clock (RTC) battery, and the clearing chip is electrically connected with the RTC reset pin;

the processing chip is used for executing a starting program;

the clearing chip is used for starting timing when the processing chip executes the starting program, and controlling the RTC reset pin to be grounded under the condition that the timing time reaches the preset time and the normal starting signal is not received so as to clear the CMOS information of the electronic equipment.

7. The electronic device of claim 6, wherein the clear chip is electrically connected to the RTC reset pin through a MOS transistor, the clear chip is electrically connected to a gate of the MOS transistor, the RTC reset pin is electrically connected to a drain of the MOS transistor, and a source of the MOS transistor is grounded;

the clearing chip is specifically used for outputting a high level to a grid electrode of the MOS tube so as to enable a drain electrode and a source electrode of the MOS tube to be connected.

8. The electronic device of claim 6 or 7, further comprising a switching circuit electrically connected to the processing chip, the purging chip, and a power supply, respectively;

the clearing chip is further used for controlling the switch circuit to be in an off state to turn off the power supply of the processing chip before controlling the RTC reset pin to be grounded; after the CMOS information of the electronic equipment is cleared, when the grounding time of the RTC reset pin reaches a preset value, the RTC reset pin is controlled to recover a non-grounding state, and the switch circuit is controlled to be in a switch-on state, so that the processing chip executes the boot program.

9. The electronic device of claim 6 or 7, further comprising a power-on key electrically connected to the clear chip;

the starting-up key is used for generating a first starting-up signal when being triggered and sending the first starting-up signal to the clearing chip;

the clearing chip is also used for reading the stored starting-up identification when the electronic equipment is powered on; when the starting-up mark represents power-on self-starting, executing a preset monitoring program to monitor whether a starting-up normal signal is received or not, and determining that the processing chip starts to execute the starting-up program; when the starting-up mark indicates that the power-on is not self-started, when the first starting-up signal is received, executing a preset monitoring program to monitor whether a normal starting-up signal is received or not, and determining that the processing chip starts to execute the starting-up program.

10. The electronic device of claim 9, further comprising a power-on control chip electrically connected to the clear chip, the processing chip, and the power-on key, respectively;

the startup key is also used for generating a third startup signal when being triggered and sending the third startup signal to the startup control chip;

the starting control chip is used for sending a second starting signal to the processing chip after receiving the third starting signal;

the processing chip is specifically configured to execute the boot program when powered on, and send a first boot normal signal and a boot identifier to the clearing chip when the boot program is executed, or send a notification signal to the boot control chip when the boot program is executed, and send the boot identifier to the clearing chip; alternatively, the first and second electrodes may be,

the startup control chip is further configured to send a second startup normal signal to the clearing chip when receiving the notification signal;

and the clearing chip is also used for determining that the electronic equipment is normally started when the first startup normal signal and the startup mark are received or the second startup normal signal and the startup mark are received, and updating the stored startup mark as the received startup mark.

11. The electronic device of claim 10, wherein the startup control chip is one of a Super IO chip, a BMC chip, and an EC chip.

12. The electronic device of claim 6 or 7, wherein the clear-up chip is a single chip microcomputer.

13. The clearing chip is characterized by comprising a processor, a communication interface, a memory and a bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the bus;

a memory for storing a computer program;

a processor for implementing the method steps of any one of claims 1 to 5 when executing a program stored in the memory.

14. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method steps of any one of the claims 1-5.

Technical Field

The invention relates to the technical field of computer information processing, in particular to a method for clearing CMOS information, electronic equipment and a clearing chip.

Background

A CMOS (Complementary Metal Oxide Semiconductor) refers to a chip for storing Basic start-up information of a computer, such as date, time, start-up setting, etc., and is a readable and writable RAM (random access memory) chip on a motherboard, which can store hardware configuration of a BIOS (Basic Input Output System) and settings of some parameters by a user.

During the use of the computer, abnormal shutdown and other operations may be caused for various reasons, and such abnormal operations may cause the CMOS information of the system to be confused, and the confused CMOS information may cause the computer to be unable to be normally started. General computers are provided with RTC (Real-time clock) batteries, generally button batteries, for supplying power to CMOS, so as to ensure that CMOS information is not lost when the computer is powered off.

Therefore, at present, when the computer is abnormally started, the RTC battery can be pulled out manually, or a jump cap or a key can be arranged on a general mainboard, and the reset pin of the RTC battery can be grounded by manually short-circuiting the jump cap or pressing the key, so that the RTC register is reset, the CMOS information is recovered to be default, namely, the CMOS information is cleared, and the computer can be normally started. However, both methods must be manually operated, which is very inconvenient.

Disclosure of Invention

The embodiment of the invention aims to provide a method for clearing CMOS information, electronic equipment and a clearing chip so as to improve the convenience of clearing the CMOS information. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present invention provides a method for clearing CMOS information, which is applied to a clearing chip in an electronic device, where the electronic device further includes a processing chip, the processing chip includes an RTC reset pin of an RTC battery, and the clearing chip is electrically connected to the RTC reset pin, and the method includes:

starting timing when the processing chip executes a starting program;

and controlling the RTC reset pin to be grounded to clear the CMOS information of the electronic equipment under the condition that the timing time reaches the preset time and a normal starting signal is not received.

Optionally, the clear chip is electrically connected to the RTC reset pin through an MOS transistor, the clear chip is electrically connected to a gate of the MOS transistor, the RTC reset pin is electrically connected to a drain of the MOS transistor, and a source of the MOS transistor is grounded;

the step of controlling the RTC reset pin to ground includes:

and outputting a high level to the grid electrode of the MOS tube so as to switch on the drain electrode and the source electrode of the MOS tube.

Optionally, the electronic device further includes a switch circuit, and the switch circuit is electrically connected to the processing chip, the clearing chip and the power supply respectively;

prior to the step of controlling the RTC reset pin to ground, the method further comprises:

controlling the switch circuit to be in an off state so as to close the power supply of the processing chip;

after the step of clearing the CMOS information of the electronic device, the method further comprises:

and when the grounding time of the RTC reset pin reaches a preset value, controlling the RTC reset pin to recover a non-grounding state and controlling the switch circuit to be in a switch-on state so as to enable the processing chip to execute the starting program.

Optionally, the electronic device further includes a power-on key, and the power-on key is electrically connected to the clear chip;

before the step of starting timing when the processing chip executes the boot program, the method further includes:

reading the stored starting-up identification when the electronic equipment is powered on;

when the starting-up mark represents power-on self-starting, executing a preset monitoring program to monitor whether a starting-up normal signal is received or not, and determining that the processing chip starts to execute the starting-up program;

when the starting-up mark shows that the power-on is not self-started, and a first starting-up signal generated when the starting-up key is triggered is received, executing a preset monitoring program to monitor whether a normal starting-up signal is received or not, and determining that the processing chip starts to execute the starting-up program.

Optionally, the electronic device further includes a startup control chip, and the startup control chip is electrically connected to the clear chip, the processing chip, and the startup key, respectively; the method further comprises the following steps:

when a first normal starting signal sent by the processing chip is received, determining that the electronic equipment is normally started, and when a starting identifier sent by the processing chip is received, updating the stored starting identifier to be the received starting identifier, wherein the first normal starting signal is sent when a starting program is executed after the processing chip is powered on, or is sent when a second starting signal sent by the starting control chip is received after the processing chip is powered on and the starting program is executed, and the second starting signal is sent when the starting control chip receives a third starting signal generated when the starting key is triggered; alternatively, the first and second electrodes may be,

when a second normal starting signal sent by the starting control chip is received, the electronic equipment is determined to be started normally, and when a starting identifier sent by the processing chip is received, the stored starting identifier is updated to be the received starting identifier, wherein the second normal starting signal is sent when a notification signal sent by the processing chip is received, and the notification signal is sent when a starting program is executed after the processing chip is powered on, or is sent when the processing chip is powered on, the second starting signal sent by the starting control chip is received and the starting program is executed.

In a second aspect, an embodiment of the present invention provides an electronic device, where the electronic device includes a clearing chip and a processing chip, the processing chip includes an RTC reset pin of an RTC battery, and the clearing chip is electrically connected to the RTC reset pin;

the processing chip is used for executing a starting program;

the clearing chip is used for starting timing when the processing chip executes the starting program, and controlling the RTC reset pin to be grounded under the condition that the timing time reaches the preset time and the normal starting signal is not received so as to clear the CMOS information of the electronic equipment.

Optionally, the clear chip is electrically connected to the RTC reset pin through an MOS transistor, the clear chip is electrically connected to a gate of the MOS transistor, the RTC reset pin is electrically connected to a drain of the MOS transistor, and a source of the MOS transistor is grounded;

the clearing chip is specifically used for outputting a high level to a grid electrode of the MOS tube so as to enable a drain electrode and a source electrode of the MOS tube to be connected.

Optionally, the electronic device further includes a switch circuit, and the switch circuit is electrically connected to the processing chip, the clearing chip and the power supply respectively;

the clearing chip is further used for controlling the switch circuit to be in an off state to turn off the power supply of the processing chip before controlling the RTC reset pin to be grounded; after the CMOS information of the electronic equipment is cleared, when the grounding time of the RTC reset pin reaches a preset value, the RTC reset pin is controlled to recover a non-grounding state, and the switch circuit is controlled to be in a switch-on state, so that the processing chip executes the boot program.

Optionally, the electronic device further includes a power-on key, and the power-on key is electrically connected to the clear chip;

the starting-up key is used for generating a first starting-up signal when being triggered and sending the first starting-up signal to the clearing chip;

the clearing chip is also used for reading the stored starting-up identification when the electronic equipment is powered on; when the starting-up mark represents power-on self-starting, executing a preset monitoring program to monitor whether a starting-up normal signal is received or not, and determining that the processing chip starts to execute the starting-up program; when the starting-up mark indicates that the power-on is not self-started, when the first starting-up signal is received, executing a preset monitoring program to monitor whether a normal starting-up signal is received or not, and determining that the processing chip starts to execute the starting-up program.

Optionally, the electronic device further includes a startup control chip, and the startup control chip is electrically connected to the clear chip, the processing chip, and the startup key, respectively;

the startup key is also used for generating a third startup signal when being triggered and sending the third startup signal to the startup control chip;

the starting control chip is used for sending a second starting signal to the processing chip after receiving the third starting signal;

the processing chip is specifically configured to execute the boot program when powered on, and send a first boot normal signal and a boot identifier to the clearing chip when the boot program is executed, or send a notification signal to the boot control chip when the boot program is executed, and send the boot identifier to the clearing chip; alternatively, the first and second electrodes may be,

the startup control chip is further configured to send a second startup normal signal to the clearing chip when receiving the notification signal;

and the clearing chip is also used for determining that the electronic equipment is normally started when the first startup normal signal and the startup mark are received or the second startup normal signal and the startup mark are received, and updating the stored startup mark as the received startup mark.

Optionally, the startup control chip is one of a Super IO chip, a BMC chip, and an EC chip.

Optionally, the clearing chip is a single chip microcomputer.

In a third aspect, an embodiment of the present invention provides an erasing chip, including a processor, a communication interface, a memory, and a bus, where the processor, the communication interface, and the memory complete mutual communication through the bus;

a memory for storing a computer program;

a processor adapted to perform the method steps of any of the above first aspects when executing a program stored in the memory.

In a fourth aspect, the present invention provides a computer-readable storage medium, in which a computer program is stored, and the computer program, when executed by a processor, implements the method steps of any one of the above first aspects.

The embodiment of the invention has the following beneficial effects:

in the scheme provided by the embodiment of the invention, the clearing chip can start timing when the processing chip executes the starting program, and the RTC reset pin is controlled to be grounded under the condition that the timing time reaches the preset time and the normal starting signal is not received so as to clear the CMOS information of the electronic equipment. Therefore, the RTC reset pin can be controlled to be grounded when the starting is abnormal, so that the RTC register is reset, the CMOS information of the electronic equipment is automatically cleared, manual operation is not needed, and the convenience is greatly improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

FIG. 2 is a flowchart of a method for removing CMOS information according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another electronic device according to the embodiment shown in FIG. 1;

FIG. 4 is a schematic structural diagram of another electronic device according to the embodiment shown in FIG. 1;

FIG. 5 is a schematic structural diagram of another electronic device according to the embodiment shown in FIG. 1;

FIG. 6 is a flowchart illustrating a method for determining how to start executing a boot program by the processing chip according to the embodiment shown in FIG. 2;

FIG. 7 is a schematic structural diagram of another electronic device according to the embodiment shown in FIG. 1;

fig. 8 is a schematic structural diagram of a clear chip according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to improve convenience of removing CMOS information, embodiments of the present invention provide a CMOS information removal method, an electronic device, a removal chip, and a computer-readable storage medium.

First, a method for removing CMOS information according to an embodiment of the present invention will be described. The method for clearing the CMOS information provided by the embodiment of the invention can be applied to a clearing chip in electronic equipment. As shown in fig. 1, the electronic device includes a clear chip 110 and a processing chip 120, the processing chip 120 includes an RTC reset pin 130 (denoted by RTCRST # in fig. 1) of an RTC battery 140, and the clear chip 110 is electrically connected to the RTC reset pin 130.

As shown in fig. 2, a method for removing CMOS information is applied to a removal chip in an electronic device, and the method includes:

s201, starting timing when the processing chip executes a starting program;

and S202, when the timing duration reaches a preset duration and a normal starting signal is not received, controlling the RTC reset pin to be grounded so as to clear the CMOS information of the electronic equipment.

Therefore, in the scheme provided by the embodiment of the invention, the clearing chip can start timing when the processing chip executes the startup program, and control the RTC reset pin to be grounded to clear the CMOS information of the electronic device when the timing duration reaches the preset duration and the normal startup signal is not received. Therefore, the RTC reset pin can be controlled to be grounded when the starting is abnormal, so that the RTC register is reset, the CMOS information of the electronic equipment is automatically cleared, manual operation is not needed, and the convenience is greatly improved.

When the electronic device is started, the BIOS in the processing chip runs a starting process to start the electronic device and complete basic settings of the electronic device. The Processing chip may be a Central Processing Unit (CPU), and the CPU generally provides high-speed signal interfaces such as a memory and a display for Processing various data. The processing chip may also be a PCH (Platform control Hub), and the PCH may provide a Controller with interfaces such as pcie (peripheral component interconnect express), SATA (Serial Advanced Technology Attachment), USB (Universal Serial Bus), and the like.

The processing chip may further include a CPU and a PCH, for example, in an Intel Desktop system (Desktop), the PCH and the CPU form a complete X86 system. In one embodiment, the CPU and PCH may be integrated together physically to form a processing chip.

When the processing chip starts to execute the boot program, it indicates that the electronic device starts to execute the boot process at this time, and since the time length required for completing the normal execution of the boot process is generally within a certain range, the clearing chip may start to time in order to determine whether the electronic device is normally booted. In one embodiment, the clear chip may start a timer to start timing.

Further, in the step S202, when the timing duration reaches the preset duration and the normal power-on signal is not received, it indicates that the electronic device is abnormal when the electronic device is powered on, and then to eliminate the abnormality, the clearing chip may control the RTC reset pin to be grounded, so that the RTC battery discharges, the RTC register may be reset, the CMOS information of the electronic device may be cleared, and then the electronic device may be normally powered on.

The preset time duration may be set according to statistical data of the time duration required for starting the electronic device, and may be, for example, 30 seconds, 50 seconds, 1 minute, and the like, which is not specifically limited herein. The normal startup signal may be a signal with a special waveform that is sent by the processing chip to the clearing chip after the electronic device is normally started up and is used for identifying normal startup, or may be sent by the processing chip to the clearing chip through other devices in the electronic device, which is also reasonable.

If the cleaning chip receives a normal starting signal within the preset time length, the electronic equipment is normally started at the moment, and then no operation is needed; if the clearing chip does not receive the normal starting signal within the preset time length, which indicates that the electronic equipment is abnormally started at the moment, the RTC reset pin can be controlled to be grounded so as to clear the CMOS information of the electronic equipment.

In an embodiment, the erase chip may be a single chip, the single chip is an integrated circuit chip, and a small and perfect microcomputer system is formed by integrating a central processing unit with data processing capability, a random access memory, a read only memory, multiple I/O (Input/Output) interfaces, an interrupt system, a timer, a counter, and other functions on a silicon chip by using a very large scale integrated circuit technology. The single chip microcomputer can also comprise a display driving circuit, a pulse width modulation circuit, an analog multiplexer, an analog/digital (A/D) converter and the like. It may control the RTC reset pin to ground in a variety of ways, e.g., through a switch control circuit, etc.

As an implementation manner of the embodiment of the present invention, as shown in fig. 3, the erase chip 110 may be electrically connected to the RTC reset pin 130 through a Metal Oxide Semiconductor (MOS) transistor 150, the erase chip 110 is electrically connected to a gate 151 of the MOS transistor 150, the RTC reset pin 130 is electrically connected to a drain 152 of the MOS transistor 150, and a source 153 of the MOS transistor 150 is grounded.

Accordingly, the step of controlling the RTC reset pin to be grounded may include:

and outputting a high level to the grid electrode of the MOS tube so as to switch on the drain electrode and the source electrode of the MOS tube.

In order to ground the RTC reset pin, the clear chip may output a high level to the gate of the MOS transistor, and the operating principle of the MOS transistor indicates that when the gate of the MOS transistor is input with the high level, since the source of the MOS transistor is grounded, a voltage difference between the gate and the source may cause a conductive channel to be formed between the drain and the source of the MOS transistor, and the drain and the source of the MOS transistor are also turned on, so that the RTC reset pin electrically connected to the drain of the MOS transistor is also grounded.

The high level output by the clearing chip needs to be not less than the turn-on voltage of the MOS transistor, the turn-on voltage is the gate voltage required for starting forming a conductive channel between the source and the drain, and the specific value may be determined according to the specific model of the MOS transistor, which is not specifically limited herein.

For example, as shown in fig. 3, the clearing chip 110 may pull up the voltage of the IO _3 interface to the turn-on voltage of the MOS transistor 150 for more than 2 seconds, and ground the RTCRST # pin (RTC reset pin) of the processing chip 120, so as to clear the CMOS information.

Therefore, in the embodiment, the clear chip can be electrically connected with the RTC reset pin through the MOS transistor, so that when the timing duration reaches the preset duration and the normal start-up signal is not received, the clear chip can output a high level to the gate of the MOS transistor to switch on the drain and the source of the MOS transistor, and at this time, the RTC reset pin is grounded, so that the CMOS information can be conveniently and quickly cleared.

As an implementation manner of the embodiment of the present invention, as shown in fig. 4, the electronic device may further include a switch circuit 160, and the switch circuit 160 may be electrically connected to the processing chip 120, the clearing chip 110, and a power supply (not shown in fig. 4), respectively. The switch circuit is used for supplying power to the processing chip when the power supply is switched on, namely supplying power to the processing chip when the electronic equipment is powered on.

In this case, before the step of controlling the RTC reset pin to be grounded, the method may further include:

and controlling the switch circuit to be in an off state so as to close the power supply of the processing chip.

Because the processing chip is in a power supply state at this moment, in order to protect the processing chip when the RTC reset pin is grounded, the switch circuit can be controlled to be in an off state firstly so as to close the power supply of the processing chip, and thus, the processing chip is also in a power-off state and does not run any more. For example, the clear chip control switch circuit is turned off to turn off the DSW (Deep Sleep Well) power supply or the SUS power supply of the processing chip.

Correspondingly, after the step of clearing the CMOS information of the electronic device, the method may further include:

and when the grounding time of the RTC reset pin reaches a preset value, controlling the RTC reset pin to recover a non-grounding state and controlling the switch circuit to be in a switch-on state so as to enable the processing chip to execute the starting program.

After the CMOS information is cleared, in order to enable the electronic device to be normally powered on, the clear chip may control the RTC reset pin to recover to the non-grounded state.

Then, the clearing chip can control the switch circuit to be in a connection state, and at the moment, the processing chip is electrified, so that a starting program can be executed, and the electronic equipment can be started normally. For example, as shown in fig. 4, the switch circuit 160 may be electrically connected to an IO _1 interface of the clear chip 110, and the clear chip 110 may control the on/off state of the switch circuit 160 through a serial port or an IO control.

Because the CMOS information needs a certain time to be cleared, in order to ensure the smooth clearing of the CMOS information, the RTC reset pin can be timed after being grounded, and when the timing duration reaches a preset value, the RTC reset pin is controlled to recover the non-grounded state. The preset value may be determined according to a time period required for clearing the CMOS information, and for example, may be 2 seconds, 3 seconds, 5 seconds, and the like, which is not specifically limited herein.

It can be seen that, in this embodiment, the electronic device may further include a switch circuit, which is electrically connected to the power supply to supply power to the processing chip, so that the clearing chip may control the switch circuit to be in an off state before controlling the RTC reset pin to be grounded, so as to turn off the power supply of the processing chip, and when the ground duration of the RTC reset pin reaches a preset value, the RTC reset pin is controlled to recover to the non-grounded state, and the switch circuit is controlled to be in an on state, so that the processing chip executes the boot program, which may protect the processing chip from being affected in the process of clearing the CMOS information, and ensure that the processing chip can smoothly execute the boot program when the switch circuit is turned on again, so that the electronic device can be smoothly booted.

As an implementation manner of the embodiment of the present invention, as shown in fig. 5, the electronic device may further include a power-on key 170, and the power-on key 170 is electrically connected to the clear chip 110. The electronic device generally has a power-on key, and the power-on key can be triggered to send a power-on signal through external triggering, for example, the power-on key can be triggered through pressing or the like.

The start-up setting for the electronic device can be divided into two types, specifically: power-on self-starting and power-on non-self-starting. The power-on self-starting is that after the electronic equipment is powered on, the BIOS in the processing chip starts to execute a power-on program without triggering a power-on key; the power-on is not self-started, that is, after the electronic equipment is powered on, the power-on key needs to be triggered, and the BIOS in the processing chip starts to execute the power-on program.

In an embodiment, as shown in fig. 5, the erasing chip may include an eeprom 111(Electrically-Erasable Programmable Read-Only Memory), which is a Memory chip in which data is not lost after power failure, and the data stored in the erasing chip may be Electrically erased, and the boot identifier may be stored in the eeprom, so that the boot identifier is not lost after the power failure of the electronic device.

In this case, as shown in fig. 6, before the step of starting timing when the processing chip executes the boot program, the method may further include:

s601, reading a stored starting-up identifier when the electronic equipment is powered on;

because the starting processes of the electronic equipment which is powered on and is not powered on are different, the stored starting identifier can be read when the electronic equipment is powered on before the cleaning chip starts timing so as to determine the starting setting of the electronic equipment.

The boot identifier may be in any computer-readable form, and may be a number or other characters, for example, "1" may be used as the boot identifier indicating power-on self-start, and "0" may be used as the boot identifier indicating that power-on is not self-start.

S602, when the starting-up mark represents power-on self-starting, executing a preset monitoring program to monitor whether a normal starting-up signal is received, and determining that the processing chip starts to execute the starting-up program;

when the starting up mark indicates power-on self-starting, the processing chip starts to execute the starting up program when being powered on, so that the clearing chip can immediately execute the preset monitoring program to monitor whether a normal starting up signal is received or not, and can determine that the processing chip starts to execute the starting up program at the same time so as to start timing.

The preset monitoring program can be a preset program for monitoring whether the normal startup signal is received, as long as the reception of the normal startup signal can be monitored.

S603, when the starting-up mark shows that the power-on is not self-started, and when a first starting-up signal generated when the starting-up key is triggered is received, executing a preset monitoring program to monitor whether a normal starting-up signal is received, and determining that the processing chip starts to execute the starting-up program.

When the power-on identifier indicates that the power-on is not self-started, after the power-on of the processing chip is finished, the power-on program is executed only after the power-on key is triggered, specifically, the power-on key generates a first power-on signal when triggered and sends the first power-on signal to the removal chip, at this time, the removal chip can determine that the electronic equipment starts to be started, and then starts to execute the preset monitoring program to monitor whether the normal power-on signal is received, and determines that the processing chip starts to execute the power-on program.

For example, as shown in fig. 5, the power-on key 170 is electrically connected to the IO _5 interface of the erase chip 110, so that when the power-on key 170 is triggered, a low level signal can be output to the IO _5 interface, and at this time, the erase chip 110 can start to run the preset monitoring program.

Therefore, in this embodiment, the electronic device may further include a power-on key electrically connected to the clear chip. And then under the two conditions that the starting of the electronic equipment is set to be powered on and not powered on, the cleaning chip can monitor whether a normal starting signal is received or not through a preset monitoring program, and further accurately determine whether the electronic equipment is started normally or not.

As an implementation manner of the embodiment of the present invention, as shown in fig. 7, the electronic device may further include a startup control chip 180, and the startup control chip 180 may be electrically connected to the clear chip 110, the processing chip 120, and the startup key 170, respectively.

The power-on control chip may be one of a Super IO chip (I/O chip), a BMC (Baseboard management Controller) chip, and an EC (Embedded Controller) chip, the Super IO chip is generally used in a desktop computer, and may be connected to a processing chip through an LPC (Low Pin Count) interface or an esii (Enhanced-peripheral serial interface), for example, in an X86 system, the Super IO chip may provide a Low-speed control interface such as a serial interface, a parallel interface, a floppy disk drive, a keyboard, and a mouse, and may also be used to monitor voltage, temperature, and rotation speed of devices such as a single chip.

As shown in fig. 7, the power-on control chip 180 may be electrically connected to an IO _4 interface of the erase chip 110, the power-on key may be electrically connected to a pin PSIN # of the power-on control chip 180, a pin PSOUT # of the power-on control chip 180 may be electrically connected to the processing chip 120, and the power-on control chip 180 and the processing chip 120 may also be electrically connected through an LPC interface or an eSPI interface to perform interaction of data signals.

Correspondingly, the method may further include:

and when a first normal starting signal sent by the processing chip is received, the electronic equipment is determined to be started normally, and when a starting identifier sent by the processing chip is received, the stored starting identifier is updated to be the received starting identifier. Or when a second normal starting signal sent by the starting control chip is received, the electronic equipment is determined to be normally started, and when the starting identifier sent by the processing chip is received, the stored starting identifier is updated to be the received starting identifier.

The first startup normal signal is sent when the processing chip is powered on and executes a startup program, or the first startup normal signal is sent when the processing chip is powered on and receives a second startup signal sent by the startup control chip and executes the startup program. The second starting-up signal is sent out when the starting-up control chip receives a third starting-up signal generated when the starting-up key is triggered.

The second startup normal signal is sent by the startup control chip when receiving the notification signal sent by the processing chip, and the notification signal is sent when the processing chip is powered on to execute the startup program, or sent when the processing chip is powered on to receive the second startup signal sent by the startup control chip and execute the startup program.

In one embodiment, when the power-on setting of the electronic device is not self-starting, after the electronic device is powered on, and when the power-on button is triggered, a low-level signal is sent to the pin PSIN # of the power-on control chip, and the low-level signal is used as the third power-on signal. At this time, the power-on control chip outputs a low level signal (the second power-on signal) to the processing chip at PSOUT #, and the processing chip starts to execute the power-on program. And then can send the normal signal of first start-up to clearing the chip when carrying out and finishing the start-up procedure, indicate the electronic equipment has already started up normally like this, clear the chip and do not need to carry on the clear operation of CMOS information.

When the starting-up setting of the electronic equipment is power-on self-starting, after the electronic equipment is powered on, the processing chip starts to execute a starting-up program. And then can send the normal signal of first start-up to clearing the chip when carrying out and finishing the start-up procedure, indicate the electronic equipment has already started up normally like this, clear the chip and do not need to carry on the clear operation of CMOS information.

As shown in fig. 7, the processing chip 120 may send the first power-on normal signal to the IO _2 interface of the clearing chip 110 through the IO interface.

In another embodiment, when the power-on setting of the electronic device is not self-starting, after the electronic device is powered on, and when the power-on button is triggered, a low-level signal is sent to the pin PSIN # of the power-on control chip, and the low-level signal is used as the third power-on signal. At this time, the power-on control chip outputs a low level signal (the second power-on signal) to the processing chip at PSOUT #, and the processing chip starts to execute the power-on program. And then can send the notice signal to the control chip of starting machine through LPC interface or eSPI interface when carrying out and finishing the starting program, the control chip of starting machine receives the notice signal and can send the normal signal of second start to clear up the chip, prove the electronic equipment has already started up normally like this, clear up the chip and do not need to carry on the clear up operation of CMOS information.

When the starting-up setting of the electronic equipment is power-on self-starting, after the electronic equipment is powered on, the processing chip starts to execute a starting-up program. And then can send the notice signal to the control chip of starting machine through LPC interface or eSPI interface when carrying out and finishing the starting program, the control chip of starting machine receives the notice signal and can send the normal signal of second start to clear up the chip, prove the electronic equipment has already started up normally like this, clear up the chip and do not need to carry on the clear up operation of CMOS information.

As shown in fig. 7, the power-on control chip 180 may send the second power-on normal signal to the IO _4 interface of the clear chip 110 through the IO interface.

In any of the above embodiments, the processing chip may send the boot identifier to the purging chip after executing the boot program, and at this time, the purging chip may update the stored boot identifier as the received boot identifier. In one embodiment, as shown in fig. 7, the processing chip 120 may be electrically connected to the clear chip through a bus such as UART (Universal Asynchronous Receiver/Transmitter)/I2C (Inter-Integrated Circuit), and further, after the BIOS in the processing chip executes the boot program, the boot identifier may be synchronized to the eprom of the clear chip through the bus such as UART/I2C.

It can be seen that, in this embodiment, the electronic device may further include a power-on control chip, and when a first power-on normal signal sent by the processing chip is received, or when a second power-on normal signal sent by the power-on control chip is received, it may be determined that the electronic device is normally powered on, and the power-on identifier may be updated at the same time, so as to ensure that the next power-on of the electronic device can perform corresponding operations according to the accurate power-on identifier.

Corresponding to the above-mentioned CMOS information clearing method, an embodiment of the present invention further provides an electronic device, as shown in fig. 1, the electronic device includes a clearing chip 110 and a processing chip 120, the processing chip 110 includes an RTC reset pin 130 of an RTC battery 140, and the clearing chip 110 is electrically connected to the RTC reset pin 130;

the processing chip 120 is configured to execute a boot program;

the clearing chip 110 is configured to start timing when the processing chip 120 executes the power-on program, and control the RTC reset pin 130 to be grounded when the timing duration reaches a preset duration and a normal power-on signal is not received, so as to clear the CMOS information of the electronic device.

Therefore, in the scheme provided by the embodiment of the invention, the clearing chip can start timing when the processing chip executes the startup program, and control the RTC reset pin to be grounded to clear the CMOS information of the electronic device when the timing duration reaches the preset duration and the normal startup signal is not received. Therefore, the RTC reset pin can be controlled to be grounded when the starting is abnormal, so that the RTC register is reset, the CMOS information of the electronic equipment is automatically cleared, manual operation is not needed, and the convenience is greatly improved.

As an implementation manner of the embodiment of the present invention, as shown in fig. 3, the clear chip 110 may be electrically connected to the RTC reset pin 130 through a MOS transistor 150, the clear chip 110 is electrically connected to a gate 151 of the MOS transistor 150, the RTC reset pin 130 is electrically connected to a drain 152 of the MOS transistor 150, and a source 153 of the MOS transistor 150 is grounded;

the clear chip 110 is specifically configured to output a high level to the gate 151 of the MOS transistor 150, so that the drain 152 and the source 153 of the MOS transistor 150 are connected.

As an implementation manner of the embodiment of the present invention, as shown in fig. 4, the electronic device may further include a switch circuit 160, where the switch circuit 160 is electrically connected to the processing chip 120, the clearing chip 110, and a power supply respectively;

the clear chip 110 is further configured to control the switch circuit 160 to be in an off state before controlling the RTC reset pin 130 to be grounded, so as to turn off the power supply of the processing chip 120; after the CMOS information of the electronic device is cleared, when the ground duration of the RTC reset pin 130 reaches a preset value, the RTC reset pin 130 is controlled to recover the non-ground state, and the switch circuit 160 is controlled to be in the on state, so that the processing chip 120 executes the boot program.

As an implementation manner of the embodiment of the present invention, as shown in fig. 5, the electronic device further includes a power-on key 170, where the power-on key 170 is electrically connected to the clear chip 110;

the boot key 170 is configured to generate a first boot signal when triggered, and send the first boot signal to the clear chip 110;

the clear chip 110 is further configured to read a stored boot identifier when the electronic device is powered on; when the power-on identifier indicates power-on self-start, executing a preset monitoring program to monitor whether a normal power-on signal is received, and determining that the processing chip 120 starts to execute the power-on program; when the power-on identifier indicates that the power-on is not self-started, and when the first power-on signal is received, a preset monitoring program is executed to monitor whether a normal power-on signal is received, and the processing chip 120 is determined to start executing the power-on program.

As an implementation manner of the embodiment of the present invention, as shown in fig. 7, the electronic device further includes a startup control chip 180, and the startup control chip 180 is electrically connected to the clear chip 110, the processing chip 120, and the startup key 170, respectively;

the startup key 170 is further configured to generate a third startup signal when triggered, and send the third startup signal to the startup control chip 110;

the startup control chip 180 is configured to send a second startup signal to the processing chip 120 after receiving the third startup signal;

the processing chip 120 is specifically configured to execute the boot program when powered on, and send a first boot normal signal and a boot identifier to the clearing chip 110 when the boot program is executed, or send a notification signal to the boot control chip 180 when the boot program is executed, and send the boot identifier to the clearing chip 110; alternatively, the first and second electrodes may be,

the power-on control chip 180 is further configured to send a second power-on normal signal to the clear chip 110 when receiving the notification signal;

the clearing chip 110 is further configured to determine that the electronic device is normally powered on when the first power-on normal signal and the power-on identifier are received or the second power-on normal signal and the power-on identifier are received, and update the stored power-on identifier as the received power-on identifier.

As an implementation manner of the embodiment of the present invention, the power-on control chip may be one of a Super IO chip, a BMC chip, and an EC chip.

As an implementation manner of the embodiment of the present invention, the clearing chip may be a single chip microcomputer.

The embodiment of the present invention further provides a clearing chip, as shown in fig. 8, including a processor 801, a communication interface 802, a memory 803, and a bus 804, where the processor 801, the communication interface 802, and the memory 803 complete mutual communication through the bus 804,

a memory 803 for storing a computer program;

the processor 801 is configured to implement the steps of the method for clearing CMOS information according to any of the embodiments described above when executing the program stored in the memory 803.

Therefore, in the scheme provided by the embodiment of the invention, the clearing chip can start timing when the processing chip executes the startup program, and control the RTC reset pin to be grounded to clear the CMOS information of the electronic device when the timing duration reaches the preset duration and the normal startup signal is not received. Therefore, the RTC reset pin can be controlled to be grounded when the starting is abnormal, so that the RTC register is reset, the CMOS information of the electronic equipment is automatically cleared, manual operation is not needed, and the convenience is greatly improved.

The bus mentioned in the above clearing chip is an internal bus of the clearing chip and can be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

The communication interface is used for communication between the cleaning chip and other devices or equipment.

The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.

The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

In another embodiment of the present invention, a computer-readable storage medium is further provided, in which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the method for clearing CMOS information according to any one of the above embodiments.

In the solution provided in the embodiment of the present invention, when the computer program is executed by the processor, the timing may be started when the processing chip executes the boot program, and when the timing duration reaches the preset duration and the normal boot signal is not received, the RTC reset pin is controlled to be grounded, so as to clear the CMOS information of the electronic device. Therefore, the RTC reset pin can be controlled to be grounded when the starting is abnormal, so that the RTC register is reset, the CMOS information of the electronic equipment is automatically cleared, manual operation is not needed, and the convenience is greatly improved.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the embodiments of the electronic device, the erase chip and the storage medium, since they are substantially similar to the embodiments of the method, the description is simple, and the relevant points can be referred to the partial description of the embodiments of the method.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.