阅读说明：本技术 一种降低mosfet衬底电阻的制作方法及其器件 (Manufacturing method and device for reducing MOSFET substrate resistance ) 是由 何昌 于 2021-08-18 设计创作，主要内容包括：本发明涉及一种降低MOSFET衬底电阻的制作方法及其器件,提供一半导体衬底,所述衬底上设有外延片,在所述外延片上进行沟槽刻蚀形成第一沟槽；在所述外延片及第一沟槽内表面生长一层栅极氧化层,并在栅极氧化层上表面沉积一绝缘介质层；通过淀积向所述第一沟槽内填充多晶硅后,再进行回刻；采用离子注入工艺注入离子后退火；在所述衬底背面进行沟槽刻蚀,形成第二沟槽；在所述衬底背面及第二沟槽内沉积背面金属层；通过在MOSFET增加了一步背面沟槽刻蚀工艺,形成第二沟槽,并在衬底背面及第二沟槽内沉积背面金属层,使得芯片衬底厚度保持不变的情况下,降低芯片衬底电阻,从而降低器件的导通电阻,工艺简单、成本低。(The invention relates to a manufacturing method for reducing the resistance of a MOSFET substrate and a device thereof, which comprises the steps of providing a semiconductor substrate, arranging an epitaxial wafer on the substrate, and etching a groove on the epitaxial wafer to form a first groove; growing a grid oxide layer on the epitaxial wafer and the inner surface of the first groove, and depositing an insulating medium layer on the upper surface of the grid oxide layer; filling polycrystalline silicon into the first groove through deposition, and then carrying out back etching; adopting an ion implantation process to implant ions and then annealing; etching a groove on the back of the substrate to form a second groove; depositing a back metal layer on the back of the substrate and in the second groove; by adding a back groove etching process to the MOSFET to form the second groove and depositing the back metal layer on the back of the substrate and in the second groove, the resistance of the substrate of the chip is reduced under the condition that the thickness of the substrate of the chip is not changed, so that the on-resistance of the device is reduced, the process is simple, and the cost is low.)

1. A manufacturing method for reducing the substrate resistance of a MOSFET is characterized by comprising the following steps:

s1, providing a semiconductor substrate, wherein an epitaxial wafer is arranged on the substrate, and a first groove is formed on the epitaxial wafer by groove etching;

s2, growing a gate oxide layer on the epitaxial wafer and the inner surface of the first groove;

s3, filling polycrystalline silicon into the first groove through deposition, and then carrying out back etching;

s4, implanting P-type ions into the epitaxial wafer substrate area by adopting an ion implantation process and then annealing;

s5, implanting N-type ions by adopting an ion implantation process and annealing to form N⁺A source region;

s6, depositing an insulating medium layer on the upper surface of the grid oxide layer;

s7, etching holes in the insulating medium layer to form contact holes to lead out the source electrode;

s8, depositing a front metal layer on the upper surfaces of the insulating medium layer and the contact hole;

s9, etching a groove on the back of the substrate to form a second groove;

and S10, depositing a back metal layer on the back of the substrate and in the second groove.

2. The method as claimed in claim 1, wherein in the step S9, the second trenches are formed by photolithography and etching, the second trenches are laterally spaced apart from each other, and the depth of the second trenches is smaller than the thickness of the semiconductor substrate.

3. The method as claimed in claim 1, wherein in the step S1, the first trenches are formed by photolithography and etching, and the first trenches are laterally spaced apart from each other.

4. The method as claimed in claim 1, wherein in step S2, the gate oxide layer is made of silicon oxide.

5. The method as claimed in claim 1, wherein in step S2, the gate oxide layer is formed by a thermal oxidation process.

6. The method of claim 1, wherein in step S4, the P-type ions are boron ions; the annealing process is a furnace tube or rapid annealing process.

7. The method as claimed in claim 1, wherein in the step S5, the N-type ions are phosphorous ions; the annealing process is a furnace tube or rapid annealing process.

8. A device, characterized by: the MOSFET power device formed by the manufacturing method for reducing the substrate resistance of the MOSFET in any one of claims 1 to 7.

Technical Field

The invention relates to the technical field of semiconductor preparation, in particular to a manufacturing method for reducing the resistance of a MOSFET substrate and a device thereof.

Background

A Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) is a Field-Effect Transistor (Field-Effect Transistor) that can be widely used in analog circuits and digital circuits. MOSFET power devices are a new generation of power semiconductor devices that integrate microelectronics and power electronics technologies. The high-voltage direct current power supply has the characteristics of high input impedance, high switching speed, large output current, good thermal stability, wide safe working area and the like, and is widely applied to electronic equipment such as power supply protection, power switches, DC/DC converters, synchronous rectification and the like.

Although the MOSFET power device has the advantages of very large safe working area and capability of using a plurality of unit structures in parallel, the MOSFET power device also has the defect of low channel mobility, thereby causing large on-resistance and large energy loss. The on-resistance Ron is an important parameter influencing the maximum output power of the MOSFET power device, the reduction of the on-resistance is beneficial to reducing the turn-on loss of the MOSFET power device, and the on-resistance Ron mainly comprises a channel resistor (Rch), a drift region resistor (Repi) and a substrate resistor (Rsub). As the voltage withstanding (BVdss) level of the MOSFET power device is reduced, the substrate resistance accounts for more than 30% of the on-resistance of the MOSFET power device, and the substrate resistance accounts for 1%.

At present, for reducing the resistance of the MOSFET substrate, the main methods are to reduce the substrate resistivity and reduce the substrate thickness, wherein the adoption of the ultra-low substrate resistivity requires strict control on the substrate autodoping, and a complex epitaxial growth technology needs to be developed, which has a great influence on the yield control of chip production. The ultrathin chip technology is used for reducing the thickness of the chip, so that a complex subsequent process needs to be developed for the development trend that the size of the current wafer is larger and larger, and higher requirements are put forward on packaging equipment and technology of the chip due to the fact that the chip is very thin.

Therefore, for low voltage MOSFET products, how to reduce the substrate resistance is important to reduce the on-resistance of the device.

Disclosure of Invention

The invention aims to solve the technical problem of providing a manufacturing method for reducing the substrate resistance of the MOSFET, so that the substrate resistance of a chip is reduced under the condition that the thickness of the substrate of the chip is not changed, the on-resistance of a device is reduced, the process is simple, and the cost is low.

In order to solve the technical problems, the invention adopts the technical scheme that: the manufacturing method for reducing the substrate resistance of the MOSFET is provided, and comprises the following steps:

s1, providing a semiconductor substrate, wherein an epitaxial wafer is arranged on the substrate, and a first groove is formed on the epitaxial wafer by groove etching;

s2, growing a gate oxide layer on the epitaxial wafer and the inner surface of the first groove;

s3, filling polycrystalline silicon into the first groove through deposition, and then carrying out back etching;

s4, implanting P-type ions into the epitaxial wafer substrate area by adopting an ion implantation process and then annealing;

s5, implanting N-type ions by adopting an ion implantation process and annealing to form N⁺A source region;

s6, depositing an insulating medium layer on the upper surface of the grid oxide layer;

s7, etching holes in the insulating medium layer to form contact holes to lead out the source electrode;

s8, depositing a front metal layer on the upper surfaces of the insulating medium layer and the contact hole;

s9, etching a groove on the back of the substrate to form a second groove;

and S10, depositing a back metal layer on the back of the substrate and in the second groove.

Further, in the step S9, a photolithography etching process is used to form the second trenches, the second trenches are laterally spaced apart, and the depth of the second trenches is smaller than the thickness of the substrate.

Further, in the step S1, a photolithography etching process is used to form the first trenches, and the first trenches are laterally spaced apart from each other.

Further, in the step S2, the gate oxide layer is made of silicon oxide.

Further, in the step S2, a thermal oxidation process is used to form the gate oxide layer.

Further, in the step S4, the P-type ions are boron ions; the annealing process is a furnace tube or rapid annealing process.

Further, in the step S5, the N-type ions are phosphorus ions; the annealing process is a furnace tube or rapid annealing process.

The invention also provides a device which comprises the MOSFET power device formed by the manufacturing method for reducing the substrate resistance of the MOSFET.

The invention has the beneficial effects that: according to the invention, a back groove etching process is added to the MOSFET to form the second groove, and the back metal layer is deposited on the back of the substrate and in the second groove, so that the resistance of the substrate of the chip is reduced under the condition that the thickness of the substrate of the chip is not changed, and the on-resistance of the device is reduced. The invention is suitable for MOSFET and its derivative devices made based on various semiconductor materials, and is also suitable for P type or N type, and for the above different types of devices, only because the structures and names of the devices are different, the manufacturing method disclosed by the invention reduces the substrate resistance of the chip on the premise of not changing the area of the MOSFET power device, thereby reducing the on-resistance of the device, and having simple process and low cost.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic diagram of a manufacturing method step S1 for reducing the substrate resistance of a MOSFET;

FIG. 2 is a schematic diagram of a manufacturing method step S2 for reducing the substrate resistance of a MOSFET;

FIG. 3 is a schematic diagram of a manufacturing method step S3 for reducing the substrate resistance of a MOSFET;

FIG. 4 is a schematic diagram of a manufacturing method step S4 for reducing the substrate resistance of a MOSFET;

FIG. 5 is a schematic diagram of a manufacturing method step S5 for reducing the substrate resistance of a MOSFET;

FIG. 6 is a schematic diagram of a manufacturing method step S6 for reducing the substrate resistance of a MOSFET;

FIG. 7 is a diagram of a manufacturing method step S7 for reducing the substrate resistance of a MOSFET;

FIG. 8 is a diagram of a manufacturing method step S8 for reducing the substrate resistance of a MOSFET;

FIG. 9 is a schematic diagram of a manufacturing method step S9 for reducing the substrate resistance of a MOSFET;

FIG. 10 is a diagram of a manufacturing method step S10 for reducing the substrate resistance of a MOSFET;

FIG. 11 is a process flow diagram of a method of making a MOSFET with reduced substrate resistance.

Description of reference numerals:

10. a substrate; 11. A second trench; 12. A back metal layer;

20. an epitaxial wafer; 201. A first trench; 21. A gate oxide layer;

22. polycrystalline silicon; 23. A base region; 24. n is a radical of⁺A source region;

25. an insulating dielectric layer; 26. A front side metal layer.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

As shown in fig. 1-11, an embodiment of the present invention provides a manufacturing method for reducing the resistance of a MOSFET substrate, including the following steps:

as shown in fig. 1, in this embodiment, S1, a semiconductor substrate 10 is provided, an epitaxial wafer 20 is disposed on the substrate 10, and a trench etching is performed on the epitaxial wafer 20 to form a first trench 201. The substrate 10 may be made of silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials, and the substrate 10 may be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate 10 may be a material suitable for process requirements or easy integration. The substrate 10 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. First, a trench etching is performed on the epitaxial wafer 20 to form a first trench 201.

As shown in fig. 2, in this embodiment, a gate oxide layer 21 is grown on the epitaxial wafer 20 and the inner surface of the first trench S2. And depositing a hard masking layer, then performing deep trench etching in the first trench, and depositing and forming a gate oxide layer, wherein the thickness of the gate oxide layer is reduced by the same proportion as the length of the channel in order to effectively inhibit the short channel effect and keep a good subthreshold slope.

As shown in fig. 3, in this embodiment, S3, filling the polysilicon 22 into the first trench by deposition, and then performing etching back; and filling the polysilicon and etching back to form bottom grid polysilicon of the hard masking layer. The threshold voltage (threshold voltage) of a MOSFET is mainly determined by the difference between the work functions of the gate and channel materials, and since polysilicon is essentially semiconductor, its work function can be changed by doping with impurities of different polarity. More importantly, since the energy gap (bandgap) between polysilicon and silicon of the substrate as the channel is the same, the requirement can be met by directly adjusting the work function of polysilicon when lowering the threshold voltage of PMOS or NMOS.

As shown in fig. 4, in this embodiment, S4, P-type ions are implanted into the epitaxial wafer base region 23 by an ion implantation process and then annealed. P-type ions are doped into the epitaxial wafer substrate region 23 at a lower temperature, and the concentration distribution and implantation depth of the doped P-type or N-type ions are precisely controlled. Can realize large-area uniform doping and has good repeatability.

In the present embodiment, as shown in fig. 5, S5, implanting N-type ions by ion implantation process and annealing to form N⁺A source region 24. The ion implantation technology is adopted, doping is carried out at a lower temperature, and the concentration distribution and the implantation depth of doped ions are accurately controlled. Can realize large-area uniform doping and has good repeatability.

As shown in fig. 6, in this embodiment, S6, an insulating dielectric layer 25 is deposited on the upper surface of the gate oxide layer; the material of the insulating dielectric layer 25 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or the like, and silicon oxide (SiO2) is preferable because silicon oxide (SiO2) has better bonding performance with a silicon semiconductor substrate.

As shown in fig. 7, in this embodiment, S7, performing hole etching on the insulating dielectric layer to form contact holes to lead out the source and the drain;

as shown in fig. 8, in the present embodiment, S8, depositing a front metal layer 26 on the insulating dielectric layer and the upper surface of the contact hole; the metal layer is subjected to a planarization process, and a thermal oxidation process by utilizing microwave thermal treatment is added to the metal layer, so that a metal oxide layer is formed on the exposed surface of the metal layer, the metal oxide layer can prevent oxygen in the air from entering the main metal layer of the metal electrode to enable the main metal layer to be continuously oxidized, and the metal electrode has the advantages of consistent thickness of the metal oxide layer, consistent contact resistance of the metal electrode and good consistency of devices; and the path of the upward diffusion of the main metal layer of the metal electrode can be prevented, and the corresponding advantage of enhancing the control capability of the grid electrode is realized.

As shown in fig. 9, in this embodiment, a trench etching is performed on the back surface of the substrate S9 to form a second trench 11. Forming a hard mask layer on the back of the substrate, then forming a layer of photoresist on the surface of the hard mask layer, forming a groove opening pattern on the surface of the photoresist layer, etching by using etching gas according to the groove opening pattern, wherein the thickness of the etched groove is smaller than that of the substrate, and then cleaning the residual photoresist by using liquid medicine.

As shown in fig. 10, in the present embodiment, a backside metal layer 12 is deposited on the backside of the substrate and in the second trench S10. The MOSFET substrate is formed by back side metal deposition.

Further, in the step S9, a photolithography etching process is used to form the second trenches, the second trenches are laterally spaced apart, and the depth of the second trenches is smaller than the thickness of the substrate.

Further, in the step S1, a photolithography etching process is used to form the first trenches, and the first trenches are laterally spaced apart from each other.

Further, in the step S2, the gate oxide layer is made of silicon oxide.

Further, in the step S2, a thermal oxidation or deposition process is used to form the gate oxide layer.

Further, in the step S4, the P-type ions are boron ions; the annealing process is a furnace tube or rapid annealing process. For an N-type power MOSFET device, the withstand voltage of a unit cell structure can be improved by injecting boron element ions; for a P-type power MOSFET device, the withstand voltage of a unit cell structure can be reduced by implanting boron element ions.

Further, in the step S5, the N-type ions are phosphorus ions; the annealing process is a furnace tube or rapid annealing process. For an N-type power MOSFET device, the withstand voltage of a unit cell structure can be reduced by injecting phosphorus element ions; for a P-type power MOSFET device, the withstand voltage of a unit cell structure can be improved by injecting phosphorus element ions. The on-resistance of the device can be reduced while the voltage resistance of the whole device is reduced by the injection method.

The invention also provides a device which comprises the MOSFET power device formed by the manufacturing method for reducing the substrate resistance of the MOSFET.

In summary, according to the manufacturing method for reducing the substrate resistance of the MOSFET and the device thereof provided by the present invention, a step of back trench etching process is added to the MOSFET to form the second trench, and the back metal layer is deposited on the back of the substrate and in the second trench, so that the substrate resistance of the chip is reduced under the condition that the thickness of the substrate of the chip is not changed, thereby reducing the on-resistance of the device. The invention is suitable for MOSFET and its derivative devices made based on various semiconductor materials, and is also suitable for P type or N type, and for the above different types of devices, only because the structures and names of the devices are different, the manufacturing method disclosed by the invention reduces the substrate resistance of the chip on the premise of not changing the area of the MOSFET power device, thereby reducing the on-resistance of the device, and having simple process and low cost.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.