阅读说明：本技术 一种多路cpu系统中时钟同步控制装置、系统及控制方法 (Clock synchronization control device, system and control method in multi-channel CPU system ) 是由 杨有桂 陈才 刘付东 范里政 于 2021-08-19 设计创作，主要内容包括：本发明公开一种多路CPU系统中时钟同步控制装置、系统及控制方法,该装置包括：分别与各路CPU系统连接的参考时钟源单元,以及分别与各路CPU系统连接的仲裁单元,参考时钟源单元用于为各CPU系统中的时间处理逻辑提供统一的参考时钟,仲裁单元用于统一控制调度各CPU系统中的时间处理逻辑进行时间的推进。本发明具有结构简单、同步效率以及精度高且复杂程度与实现成本低等优点。(The invention discloses a clock synchronization control device, system and control method in a multi-channel CPU system, the device includes: the system comprises a reference clock source unit and an arbitration unit, wherein the reference clock source unit is respectively connected with each path of CPU system, the arbitration unit is respectively connected with each path of CPU system, the reference clock source unit is used for providing a uniform reference clock for the time processing logic in each CPU system, and the arbitration unit is used for uniformly controlling and scheduling the time processing logic in each CPU system to advance time. The invention has the advantages of simple structure, high synchronization efficiency and precision, low complexity, low implementation cost and the like.)

1. A clock synchronization control device in a multi-CPU system is characterized by comprising: the device comprises a reference clock source unit (2) connected with each path of CPU system respectively and an arbitration unit (3) connected with each path of CPU system respectively, wherein the reference clock source unit (2) is used for providing a uniform reference clock for the time processing logic (1) in each CPU system, and the arbitration unit (3) is used for uniformly controlling and scheduling the time processing logic (1) in each CPU system to advance time.

2. The clock synchronization control apparatus in a multi-CPU system according to claim 1, wherein: and the reference clock source unit (2) is connected with each CPU system through a physical line.

3. The clock synchronization control apparatus in a multi-CPU system according to claim 1, wherein: the arbitration unit (3) is connected with GPIO interfaces in the CPU systems so as to communicate through the GPIO interfaces.

4. The clock synchronization control apparatus in a multi-CPU system according to claim 1, 2 or 3, wherein: the arbitration unit (3) comprises a control signal generation subunit (31) and a control subunit (32) which are sequentially connected, wherein the control signal generation subunit (31) is used for generating a starting time advancing control signal and respectively sending the starting time advancing control signal to the time processing logic (1) in each path of CPU system, and the control subunit (32) controls the time processing logic (1) in each path of CPU system to start time advancing according to the time advancing starting control signal.

5. The clock synchronization control device in a multi-CPU system according to claim 4, wherein: and each path of CPU system is also provided with a ready signal sending unit connected with the arbitration unit (3) and used for sending a time advance ready state signal to the arbitration unit (3).

6. The clock synchronization control apparatus in a multi-CPU system according to claim 5, wherein: specifically, when the time advance ready state signals sent by the CPU systems of the respective channels are all in an active state, the control subunit (32) configures the time advance start control signal to be in an active state to control and start the time processing logic (1) in the CPU systems of the respective channels to start time advance.

7. A multi-channel CPU system, each of which comprises time processing logic (1), and further comprising a clock synchronization control device according to any one of claims 1 to 6, wherein the clock synchronization control device controls the time processing logic (1) in each of the multiple CPU systems to perform clock synchronization.

8. A clock synchronization control method in a multi-CPU system is characterized by comprising the following steps:

generating a reference clock source, and uniformly providing the reference clock source to the time processing logic (1) in each path of CPU system;

and the time processing logic (1) in each CPU system is controlled and scheduled to advance time in a unified manner.

9. The method for controlling clock synchronization in a multi-CPU system according to claim 8, wherein said unified control scheduling said time processing logic (1) in each CPU system to advance time comprises:

generating a time advance starting control signal, and respectively sending the time advance starting control signal to the time processing logic (1) in each path of CPU system;

and controlling the time processing logic (1) in each CPU system to start time advancing according to the time advancing starting control signal.

10. The clock synchronization control method in the multi-CPU system according to claim 9, wherein the method comprises:

after configuring the initial value of time, each path of CPU system generates and sends a time advance ready state signal;

when the time advance ready state signals sent by the CPU systems are all in an effective state, the time advance starting control signals are configured to be in an effective state, and the time processing logic (1) in the CPU systems is controlled to start time advance.

Technical Field

The invention relates to the technical field of clock synchronization, in particular to a clock synchronization control device, a clock synchronization control system and a clock synchronization control method in a multi-channel CPU system.

Background

In a multi-channel CPU system, a time system is an important basic part in a multi-channel server and is mainly used for task scheduling and switching of program operation, a message timeout mechanism of a physical channel and the like. Each socket in the system needs to keep time consistent, that is, clock synchronization needs to be kept, otherwise system hardware initialization, software operation exception and the like can be caused.

A reference source of a clock system of a CPU is generally provided from the outside, a time processing logic inside the CPU generates a time of the CPU after acquiring the external reference source, and then dispatches the time to each CPU core, and based on the received time, each CPU core should be synchronous and have no time difference in an ideal state, so that a code can be migrated and run among the cores, and a time system of a single-path CPU is shown in fig. 1. After the single-path CPU system is expanded into a multi-path CPU system, the difference among a plurality of CPUs does not need to be concerned on the software level, and the multi-path CPU only provides hardware resources (kernel number, cache, internal memory, IO and the like) for software to use, so that stronger computing and IO expansion capabilities are realized. In the multi-CPU system, since each CPU chip has time processing logic, there are multiple time processing logics in the multi-CPU system, and in order to maintain the time consistency of multiple CPUs, it is necessary to require that the times issued by the multiple time processing logics be consistent, that is, to ensure that the time processing logics of the CPUs are synchronized. In order to ensure the performance of a multiplex system, it is generally required that time synchronization between CPUs is maintained with high accuracy.

For time/clock synchronization, most of the prior art adopts a network protocol message mode to perform time synchronization, that is, time acquisition or time calibration is performed between two devices through a network mode, as shown in fig. 2, time is acquired or time calibration is performed between a device a and a device B through a network mode to achieve time synchronization. In the above network protocol message mode, the time calibration process usually includes: the network time transmitted on the network is transmitted in a specific message form, the message is attached with the time information of the transmitting end, and the receiving end analyzes the time information after receiving the message and carries out equipment time calibration.

However, the conventional method of using network protocol packets to implement time synchronization has the following problems:

1. low efficiency and long time consumption.

Because time synchronization among devices needs to be completed by relying on network transmission, and network transmission, message analysis and the like all need certain time, the completion of the whole time synchronization usually needs more time, so that the synchronization efficiency is low, and after a chip is powered on, an effective clock system cannot be obtained as soon as possible, which affects the initialization time of the chip.

2. The synchronization effect is difficult to achieve with high accuracy.

Not only a certain time is needed for network transmission, but also a certain time delay exists in the generation and analysis of the message, so that the transmission time delay from the message to different devices is usually different, the finally obtained time of different devices is different, the high-precision synchronization is difficult to achieve actually, and the high-precision requirement of a multi-channel CPU on a time system cannot be met.

3. The implementation operation is complex and costly.

Since time calibration needs to depend on transmission of a message, a time device including a message sending end, a message receiving end and a transmission medium must be constructed, which is not only complex to implement, but also increases implementation cost. Especially, when the method is applied to a multi-channel system, a large number of time devices need to be constructed between the multi-channel systems to transmit and receive messages, so that the implementation complexity and the cost are greatly increased.

Some practitioners consider placing the time synchronization method in the chip design to improve the efficiency and accuracy of time synchronization, but this will result in a significant increase in the complexity of chip design, and it is difficult to perform a test on the time synchronization logic subsequently.

Therefore, it is desirable to provide a clock synchronization control scheme applicable to a multi-channel system, so as to achieve both the efficiency and the precision of clock synchronization implementation and the implementation cost and complexity.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a clock synchronization control device, a clock synchronization control system and a clock synchronization control method in a multi-channel CPU system, wherein the clock synchronization control device, the clock synchronization control system and the clock synchronization control method are simple in structure, high in synchronization efficiency and precision, low in complexity and low in implementation cost.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

a clock synchronization control device in a multi-CPU system comprises: the system comprises a reference clock source unit and an arbitration unit, wherein the reference clock source unit is respectively connected with each CPU system, the arbitration unit is respectively connected with each CPU system, the reference clock source unit is used for providing a uniform reference clock for the time processing logic in each CPU system, and the arbitration unit is used for uniformly controlling and scheduling the time processing logic in each CPU system to advance time.

Furthermore, the reference clock source unit is connected with each CPU system through a physical line.

Further, the arbitration unit is connected to a General-purpose input/output (GPIO) interface in each CPU system, so as to communicate via the GPIO interface.

Further, the arbitration unit includes a control signal generation subunit and a control subunit, which are connected in sequence, where the control signal generation subunit is configured to generate a start time advance control signal and send the start time advance control signal to the time processing logic in each CPU system, and the control subunit controls the time processing logic in each CPU system to start time advance according to the time advance start control signal.

Furthermore, each path of CPU system is also provided with a ready signal sending unit connected with the arbitration unit, and the ready signal sending unit is used for sending a time advance ready state signal to the arbitration unit.

Further, when the time advance ready state signals sent by the CPU systems of the respective channels are all in an active state, the control subunit configures the time advance start control signal to be in an active state to control and start the time processing logic in the CPU systems of the respective channels to start time advance.

A multi-path CPU system comprises time processing logic and the clock synchronization control device, wherein the clock synchronization control device controls the time processing logic in each path of CPU system to carry out clock synchronization.

A clock synchronization control method in a multi-CPU system comprises the following steps:

generating a reference clock source, and uniformly providing the reference clock source to the time processing logic in each path of CPU system;

and uniformly controlling and scheduling the time processing logic in each CPU system to advance time.

Further, the unified control and scheduling of the time processing logic in each CPU system to advance time includes:

generating time advance starting control signals, and respectively sending the time advance starting control signals to the time processing logic in each path of CPU system;

and controlling the time processing logic in each CPU system to start time advancing according to the time advancing starting control signal.

Further, the method comprises:

after configuring the initial value of time, each path of CPU system generates and sends a time advance ready state signal;

when the time advance ready state signals sent by the CPU systems of all paths are all in an effective state, the configuration enables the time advance starting control signal to be in an effective state, and the time processing logic in the CPU systems of all paths is controlled to start time advance.

Compared with the prior art, the invention has the advantages that:

1. the invention provides a uniform reference clock by configuring a reference clock source unit for the time system of the multi-channel CPU system, and configures an arbitration unit for the multi-channel CPU system, and the arbitration unit uniformly schedules and controls whether each time processing logic carries out time propulsion, thereby effectively ensuring the synchronization precision and the synchronization efficiency of the time processing logic of each channel of CPU system, realizing the rapid and accurate clock synchronization of the multi-channel CPU system, having no need of depending on complex network protocol messages in the whole synchronization process, and greatly reducing the complexity and the realization cost of the synchronization realization.

2. The invention can realize clock synchronization by combining the internal mechanism of the multi-path CPU system, so that the clock synchronization mechanism is matched with the structure of the multi-path system, and the multi-path CPU system can be ensured to realize accurate clock synchronization.

Drawings

FIG. 1 is a schematic diagram of a time system architecture of a single-channel CPU.

Fig. 2 is a schematic diagram illustrating a principle of time synchronization in a network protocol messaging manner in the prior art.

Fig. 3 is a schematic structural diagram of the clock synchronization control device in the multi-CPU system of the present embodiment.

Fig. 4 is a schematic diagram of the structural principle of implementing clock synchronization in this embodiment.

Fig. 5 is a schematic flow chart of implementing clock synchronization in a specific application embodiment (two-way system).

Illustration of the drawings: 1. time processing logic; 2. a reference clock source unit; 3. an arbitration unit; 31. a control signal generating subunit; 32. a control subunit.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

As shown in fig. 3 and 4, the clock synchronization control device in the multi-CPU system of the present embodiment includes: the system comprises a reference clock source unit 2 connected with each path of CPU system respectively and an arbitration unit 3 connected with each path of CPU system respectively, wherein the reference clock source unit 2 is used for providing a uniform reference clock for the time processing logic 1 in each CPU system, and the arbitration unit 3 is used for uniformly controlling and scheduling the time processing logic 1 in each CPU system to carry out time propulsion. Each CPU system includes a time processing logic 1, and the time processing logic 1 is mainly used for time setting, time advancing, time distribution, and the like.

The different clock sources have frequency offset and phase difference, and the time processing logic of the CPU is sensitive to the frequency offset and the phase difference of the clock, so that the time possibly generated by the different reference clock sources is different. In view of the above problem, the present embodiment configures a reference clock source unit 2 for a time system of a multi-channel CPU system, and the reference clock source unit 2 provides a uniform time reference source for each time processing logic 1, so that each time processing logic 1 keeps clock homology.

The time processing logic 1 of the multi-path CPU system can acquire the same clock source based on the reference clock source unit 2, and can ensure the identity of the clock source of each path of CPU, but the time advance is processed by the time processing logic inside each CPU, and the time points of the time advance and the time stop of each CPU are different, so that even if the same clock source is used, the synchronization of each path of CPU system during the time advance cannot be ensured. In view of the above problems, in this embodiment, on the basis of configuring one reference clock source unit 2 for a time system of a multi-channel CPU system, one arbitration unit 3 is configured for the time processing logic 1 of the multi-channel CPU system, and the arbitration unit 3 uniformly schedules and controls whether each time processing logic 1 performs time advance, so that clock synchronization is realized by combining the reference clock source unit 2 and the arbitration unit 3, which can effectively ensure synchronization accuracy and synchronization efficiency of the time processing logic 1 of each channel of CPU system, and realize fast and accurate clock synchronization of the multi-channel CPU system.

In a specific application embodiment, the frequency of the reference clock provided by the reference clock source unit 2 may be specifically configured according to the practical design constraint of the CPU.

In this embodiment, the reference clock source unit 2 is specifically connected to each CPU system through a physical line, a reference clock signal output by the reference clock source unit 2 is transmitted to the time processing logic 1 of each CPU system through the physical line, and the reference clock signal is transmitted in a physical medium. The reference clock source unit 2 is connected with each CPU system by a physical line, on one hand, because the signal is directly transmitted by the physical line, the transmission efficiency is high, the time delay is small, and the network transmission time delay of the traditional network protocol message mode can be greatly reduced; on the other hand, the anti-interference performance of the signal transmitted through the physical line is strong, and the reference clock is not easily influenced by the interference signal, so that the precision and the reliability of clock synchronization can be further improved.

Since different physical medium lengths may generate different delays, in a specific application embodiment, when a physical line between the reference clock source unit 2 and each CPU system is configured, the maximum tolerable transmission length of the physical medium corresponding to each CPU system may be specifically determined according to the time precision requirement of each CPU.

In this embodiment, the arbitration unit 3 is connected to a GPIO interface in each CPU system to perform communication via the GPIO interface. Compared with the traditional communication interface, the GPIO interface has high transmission efficiency and simple message transmission realization, and can further improve the clock synchronization efficiency and precision of a multi-channel CPU system by combining the GPIO interface connection mode.

It is understood that the arbitration unit 3 and each CPU system may also use other low-speed interfaces such as I2C, UART, etc. according to actual requirements.

As shown in fig. 4, the arbitration unit 3 in this embodiment includes a control signal generation subunit 31 and a control subunit 32 connected in sequence, where the control signal generation subunit 31 is configured to generate a START time advance control signal TIMER _ START, and send the START time advance control signal TIMER _ START to the time processing logic 1 in each CPU system, respectively, and the control subunit 32 controls the time processing logic 1 in each CPU system to START time advance according to the START time advance control signal TIMER _ START, that is, controls the START time of time advance. Since the arbitration unit cannot sense the time advance state of the CPU system, that is, when the time advance starts, the control signal generation subunit 31 is disposed in the arbitration unit 3, and the control signal generation subunit 31 generates the control signal to control the start of the time advance, so that it can be ensured that the time processing logic 1 of each CPU system starts to perform the time advance at the same time point, thereby avoiding the time points of the time advance of the time processing logic 1 of different CPU systems from being different, and ensuring high precision of the clock synchronization of multiple CPU systems.

In this embodiment, each of the CPU systems is further provided with a READY signal sending unit connected to the arbitration unit 3, and configured to send a time advance READY state signal TIMER _ READY to the arbitration unit 3. In this embodiment, the READY signal sending unit of each CPU system sends a time advance READY state signal TIMER _ READY to the arbitration unit 3 after the time advance is READY to notify the arbitration unit 3 that the CPU system can be READY to advance time, thereby avoiding starting time advance when the CPU system is not in an accurate READY state.

In a specific application embodiment, the time advance READY status signal TIMER _ READY is generated after setting configuration information such as a time initial value, and after the time initial value is set by the CPU, it is determined that the CPU system has a time advance condition, that is, the time advance is accurate and READY, and the time advance READY status signal TIMER _ READY is set to be valid and sent to the arbitration unit 3.

To achieve the time setting, further CPU systems may be configured with programmable interfaces for setting time initial values, start and stop points of time advance, etc.

In this embodiment, the control subunit 32 is specifically configured to, when the time advance READY state signals TIMER _ READY sent by the CPU systems of each channel are all in a valid state, that is, all the CPU systems are accurately READY, configure that the time advance START control signal is a TIMER _ START valid state, START time advance by controlling and starting the time processing logic 1 in the CPU systems of each channel, and if there is an invalid state of the time advance READY state signal TIMER _ READ sent by the CPU system, set the time advance START control signal as TIMER _ START invalid state, so as not to control time advance. The control subunit 32 determines whether the TIMER _ START signal is valid by identifying whether the time advance READY state signals TIMER _ READY of the CPUs of the respective paths are valid, so that it can be ensured that the time advance is performed at the same time point when the CPU systems of the respective paths are in the time advance READY state, thereby ensuring the accuracy and reliability of the clock synchronization.

In a specific application embodiment, as shown in table 1, if the TIMER _ READY signals sent by the CPU systems are all valid, the TIMER _ START signal is set to be valid, which indicates that the entire system can START execution time synchronization, and if the TIMER _ READY signals are not all valid, it is determined that the TIMER _ START is invalid, which indicates that the entire system cannot START execution time synchronization.

Table 1: and defining a CPU interface.

It is understood that the arbitration unit 3 can also generate other types of control signals according to actual requirements, or comprehensively use multiple types of control signals to jointly control the time advance of the CPU system, so as to further improve the control performance of clock synchronization.

The clock synchronization control device of the present embodiment will be further described below by taking the example of clock synchronization control performed on a two-way CPU system (CPU0, CPU 1).

As shown in fig. 5, the arbitration unit 3 in this embodiment specifically handles signal logic of TIMER _ READY and TIMER _ START, the two signals are powered on by default to a low level (inactive state), and the logic is configured as a part of a power-on initialization process of the system. For the processing logic of both the TIMER _ READY and TIMER _ START signals, as shown in table 2, when the TIMER _ READY of the CPU0 and the CPU1 are both high level (active state), the TIMER _ START signal is high level (active state), and if the TIMER _ READY of the CPU0 and the CPU1 are both low level (inactive state), the TIMER _ START signal is low level (inactive state); if the TIMER _ READY signal is low in the CPU0, the CPU1, the TIMER _ START signal remains unchanged, i.e., the current time advance state is maintained.

Table 2: arbitration unit time advance control logic.

CPU0_TIMER_READY	CPU1_TIMER_READY	TIMER_START
			Height of	Height of	Height of
Is low in	Is low in	Is low in
			Height of	Is low in	The level remains unchanged
Is low in	Height of	The level remains unchanged

The present embodiment further provides multiple CPU systems, each of which includes a time processing logic 1, and further includes the clock synchronization control device, where the clock synchronization control device controls the time processing logic 1 in each of the multiple CPU systems to perform clock synchronization.

The embodiment also provides a clock synchronization control method in the multi-path CPU system, including:

s1, generating a reference clock source, and uniformly providing the reference clock source to time processing logic 1 in each path of CPU system;

and S2, uniformly controlling and scheduling the time processing logic 1 in each CPU system to advance time.

In this embodiment, the step S2 specifically includes:

generating a starting time advance control signal TIMER _ START, and respectively sending the starting time advance control signal TIMER _ START to time processing logic 1 in each path of CPU system;

and controlling the starting time of time advancing by the time processing logic 1 in each CPU system according to the starting time advancing control signal TIMER _ START.

In this embodiment, the method includes:

after configuring the initial time value, each path of CPU system generates a time advance READY state signal TIMER _ READY and sends the signal TIMER _ READY;

when the time advance READY state signals TIMER _ READY sent by the CPU systems of all the paths are in an effective state, the time advance starting control signal TIMER _ START is configured to be in an effective state, and the time processing logic 1 in the CPU systems of all the paths is controlled to START time advance.

The clock synchronization control method in the multi-channel CPU system of this embodiment is a method for implementing the clock synchronization control device in the multi-channel CPU system, and has an effect corresponding to the clock synchronization control device in the multi-channel CPU system, which is not described in detail herein.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.