阅读说明：本技术 单次可程序化位元的形成方法 (Method for forming one-time programmable bit ) 是由 柯昱州 于 2020-05-27 设计创作，主要内容包括：本发明公开一种单次可程序化位元的形成方法,首先,提供一薄膜存储器装置,其包含至少一个存储器元件与一晶体管,且存储器元件电性串联晶体管。接着,在一交流电流的复数周期中,施加交流电流于存储器元件与晶体管,并限制提供给存储器元件的功率,且导通晶体管,以改变存储器元件的电阻,直到存储器元件的电阻发生不可逆改变为止。本发明利用双极性电流对薄膜存储器装置施压,并限制提供给存储器装置的功率,以达到较低崩溃电压,同时缩小崩溃后的电阻分布范围。(The invention discloses a method for forming a one-time programmable bit, which comprises the following steps of firstly, providing a thin film memory device which comprises at least one memory element and a transistor, wherein the memory element is electrically connected with the transistor in series. Then, in a plurality of cycles of an alternating current, the alternating current is applied to the memory element and the transistor, the power supplied to the memory element is limited, and the transistor is turned on to change the resistance of the memory element until the resistance of the memory element is irreversibly changed. The invention utilizes bipolar current to pressurize the thin film memory device and limit the power supplied to the memory device to achieve lower breakdown voltage and simultaneously reduce the distribution range of the resistance after breakdown.)

1. A method for forming a one-time programmable bit, comprising the steps of:

providing a thin film memory device comprising at least one memory element and a transistor, wherein the at least one memory element is electrically connected in series with the transistor; and

applying an alternating current to at least one of the memory elements and the transistor during a plurality of cycles of the alternating current, limiting power supplied to at least one of the memory elements, and turning on the transistor to change a resistance of at least one of the memory elements until the resistance of at least one of the memory elements irreversibly changes.

2. The method of claim 1, wherein the transistor is a MOSFET.

3. The method of claim 1, wherein at least one of the memory elements is a Magnetoresistive Random Access Memory (MRAM) device having a Magnetic Tunnel Junction (MTJ) or a one-time programmable resistance (OTP) device.

4. The method of claim 3, wherein the one-time programmable resistive element is a phase change memory, a conductive bridge random access memory, a ferroelectric tunnel junction memory, or a resistive random access memory.

5. The method of claim 1, wherein an absolute value of the alternating current divided by an absolute value of a write current received by at least one of the memory elements during a write operation is greater than or equal to 1.25.

6. The method of claim 1, wherein each of the periods is 0.2-200 ns.

7. The method of claim 1, wherein the step of limiting the power is performed by limiting the AC current supplied to at least one of the memory elements.

8. The method of claim 1, wherein the alternating current comprises a positive current and a negative current.

9. The method of claim 1, wherein said step of applying said alternating current to at least one of said memory element and said transistor and limiting said power provided to at least one of said memory element and turning on said transistor comprises applying said alternating current to at least one of said memory element and said transistor and limiting said power provided to at least one of said memory element and turning on said transistor.

10. The method of claim 1, wherein the step of applying the AC current to the at least one memory element and the transistor and limiting the power provided to the at least one memory element comprises turning on the transistor, applying the AC current to the at least one memory element and the transistor, and limiting the power provided to the at least one memory element.

11. The method of claim 1, wherein the upper limit of the power is gradually decreased over time.

Technical Field

The present invention relates to the field of memories, and more particularly, to a bit forming method, and more particularly, to a method for forming a one-time programmable bit.

Background

Thin film Memory devices, such as Magnetic Random Access Memories (MRAMs), typically include a tunneling barrier capable of representing two resistance states. The permanent third state resulting from the barrier breakdown has a lower resistance than the two resistance states before the barrier breakdown. This third state is used for One Time Programmable (OTP), but the resistance distribution of this state is wide, making it prone to high read error rates and circuit complexity. In addition, for power consumption considerations, it is desirable to operate with a lower barrier breakdown voltage and select a smaller transistor size.

Disclosure of Invention

The present invention provides a method for forming one-time programmable bits to solve the above-mentioned problems.

It is therefore a primary objective of the claimed invention to provide a method for forming a one-time programmable bit by applying a voltage to a thin film memory device using bipolar current and limiting the power supplied to the memory device to achieve a lower breakdown voltage of the memory device and to reduce the resistance distribution after the memory device is broken down.

To achieve the above objective, the present invention provides a method for forming a one-time programmable bit, which comprises providing a thin film memory device comprising at least one memory element and a transistor, wherein the memory element is electrically connected in series with the transistor. Then, in a plurality of cycles of an alternating current, the alternating current is applied to the memory element and the transistor, the power supplied to the memory element is limited, and the transistor is turned on to change the resistance of the memory element until the resistance of the memory element is irreversibly changed.

In an embodiment of the invention, the transistor is a metal oxide semiconductor field effect transistor.

In an embodiment of the invention, the Memory device is a Magnetoresistive Random Access Memory (MRAM) having Magnetic Tunnel Junctions (MTJs) or other one-time programmable Resistive devices (OTP components), such as Phase Change Memory (PCM), conductive-bridge Random Access Memory (CBRAM), ferroelectric Random Access Memory (FeRAM), Ferroelectric Tunnel Junction (FTJ) Memory or Resistive Random Access Memory (RRAM).

In an embodiment of the invention, the absolute value of the alternating current is greater than or equal to 1.25 times the absolute value of the write current received by the memory element during the write operation.

In one embodiment of the present invention, each period is 0.2-200 nanoseconds.

In one embodiment of the invention, the step of limiting power limits the alternating current supplied to the memory element.

In an embodiment of the present invention, the alternating current includes a positive current and a negative current.

In an embodiment of the invention, the step of applying the ac current to the memory device and the transistor and limiting the power supplied to the memory device, and the step of turning on the transistor includes applying the ac current to the memory device and the transistor, and limiting the power supplied to the memory device and then turning on the transistor, or may also include turning on the transistor first and then applying the ac current to the memory device and the transistor and limiting the power supplied to the memory device.

In one embodiment of the invention, the upper limit of the power limited to the memory element is tapered over time.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a timing diagram illustrating voltage drops across a memory device during writing data to the memory device according to the present invention;

FIG. 2 is a block diagram of a thin film memory device, a controller and a current limiting circuit according to the present invention;

FIG. 3 is a waveform diagram of the AC current and the absolute value of the voltage across the thin film memory device according to the present invention;

FIG. 4 is a breakdown voltage distribution diagram of the breakdown phenomenon of the alternating current compared with the unidirectional current according to the present invention;

FIG. 5 is a graph of resistance after breakdown with power limiting versus without power limiting according to the present invention.

Description of the symbols: 10. a thin film memory device; 12. a memory element; 14. a transistor; 16. a controller; 18. a power limiting circuit.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

When an element is referred to as being "on …," it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no other elements present between the two. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.

The description below of "one embodiment" or "an embodiment" refers to a particular element, structure, or feature associated with at least one embodiment. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Referring to FIG. 1, an embodiment of a method for forming a one-time programmable bit according to the present invention is described. First, the memory device used in the present invention is described, which can be a Magnetoresistive Random Access Memory (MRAM) or a Resistive Random Access Memory (RRAM) having a Magnetic Tunnel Junction (MTJ). As shown in fig. 1, the memory element has a tunneling barrier (tunneling barrier) capable of representing two resistance values Rap, Rp. When the memory element has a resistance Rap, a positive constant current is supplied to the memory element for about 1-100 ns, so that the resistance of the memory element decreases from Rap to Rp, and thus the absolute value of the voltage across the memory element decreases from Vap. When the memory element has a resistance Rp, a negative constant current is supplied to the memory element for about 1-100 ns, so that the resistance of the memory element is increased from Rp to Rap, and the absolute value of the voltage across the memory element is increased from Vp. The above-described positive and negative constant currents represent passing through the memory element in different directions, but the absolute values of the positive and negative constant currents are the same. The switching in fig. 1 is followed by a change in the resistance value of the memory element.

Please refer to fig. 2. In the method for forming one-time programmable bits of the present invention, first, a thin film memory device 10 is provided, which includes at least one memory element 12 and a transistor 14, wherein the memory element 12 is electrically connected in series with the transistor 14. The memory device 12 may be a Magnetoresistive Random Access Memory (MRAM) having a Magnetic Tunnel Junction (MTJ) or a one-time programmable resistance device (OTP resistive component), which may be a Phase Change Memory (PCM), a Conductive Bridge Random Access Memory (CBRAM), a ferroelectric random access memory (FeRAM), a Ferroelectric Tunnel Junction (FTJ) memory or a Resistive Random Access Memory (RRAM), but the invention is not limited thereto. The one-time programmable resistance element may be an antifuse (antifuse), which may be composed of one or more contacts or inter-layer contacts (via) with an insulator therebetween. The antifuse may also be coupled to the body of the cmos fet by the gate of the cmos fet, which has a gate oxide as an insulator, and the transistor 14 may be a mosfet, but the invention is not limited thereto. One end N1 of thin film memory device 10 is electrically connected to a controller 16, and the other end N2 is electrically connected to controller 16 through a power limiting circuit 18.

Please refer to fig. 2 and fig. 3 simultaneously. During the multiple cycles of an ac current, the controller 16 applies the ac current to the memory element 12 and the transistor 14 and limits the power supplied to the memory element 12 using the power limiting circuit 18, and the controller 16 turns on the transistor 14 to change the resistance of the memory element 12 until the resistance of the memory element 12 irreversibly changes. When the resistance of the memory element 12 changes irreversibly, it indicates that a breakdown phenomenon of the memory element 12 occurs.

For example, the absolute value of the alternating current divided by the absolute value of the write current received by the memory element 12 during the write operation is greater than or equal to 1.25, and each period T of the alternating current is 0.2-200 nanoseconds (ns), but the invention is not limited thereto. Specifically, the alternating current includes a positive current and a negative current, and the absolute value of the positive current is equal to the absolute value of the negative current, wherein the positive current and the negative current represent passing through the memory element 12 in different directions. In addition, in some embodiments of the present invention, the controller 16 may first apply an alternating current to the memory element 12 and the transistor 14, and then limit the power supplied to the memory element 12 by the power limiting circuit 18, and then turn on the transistor 14 by the controller 16. Alternatively, the controller 16 may pilot the transistor 14, apply an alternating current to the memory element 12 and the transistor 14, and limit the power supplied to the memory element 12 by the power limiting circuit 18.

When the memory element 12 exhibits a resistance Rap, the controller 16 provides a positive current to the memory element 12 and the transistor 14, so that the resistance of the memory element 12 decreases from Rap to Rp, and thus the absolute value of the voltage across the memory element 12 decreases from Vap. The controller 16 then provides a negative current to the memory element 12 and the transistor 14, so that the absolute value of the voltage across the memory element 12 is further decreased to Vp. After the drop, the resistance of the memory element 12 increases from Rp to Rap, so the cross voltage across the memory element 12 increases from Vp. When the controller 16 again provides a positive current to the memory element 12 and the transistor 14, the absolute value of the voltage across the memory element 12 first rises further to Vap. Then, since the resistance of the memory element 12 decreases from Rap to Rp, the cross voltage across the memory element 12 decreases from Vap. When an alternating current is applied to the thin film memory device 10, the memory element 12 can be rapidly broken down because the high voltage Vap is continuously generated.

Please refer to fig. 2 and fig. 4. In the present invention, the alternating current is applied to the thin film memory device 10, and the breakdown voltage corresponding to the alternating current is lower at the same breakdown rate because a high voltage can continuously occur compared to the case of using a unidirectional current, wherein the breakdown rate refers to the breakdown rate, which means that if four memory elements 12 are simultaneously applied with the same alternating current, three of the memory elements 12 are broken, which means that the breakdown rate is 0.75.

If there are a plurality of memory elements 12 in the thin film memory device 10, the power limiting circuit 18 is not provided, so that when an alternating current is applied, metal atoms can easily enter into the junction (junction) of the memory elements 12, and the resistance of the memory elements 12 after breakdown is widely distributed, as shown by the dotted line in fig. 5. If the breakdown resistance is widely distributed, it will cause reading difficulty and it is difficult to operate the memory device 12, so the power limiting circuit 18 is designed to limit the power supplied to the memory device 12, for example, the power limiting circuit 18 can be implemented as a current limiting circuit to limit the current supplied to the memory device 12, thereby reducing the breakdown resistance distribution, as shown by the solid line in fig. 5. In some embodiments of the present invention, power limiting circuit 18 limits the upper limit of power supplied to memory element 12 to decrease over time to narrow the resistance distribution after breakdown. For example, power limiting circuit 18 of the previous cycle limits the power supplied to memory element 12 more than power limiting circuit 18 of the next cycle limits the power supplied to memory element 12.

In summary, the present invention utilizes bipolar ac current to apply voltage to the thin film memory device and limit the power supplied to the memory device to achieve lower breakdown voltage and reduce the distribution range of the resistance after breakdown.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.