阅读说明：本技术 一种改善nand闪存有源区光刻显影缺陷的方法 (Method for improving photoetching development defects of NAND flash memory active area ) 是由 刘天舒 巨晓华 王奇伟 于 2021-08-30 设计创作，主要内容包括：本发明提供了一种改善NAND闪存有源区光刻显影缺陷的方法,应用于半导体领域,所述方法通过在核心有源区的高深宽比的侧墙间隙中填充有机介电层,避免光刻胶与侧墙直接接触,从而在有机介电层上涂覆光刻胶,并进行曝光显影以形成图案化的光刻胶层时,避免对光刻胶显影后产生遗留在侧墙间隙中的显影残留物,进而可避免光刻胶显影缺陷的产生。进一步地,使有机介电层的顶面与所述侧墙的顶面齐平,进而在后续可以以等高的侧墙和有机介电层为掩膜继续向下刻蚀,由此保证待图形化层中形成的图形的质量。(The invention provides a method for improving photoetching development defects of an active area of a NAND flash memory, which is applied to the field of semiconductors. Furthermore, the top surface of the organic dielectric layer is flush with the top surface of the side wall, so that the subsequent downward etching can be continued by using the side wall and the organic dielectric layer with the same height as the mask, and the quality of the pattern formed in the layer to be patterned is ensured.)

1. A method for improving photoetching development defects of an active area of a NAND flash memory is characterized by comprising the following steps:

s1, providing a semiconductor substrate with a core active region and a peripheral region, sequentially forming a layer to be patterned and an amorphous silicon layer on the semiconductor substrate, and forming a plurality of side walls arranged at intervals on the amorphous silicon layer of the core active region;

s2, covering an organic dielectric layer on the amorphous silicon layers of the core active region and the peripheral region, wherein the organic dielectric layer is also filled in the gap of the side wall;

s3, coating photoresist on the organic dielectric layer, and exposing and developing to form a patterned photoresist layer and define the photoresist pattern required in the peripheral region;

s4, etching the organic dielectric layer to the surface of the amorphous silicon layer by taking the patterned photoresist layer as a mask so as to remove the organic dielectric layer of the core active region and reserve the required organic dielectric layer in the peripheral region;

and S5, removing the patterned photoresist layer, and etching the amorphous silicon layer and the layer to be patterned by taking the side wall and the rest of the organic dielectric layer as masks to form a required pattern in the layer to be patterned.

2. The method for improving lithography development defects of the active area of the NAND flash memory as claimed in claim 1, wherein the layer to be patterned formed in step S1 includes a floating gate layer, a gate oxide layer and a hard mask layer stacked in sequence from bottom to top, the layer to be patterned is used for forming the memory cell of the NAND flash memory; in step S5, etching is stopped on the surface of the gate oxide layer.

3. The method of claim 1, wherein in step S1, the step of forming a plurality of spacers on the amorphous silicon layer of the core active region comprises:

s1.1, forming a plurality of core structures arranged at intervals on the amorphous silicon layer of the core active region;

s1.2, forming side walls on the side walls of the core structures;

s1.3, removing each core structure.

4. The method for improving lithography development defects of the active area of the NAND flash memory as claimed in claim 3, wherein the core structure formed in the step S1.1 comprises a first oxide layer and a second oxide layer stacked in sequence from bottom to top.

5. The method for improving lithography development defects of the active area of the NAND flash memory as claimed in claim 3, wherein the material of the deposited sidewall spacer in step S1.2 comprises silicon nitride.

6. The method for improving photolithographic development defects of an active area of a NAND flash memory as claimed in claim 4, wherein the densification of the first oxide layer is greater than the densification of the second oxide layer.

7. The method for improving lithography development defects of active areas of NAND flash memories as claimed in claim 6, wherein in said step S1.3, the step of removing each of said core structures comprises:

s1.3.1, removing the first oxide layer of each core structure by a first etching process;

s1.3.2, removing the second oxide layer by a second etching process.

8. The method for improving the lithography development defect of the active area of the NAND flash memory as claimed in claim 7, wherein the first etching process is a dry etching process, and the second etching process is a wet etching process.

9. The method of claim 1, wherein in step S2, the top surface of the organic dielectric layer is flush with the top surfaces of the sidewalls.

10. The method of improving lithography development defects in an active area of a NAND flash memory as claimed in claim 3, wherein the line width of said core structure is equal to the line width of the gap between adjacent sidewalls of adjacent said core structures.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for improving photoetching development defects of an active area of a NAND flash memory.

Background

A NAND flash (flash memory) memory array is generally composed of a plurality of blocks, each block including a plurality of word lines and a select transistor, and has advantages of large capacity, long life, non-volatility, low cost, and the like, and thus is widely used in automobiles, electronics, and consumer products. To meet the increasing demand for memory capacity, the word lines are continuously scaled down in size as technology advances. And therefore the process requirements are also increasing.

In the process of developing a two-dimensional plane NAND flash product with 19 nm and below technical nodes, the depth-to-width ratio of the side wall of the storage array for manufacturing the core active area is large, when the peripheral area is exposed and developed by photoresist, the position of the core active area covered by the photoresist is easy to develop insufficiently, so that residues exist between the side walls, and the residues are difficult to remove even through a subsequent cleaning process due to the large depth-to-width ratio of the side wall, so that the residues become a defect source of the subsequent process.

Disclosure of Invention

The invention aims to provide a method for improving the photoetching development defects of an active area of a NAND flash memory, which can avoid the problem that development residues are left in gaps among side walls of a core active area due to the fact that the depth-to-width ratio of the gaps among the side walls is large, and further can solve the problem of device defects caused by the development residues of photoresist in the core active area.

In order to solve the above technical problem, the present invention provides a method for improving the lithography development defect of the active area of a NAND flash memory, comprising:

s1, providing a semiconductor substrate with a core active region and a peripheral region, sequentially forming a layer to be patterned and an amorphous silicon layer on the semiconductor substrate, and forming a plurality of side walls arranged at intervals on the amorphous silicon layer of the core active region;

s2, covering an organic dielectric layer on the amorphous silicon layers of the core active region and the peripheral region, wherein the organic dielectric layer is also filled in the gap of the side wall;

s3, coating photoresist on the organic dielectric layer, and exposing and developing to form a patterned photoresist layer and define the photoresist pattern required in the peripheral region;

s4, etching the organic dielectric layer to the surface of the amorphous silicon layer by taking the patterned photoresist layer as a mask so as to remove the organic dielectric layer of the core active region and reserve the required organic dielectric layer in the peripheral region;

and S5, removing the patterned photoresist layer, and etching the amorphous silicon layer and the layer to be patterned by taking the side wall and the rest of the organic dielectric layer as masks to form a required pattern in the layer to be patterned.

Optionally, the layer to be patterned formed in step S1 includes a floating gate layer, a gate oxide layer and a hard mask layer stacked in sequence from bottom to top, where the layer to be patterned is used to form a memory cell of the NAND flash memory; in step S5, etching is stopped on the surface of the gate oxide layer.

Optionally, in step S1, the step of forming a plurality of spacers at intervals on the amorphous silicon layer of the core active region includes:

s1.1, forming a plurality of core structures arranged at intervals on the amorphous silicon layer of the core active region;

s1.2, forming side walls on the side walls of the core structures;

s1.3, removing each core structure.

Optionally, the core structure formed in step S1.1 includes a first oxide layer and a second oxide layer stacked in sequence from bottom to top.

Optionally, the material of the deposited sidewall spacer in step S1.2 includes silicon nitride.

Optionally, the first oxide layer has a denseness greater than that of the second oxide layer.

Optionally, in step S1.3, the step of removing each of the core structures includes:

s1.3.1, removing the first oxide layer of each core structure by a first etching process;

s1.3.2, removing the second oxide layer by a second etching process.

Optionally, the first etching process is a dry etching process, and the second etching process is a wet etching process.

Optionally, in the step S2, the top surface of the formed organic dielectric layer is flush with the top surfaces of the side walls.

Optionally, the line width of the core structure is equal to the line width of a gap between adjacent sidewalls of adjacent core structures.

Compared with the prior art, the technical scheme provided by the invention has at least one of the following beneficial effects:

1. the organic dielectric layer is filled in the gap of the side wall with the high depth-width ratio of the core active region, so that the photoresist is prevented from being directly contacted with the side wall, the photoresist is coated on the organic dielectric layer, and when the patterned photoresist layer is formed by exposure and development, development residues remained in the gap of the side wall after the photoresist is developed are avoided, and further, the development defect of the photoresist can be avoided.

2. Furthermore, the top surface of the organic dielectric layer is flush with the top surface of the side wall, so that the subsequent downward etching can be continued by using the side wall and the organic dielectric layer with the same height as the mask, and the quality of the pattern formed in the layer to be patterned is ensured.

3. The core structure can be conveniently and effectively removed by carrying out two-step etching process treatment of dry etching and wet etching on the core structures arranged at intervals, so that an organic dielectric layer with higher thickness uniformity can be conveniently formed on the surface of the amorphous silicon layer, and in the process of etching the organic dielectric layer to the surface of the amorphous silicon layer by taking the patterned photoresist as a mask, organic dielectric layer residues generated in a core active region can be prevented from being left in a side wall gap, and the performance of a subsequent process is improved.

Drawings

Fig. 1a-1b are schematic cross-sectional views illustrating a device structure in a conventional NAND flash memory manufacturing method.

Fig. 2 is a schematic diagram of a top view structure of a sidewall in a conventional NAND flash memory manufacturing method.

FIG. 3 is a flowchart illustrating a method for improving lithography development defects in an active area of a NAND flash memory according to an embodiment of the present invention.

FIGS. 4 a-4 d are schematic cross-sectional views illustrating the structure of a device in a method for improving lithography development defects in an active area of a NAND flash memory according to an embodiment of the present invention.

Wherein the reference numbers are as follows:

100-a semiconductor substrate; 200-a floating gate layer; 300-a gate oxide layer; 400-a hard mask layer; 500-an amorphous silicon layer; 600-side walls; 600a, 600 b-sidewall spacer; 700-a first oxide layer; 701-a second oxide layer; 800-patterned photoresist layer; 800 a-development residue; 900-organic dielectric layer.

Detailed Description

The method for improving the lithography development defect of the active area of the NAND flash memory according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

The current manufacturing process of NAND flash memory generally includes the following steps: first, as shown in fig. 1a, a floating gate layer 200, a gate oxide layer 300, a hard mask layer 400, an amorphous silicon layer 500, and a core layer (including a first oxide layer 700 and a second oxide layer 701) are deposited on a substrate 100 having a core active region I and a peripheral region II; then, as shown in fig. 1a-1b and fig. 2, etching a core required by the core active region I by photolithography and etching processes, depositing a sidewall material and etching to form a sidewall 600 on the sidewall of the core, where the sidewall 600 surrounding the core is an annular sidewall, which encloses a sidewall gap 600a, and a linear sidewall gap 600b is formed between the sidewalls 600 of adjacent cores; next, a photoresist is coated and exposed to light and developed to form the patterned photoresist layer 800 on the peripheral region II.

In the above process, since the sidewalls of the core active region I and the lower film layer are both in direct contact with the photoresist, and since the aspect ratio of the gap between the sidewalls 600 is large, and the sidewalls 600 are usually ring-shaped walls, it is easy to block the ingress and egress of the developing solution during the photolithography development, so that some developing residues 800a are easily generated to be left in the sidewall gap 600a surrounded by the sidewalls 600 having the high aspect ratio, and it is difficult to remove the developing residues even if the subsequent cleaning process is performed, and therefore when the patterned photoresist layer 800 and the sidewalls 600 are used as masks and the lower amorphous silicon layer 500 and other film layers are etched, the developing residues 800a are also used as masks to perform the pattern downward transfer, thereby introducing the device defect.

Therefore, the invention provides a method for improving the photoetching development defect of the active area of the NAND flash memory, so that the development residues are prevented from being left in the side wall gap with the high depth-to-width ratio, and further the device defect caused by the development residues in the subsequent process is avoided.

Referring to fig. 3, fig. 3 is a flowchart of a method for improving lithography development defects of an active area of a NAND flash memory according to an embodiment of the present invention. Specifically, the method for improving the lithography development defect of the active area of the NAND flash memory provided by the embodiment includes the following steps:

s1, providing a semiconductor substrate with a core active region and a peripheral region, sequentially forming a layer to be patterned and an amorphous silicon layer on the semiconductor substrate, and forming a plurality of side walls arranged at intervals on the amorphous silicon layer of the core active region;

s2, covering an organic dielectric layer on the amorphous silicon layers of the core active region and the peripheral region, wherein the organic dielectric layer is also filled in the gap of the side wall;

s3, coating photoresist on the organic dielectric layer, and exposing and developing to form a patterned photoresist layer and define the photoresist pattern required in the peripheral region;

s4, etching the organic dielectric layer to the surface of the amorphous silicon layer by taking the patterned photoresist layer as a mask so as to remove the organic dielectric layer of the core active region and reserve the required organic dielectric layer in the peripheral region;

and S5, removing the patterned photoresist layer, and etching the amorphous silicon layer and the layer to be patterned by taking the side wall and the rest of the organic dielectric layer as masks to form a required pattern in the layer to be patterned.

In other words, in the method for improving the lithography development defect of the NAND flash active region provided by the invention, the organic dielectric layer is filled in the side wall gap with the high aspect ratio, so that the contact between the photoresist and the side wall can be avoided, the development residue can be prevented from being left in the side wall gap, and the generation of the lithography development defect of the photoresist can be avoided.

Fig. 4a to 4d are schematic cross-sectional views of a device in a method for improving lithography development defects of an active area of a NAND flash memory according to an embodiment of the invention.

In step S1, referring to fig. 4a in particular, a semiconductor substrate 100 having a core active region I and a peripheral region II is provided, a layer to be patterned and an amorphous silicon layer 500 are sequentially formed on a surface of the semiconductor substrate 100, and a plurality of spacers 600 arranged at intervals are formed on the amorphous silicon layer 500. The peripheral region II is located at the periphery of the core active region I, and may be disposed around the core active region I, or may be located only on one side of the core active region I.

The semiconductor substrate 100 provides a process platform for subsequently forming semiconductor devices. In the embodiment of the present invention, the semiconductor substrate 100 is used to form a NAND flash memory, and the layer to be patterned is used to form memory cells of the NAND flash memory.

In this embodiment, the semiconductor substrate 100 is a silicon substrate. In other embodiments, the material of the semiconductor substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the semiconductor substrate 100 may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the semiconductor substrate 100 may be a material suitable for process requirements or easy integration.

In this embodiment, the layer to be patterned includes a floating gate layer 200, a gate oxide layer 300, and a hard mask layer 400 sequentially stacked on a semiconductor substrate 100. The material of the floating gate layer 200 may be doped polysilicon, the gate oxide layer 300 may be silicon dioxide, and the material of the hard mask layer 400 may be silicon nitride, silicon oxynitride, or Tetraethylorthosilicate (TEOS).

In an embodiment of the present invention, the process of forming the sidewall spacers 600 on the amorphous silicon layer 500 in step S1 includes:

s1.1, depositing a core layer (such as the first oxide layer 700 and the second oxide layer 701 in fig. 1 a) on the amorphous silicon layer 500, and etching the core layer by photolithography and etching processes to form a plurality of core structures (not shown) spaced apart on the core active region I;

s1.2, depositing sidewall materials such as silicon nitride and the like on the core structure and the amorphous silicon layer 500, performing sidewall etching,

s1.3, removing each core structure through an etching process, wherein a closed side wall gap (shown as 600a in FIG. 2) is formed in the side wall 600 surrounding the core, and an open side wall gap (shown as 600a in FIG. 2) is formed between the side walls 600 of adjacent core structures.

In this embodiment, the core structures in the core active region II are the same in size and shape, and the spacing distances between adjacent core structures are the same.

Further, in step S1.2, spacers 600 are formed on the outer sidewalls of the core structures, and the spacers 600 may be used to manufacture the floating gate structure in the NAND.

The material of the deposited sidewall in step S1.2 may be silicon nitride, or any other suitable material, and may be a single-layer structure, or a structure formed by compounding multiple layers of materials.

In this embodiment, the line width of the core structure is equal to the line width of the gap between the adjacent side walls 600 of the adjacent core structures, so that the side walls 600 are uniformly distributed in the core active region I. That is, the sidewall gap surrounded by the annular sidewall 600 is equal to the sidewall gap between adjacent annular sidewalls 600.

It should be noted that in this embodiment, the compactness of the first oxide layer for forming the core structure is greater than that of the second oxide layer, so that when a plurality of spacers 600 are formed, the features of the spacers 600 are better.

Optionally, in S1.3, the step of removing each core structure includes:

s1.3.1, removing the first oxide layer on the top layer by etching with a first etching process to form an opening between the side walls 600;

s1.3.2, etching the second oxide layer along the opening by the second etching process until the etching reaches the surface of the amorphous silicon layer 500 to remove each core structure.

In this embodiment, the first etching process is a dry etching process, and the second etching process is a wet etching process. Illustratively, the first etching process is a plasma etching process, and the second etching process can etch the core structure through a wet etching solution with a preset selection ratio, such as phosphoric acid, hydrofluoric acid, and the like.

Optionally, in other embodiments of the present invention, two ends of the annular sidewall 600 may be etched and opened first, so that an etchant for removing the core structure subsequently enters into a sidewall gap surrounded by the annular sidewall 600 smoothly, and then the core structure is etched and removed, for example, the first oxide layer and the second oxide layer of the core structure are etched by an etching solution with a preset selection ratio until the core structure is removed.

Referring to fig. 4a, in order to prevent the photoresist from contacting the sidewall spacers 600 and the amorphous silicon layer 500 to generate the development residue, step S2 may be performed, in which an organic dielectric layer 900 is deposited or coated on the surfaces of the amorphous silicon layer 500 and the sidewall spacers 600 to fill the organic dielectric layer 900 in each sidewall gap, and further, the top surface of the organic dielectric layer 900 may be planarized by a planarization process such as chemical mechanical polishing until the top surfaces of the sidewall spacers 600 are exposed, at which time the top surfaces of the organic dielectric layer 900 are flush with the top surfaces of the sidewall spacers 600.

Referring to fig. 4a and 4b, the step S3 is performed to coat a photoresist on the surface of the organic dielectric layer 900, and expose and develop the photoresist to remove the photoresist on the surface of the organic dielectric layer 900 in the core active region I and leave a desired pattern of photoresist on the surface of the organic dielectric layer 900 in the peripheral region II, thereby forming the patterned photoresist layer 800. The patterned photoresist layer 800 may define, for example, the select gates of the NAND or the gates of the transistors in the peripheral region. In the exposure and development process, since the gap of the sidewall spacer 600 is filled with the organic dielectric layer 900, no development residue is generated.

Referring to fig. 4c, in step S4, the patterned photoresist layer 800 is used as a mask, and an etching process (e.g., a dry etching process) is performed to remove the organic dielectric layer 900 on the core active region I and the excess organic dielectric layer 900 in the peripheral region II by using the organic dielectric layer 900 having a higher etching selectivity with respect to the sidewall 600, so that the organic dielectric layer 900 at the bottom of the patterned photoresist layer 800 is remained.

Referring to fig. 4d, in step S5, the patterned photoresist layer 800 is removed, and then the amorphous silicon layer 500 and the layer to be patterned with a partial thickness or a full thickness are etched using the sidewall spacers 600 in the core active region I and the remaining organic dielectric layer 900 in the peripheral region II as masks to form a desired pattern in the layer to be patterned. Wherein, when the layer to be patterned includes the floating gate layer 200, the gate oxide layer 300 and the hard mask layer 400 stacked in sequence from bottom to top, in step S5, the amorphous silicon layer 500 and the hard mask layer 400 of the entire thickness are etched with the sidewall 600 in the core active region I and the organic dielectric layer 900 remaining in the peripheral region II as masks, the etching is stopped on the top surface of the gate oxide layer 300, to transfer the pattern of the sidewall spacers 600 and the organic dielectric layer 900 into the hard mask layer 400, after which the sidewall spacers 600 and the organic dielectric layer 900 may be removed, then, using the hard mask layer 400 as a mask, the gate oxide layer 300 and the floating gate layer 200 are continuously etched, the etching is stopped on the surface of the semiconductor substrate 100, in a pattern required for forming a NAND flash memory, such as a floating gate required for each memory cell of a memory array, at this time, the floating gate layer 200 remaining in the peripheral region II may form a select gate required for a NAND flash memory or a gate required for a logic transistor, etc.

In summary, in the method for improving the lithography development defect of the NAND flash active region provided by the present invention, the organic dielectric layer is filled in the spacer gap with the high aspect ratio, so that the photoresist can be prevented from contacting the spacer, the development residue can be prevented from remaining in the spacer gap, and the development defect of the photoresist can be prevented from being generated.

Furthermore, in the method for improving the lithography development defect of the active region of the NAND flash memory, the core structures arranged at intervals are subjected to two-step etching process of dry etching and wet etching, so that the core structures can be conveniently and effectively removed, the organic dielectric layer can be conveniently deposited on the surface of the amorphous silicon layer, the top surface of the organic dielectric layer is flush with the top surface of the side wall, and then the downward etching can be continuously carried out by taking the side wall and the organic dielectric layer with the same height as a mask in the follow-up process, so that the quality of the pattern formed in the layer to be patterned is ensured.

The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the present invention.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated. The meaning of "and/or" herein is either or both.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.