阅读说明：本技术 一种SiC/Si Cascode器件用多芯片并联结构 (Multi-chip parallel structure for SiC/Si Cascode device ) 是由 王来利 赵成 杨俊辉 潘东 程登峰 汪胜和 于 2021-07-29 设计创作，主要内容包括：本发明公开了一种SiC/Si Cascode器件用多芯片并联结构,包括低压Si MOSFET和SiC JFET,多个低压Si MOSFET和多个SiC JFET以共栅共源的方式连接构成一个SiC/Si Cascode器件；多个SiC JFET的源极之间通过桥接支路连接。本发明极大的抑制多个SiC/Si Cascode器件并联时开关过程中电流的不均衡,进而抑制并联芯片之间的开关损耗和结温差异,避免了局部热应力集中的情况,提高了并联整体的可靠性。(The invention discloses a multi-chip parallel structure for a SiC/Si Cascode device, which comprises a low-voltage Si MOSFET and a SiC JFET, wherein the low-voltage Si MOSFET and the SiC JFET are connected in a common-gate-common-source mode to form the SiC/Si Cascode device; the sources of the SiC JFETs are connected through a bridge branch. The invention greatly inhibits the unbalance of current in the switching process when a plurality of SiC/Si Cascode devices are connected in parallel, thereby inhibiting the switching loss and junction temperature difference between chips connected in parallel, avoiding the condition of local thermal stress concentration and improving the reliability of the whole parallel connection.)

1. A multi-chip parallel structure for a SiC/Si Cascode device is characterized by comprising a low-voltage Si MOSFET and SiC JFETs, wherein the low-voltage Si MOSFET and the SiC JFETs are connected in a common-gate-common-source mode to form the SiC/SiCascode device; the sources of the SiC JFETs are connected through a bridge branch.

2. The multi-chip parallel structure for SiC/Si Cascode device according to claim 1, wherein the low voltage Si MOSFET is M₁，M₂，……，M_nSiC JFET of J₁，J₂，……，J_n；M₁，M₂，……，M_nThe grid G of the grid is connected to the G, M of the parallel structure after being connected in parallel₁，M₂，……，M_nAre respectively connected with corresponding J₁，J₂，……，J_nPower source m₁，m₂，……，m_n；M₁，M₂，……，M_nIs respectively connected with the driving source electrode k through the corresponding power source electrodes s and J₁，J₂，……，J_nThe driving source electrode K is connected in parallel with the parallel structure K, and the power source electrode S is connected in parallel with the parallel structure S, J₁，J₂，……，J_nThe drain D of (a) is connected in parallel with D of the parallel structure.

3. The multi-chip parallel structure for SiC/Si Cascode device according to claim 2, wherein J is₁，J₂，……，J_nPower source m₁，m₂，……，m_nAre connected in parallel.

4. The multi-chip parallel structure for SiC/Si Cascode devices according to claim 1, wherein a plurality of SiC/Si Cascode devices are connected in parallel to constitute a switch of a power module.

5. The multi-chip parallel structure for SiC/Si Cascode device according to claim 4, wherein a plurality of SiC/Si Cascode devices share one drive.

Technical Field

The invention belongs to the technical field of power electronic devices, and particularly relates to a multi-chip parallel structure for a SiC/Si Cascode device.

Background

In recent years, third generation power semiconductor devices, mainly Silicon carbide (SiC) devices, have been developed rapidly. Compared with the traditional silicon device, the SiC device has the excellent characteristics of small on-resistance, small parasitic capacitance, high maximum switching frequency, high maximum working junction temperature and the like. Therefore, the SiC device has great potential and wide development prospect in a plurality of application occasions such as charging piles and motor driving systems of electric vehicles, photovoltaic inverters, multi-electric planes, ship power supply systems, direct-current circuit breakers in power grids and the like.

The currently mainstream fully-controlled SiC chip mainly includes a SiC Junction Field Effect Transistor (JFET) and a SiC Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The manufacturing process of the SiC JFET chip is relatively mature, but the SiC JFET chip is usually a normally-open device, and the driving method for direct use is complicated. In practical applications, normally-on SiC JFETs are commonly connected in Cascode with a low-voltage normally-off MOSFET to form a normally-off device, referred to as a SiC/Si Cascode device. The SiC JFET and the low-voltage MOSFET are directly stacked together by the United SiC manufacturer through a nano-silver sintering mode to form a chip, and therefore the SiC JFET and the low-voltage MOSFET which are connected in a cascode mode can be integrally regarded as the chip. Compared with a SiC MOSFET, the SiC/Si Cascode device has no problem of gate oxide layer defect, and the thermal stability of the threshold voltage is better; under the same voltage resistance level and the like, because the SiC JFET is usually a normally-on device, the overall on-state resistance of the SiC/Si Cascode device can be lower than that of a SiC MOSFET, and further the conduction loss is smaller; in the switching process, the SiC/Si Cascode device has a mechanism of spontaneously forming current type drive, so that the switching speed is greatly improved, and the switching loss is reduced; in addition, the reverse conduction performance of the SiC/Si Cascode device is determined by the body diode of the low-voltage MOSFET, which has certain advantages in terms of reverse recovery characteristics and conduction voltage drop compared to the body diode of the SiC MOSFET having a relatively high withstand voltage. Besides the advantages in partial device performance, the maturity of the SiC/Si Cascode device in the aspect of chip manufacturing process is higher than that of the SiC MOSFET, so that the SiC/Si Cascode device may play an important role in future market promotion and application.

In the production manufacturing process of SiC chips, in order to improve the yield of the chips, the area of a single SiC chip is generally small, which further results in a small current capacity of the single SiC chip. The maximum current capacity of a single SiC chip in the market is 200A at present, the current carrying capacity of the device is required to reach 400A or even higher in most application occasions, and in order to meet the requirement of higher current carrying capacity, multiple SiC chips are generally required to be subjected to parallel capacity expansion. When a plurality of SiC chips are connected in parallel, the current borne by each chip is inconsistent due to the differences in the parameters, layout and heat dissipation conditions of the devices. This may further cause on-state losses and switching losses of the parallel chips to vary, resulting in different junction temperatures of the respective chips. This causes different chips to experience different thermal and power cycles during actual continuous operation, resulting in inconsistent degradation of the individual chips in parallel. The difference of current borne by the parallel chips can be further increased due to the inconsistent performance degradation degree of the chips, the aging and the failure of part of the chips are accelerated, and the integral reliability and the service life of the parallel chips are threatened. In order to avoid the harm caused by uneven current distribution when a plurality of SiC chips are connected in parallel, in practical application occasions, the SiC chips are usually used in a de-rated mode after being connected in parallel, so that the reliability problem caused by overlarge current stress borne by part of the chips is avoided. However, this is very economical and the current carrying capability of most SiC chips is not fully utilized. In order to fully utilize the current capacity of each SiC chip and avoid serious reliability problems, deep research needs to be performed on the parallel current sharing characteristics of a plurality of SiC chips, and a corresponding optimization design scheme is proposed, which has an extremely important significance for the application and popularization of the SiC chips in practice.

At present, some optimization design method strategies aiming at the problem of parallel current sharing of SiC MOSFETs are provided, including layout optimization of a main power loop, layout optimization of a driving loop, a current sharing strategy of an integrated magnetic element, and modes of realizing current sharing by adopting active drive control and the like. But the optimization of the parallel current sharing problem of a plurality of SiC/Si Cascode devices is basically blank. Because the SiC/Si Cascode device is a composite device formed by connecting two devices through a common gate and a common source, the current equalizer system is more complex compared with a SiC MOSFET, and has higher degree of freedom and more parameters capable of being optimally designed.

Disclosure of Invention

The invention aims to solve the technical problem of providing a multi-chip parallel structure for SiC/Si Cascode devices, which is used for parallel connection of discrete SiC/Si Cascode devices designed based on PCB layout and can also be used for parallel connection of bare chips of SiC/Si Cascode devices in the packaging process, is easy to implement, does not increase the complexity of layout or packaging design, does not need extra cost, and is suitable for large-scale market application.

The invention adopts the following technical scheme:

a multi-chip parallel structure for a SiC/Si Cascode device comprises a low-voltage Si MOSFET and SiC JFETs, wherein the low-voltage Si MOSFET and the SiC JFETs are connected in a common-gate-common-source mode to form the SiC/Si Cascode device; the sources of the SiC JFETs are connected through a bridge branch.

Specifically, the low voltage Si MOSFET is M₁，M₂，……，M_nSiC JFET of J₁，J₂，……，J_n；M₁，M₂，……，M_nThe grid G of the grid is connected to the G, M of the parallel structure after being connected in parallel₁，M₂，……，M_nAre respectively connected with corresponding J₁，J₂，……，J_nPower source m₁，m₂，……，m_n；M₁，M₂，……，M_nIs respectively connected with the driving source electrode k through the corresponding power source electrodes s and J₁，J₂，……，J_nThe driving source electrode K is connected in parallel with the parallel structure K, and the power source electrode S is connected in parallel with the parallel structure S, J₁，J₂，……，J_nThe drain D of (a) is connected in parallel with D of the parallel structure.

Further, J₁，J₂，……，J_nPower source m₁，m₂，……，m_nAre connected in parallel.

Specifically, a plurality of SiC/Si Cascode devices are connected in parallel to form a switch of the power module.

Further, a plurality of SiC/Si Cascode devices share one drive.

Compared with the prior art, the invention has at least the following beneficial effects:

according to the multi-chip parallel structure for the SiC/Si Cascode device, after the SiC/Si Cascode devices are connected in parallel, the auxiliary branch circuits are additionally arranged, and the source electrodes of SiC JFETs in all the parallel devices are directly connected together, so that the integral symmetry of the parallel structure is increased, the balanced distribution of the switching-on current is promoted, and the junction temperature between the parallel chips is further balanced; the capability of carrying large current of the whole device can be greatly improved through the parallel connection of a plurality of chips, the current difference of the parallel chips at the turn-on moment can be greatly restrained by connecting the source electrodes of all the SiC JFETs through the bridging branch, and the reliability of the whole parallel connection is enhanced.

Furthermore, the low-voltage Si MOSFET and the SiC JFET are directly connected through copper wires on the PCB or directly connected on the die in a packaging mode, parasitic inductance on a connecting wire is reduced, and overall switching performance is improved.

Further, J₁，J₂，……，J_nPower source m₁，m₂，……，m_nThe parallel connection between the SiC JFET gates and the source electrodes promotes the balance of voltage between the SiC JFET gates and the source electrodes in the parallel devices, and further inhibits the difference of opening current between the parallel chips.

Furthermore, a plurality of SiC/Si Cascode devices are connected in parallel to form a switch of the power module, so that the current carrying capacity of the power module can be greatly improved.

Furthermore, a plurality of SiC/Si Cascode devices share one drive, so that the structure is simple, and the control is convenient.

In summary, the invention is suitable for the imbalance of chip equivalent thermal resistance and junction temperature difference caused by incomplete symmetry of chip distribution position, DBC layout and heat dissipation conditions, and simultaneously realizes the integration of the driving resistor and improves the driving stability.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

FIG. 1 is a circuit block diagram of the present invention;

fig. 2 is a schematic diagram of current optimization according to the present invention, wherein (a) is current distribution before optimization and (b) is current distribution after optimization.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

It is to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Various structural schematics according to the disclosed embodiments of the invention are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers and their relative sizes and positional relationships shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, according to actual needs.

The invention provides a multi-chip parallel structure for a SiC/Si Cascode device, which is characterized in that when the SiC/Si Cascode device is connected in parallel, the sources of SiC JFETs in the SiC/Si Cascode device connected in parallel are connected together by adding an auxiliary bridge branch circuit. By adopting the circuit structure, the influence of asymmetric layout on the dynamic current-sharing performance of a plurality of SiC/Si Cascode devices connected in parallel can be reduced, the switching current distribution of the SiC/Si Cascode devices connected in parallel is effectively balanced, the uniform distribution of switching loss is promoted, the condition that the junction temperature of part of chips in the chips connected in parallel is overhigh is inhibited, the integral current bearing capacity and reliability of the chips connected in parallel are improved, the potential and value of the SiC/Si Cascode devices in practical application are fully exerted, and the technical blank of the parallel capacity expansion of the SiC/Si Cascode devices is filled.

Referring to FIG. 1, the multi-chip parallel structure for SiC/Si Cascode device of the present invention comprises a low voltage Si MOSFET and a SiC JFET, wherein the low voltage Si MOSFET in the SiC/Si Cascode device is M₁，M₂，……，M_nThe SiC JFET in the SiC/Si Cascode device is J₁，J₂，……，J_n(ii) a Mi and Ji are connected together in a cascade mode to form a SiC/Si Cascode device, d, g, k and s respectively represent a drain electrode, a grid electrode, a driving source electrode and a power source electrode of the SiC/Si Cascode device, and a plurality of SiC/Si Cascode devices are connected in parallel to form a switching device with the capability of switching on and off large current.

In particular, M₁，M₂，……，M_nThe grid G of the grid is connected to the G, M of the parallel structure after being connected in parallel₁，M₂，……，M_nDrain electrodes d of (1) are connected in parallel to correspond to J₁，J₂，……，J_nA power source s; m₁，M₂，……，M_nIs respectively connected with the driving source electrode k through the corresponding power source electrodes s and J₁，J₂，……，J_nThe driving source electrode K is connected in parallel with the parallel structure K, and the power source electrode S is connected in parallel with the parallel structure S, J₁，J₂，……，J_nThe drain D of (a) is connected in parallel with D of the parallel structure.

To promote even distribution of switching current between parallel chips, power source (m) of SiC JFET in SiC/Si Cascode device₁，m₂，……，m_n) The gate and source voltage of the SiC JFET in the SiC/Si Cascode device are balanced and distributed, and therefore current is balanced and distributed.

The power module comprises a power module and is characterized in that a plurality of SiC/Si Cascode devices are connected in parallel to form a switch of the power module, the plurality of SiC/Si Cascode devices share one drive, a main body DBC substrate of the power module is provided with a rectangular region used for adjusting chip equivalent thermal resistance, the rectangular region is arranged in a bottom copper layer of the main body DBC substrate, the main body DBC substrate is provided with a drive resistor DBC substrate, the topological structure of the power module is a half-bridge structure and comprises an upper bridge arm and a lower bridge arm, and the plurality of SiC/Si Cascode devices are arranged at the switch positions of the upper bridge arm and the lower bridge arm in parallel.

The invention can be used for parallel connection of discrete SiC/Si Cascode devices designed based on PCB layout and can also be used for parallel connection of bare chips of the SiC/Si Cascode devices in the packaging process. The method is low in implementation difficulty, does not increase the complexity of layout or packaging design, basically does not need extra cost, and is suitable for large-scale market application.

Referring to fig. 2, in fig. 2(a), after two SiC/Si cascode devices are directly connected in parallel, the respective on-currents of the two chips are shown, and it can be seen that the on-currents of the two chips have a large difference; and fig. 2(b) shows the condition that the two parallel SiC/Si cascode devices respectively turn on currents after the bridge branch is adopted for optimization, and it can be seen that the difference of the turn-on currents at this time is greatly reduced and basically approaches to the same, so that the effectiveness of the proposed optimization method can be verified.

In conclusion, the multi-chip parallel structure for the SiC/Si Cascode devices greatly inhibits the unbalance of current in the switching process when the SiC/Si Cascode devices are connected in parallel, further inhibits the switching loss and junction temperature difference between the chips connected in parallel, avoids the condition of local thermal stress concentration, and improves the reliability of the whole parallel connection.

The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.