阅读说明：本技术 延迟锁相回路装置及其操作方法 (Delay phase locked loop device and operation method thereof ) 是由 奥野晋也 于 2020-05-28 设计创作，主要内容包括：本发明提供一种延迟锁相回路(delay-locked loop,DLL)装置以及用于DLL装置的操作方法。DLL装置包括延迟线、复本电路、相位检测器以及延迟控制器。延迟线反应于延迟码对输入时钟进行延迟以提供延迟时钟。复本电路依据延迟时钟产生回馈时钟。相位检测器比较输入时钟以及回馈时钟以产生延迟控制信号。延迟控制器基于控制时钟依据延迟控制信号在第一时间点产生延迟码,延迟复本延迟时间长度以在第二时间点将延迟码提供到延迟线。延迟线在第二时间点调整输入时钟。控制时钟的周期被调整为大于复本延迟时间长度。(The present invention provides a delay-locked loop (DLL) device and an operating method for the DLL device. The DLL device includes a delay line, a replica circuit, a phase detector, and a delay controller. The delay line delays the input clock in response to the delay code to provide a delayed clock. The replica circuit generates a feedback clock according to the delay clock. The phase detector compares the input clock and the feedback clock to generate a delay control signal. The delay controller generates a delay code at a first time point according to a delay control signal based on a control clock, delays a replica delay time length to provide the delay code to the delay line at a second time point. The delay line adjusts the input clock at a second point in time. The period of the control clock is adjusted to be greater than the replica delay time length.)

1. A delay locked loop device, comprising:

a delay line configured to receive an input clock and delay the input clock in response to a multi-bit delay code to provide a delayed clock;

a replica circuit, coupled to the delay line, configured to receive the delayed clock and generate a feedback clock according to the delayed clock;

a phase detector, coupled to the replica circuit, configured to receive the input clock and the feedback clock, and compare the input clock and the feedback clock to generate a delay control signal; and

a delay controller coupled to the phase detector and the delay line, configured to generate the delay code at a first time point according to the delay control signal based on a control clock, delay a replica delay time length to provide the delay code to the delay line at a second time point, and make the delay line adjust the timing of the input clock at the second time point,

wherein a period of the control clock is adjusted to be greater than the replica delay time length.

2. The dll device of claim 1, wherein based on the control clock, the delay controller provides another delay code at a third time point after the second time point, wherein a length of time between the third time point and the first time point is substantially equal to a period of the control clock.

3. The dll device of claim 1, wherein the replica delay time length is adjusted according to a transistor skew generated by a manufacturing process of the dll device, wherein the transistor skew is determined by a threshold voltage value in a transistor.

4. The dll device of claim 3, wherein the replica delay time length is increased in accordance with a slow one of the transistor skews, wherein the replica delay time length is decreased in accordance with a fast one of the transistor skews.

5. The dll apparatus of claim 1, further comprising:

an oscillator, coupled to the delay controller, configured to provide the control clock.

6. The dll device of claim 5, wherein the oscillator is enabled according to an enable signal to provide the control clock.

7. The dll device of claim 6, further comprising:

an enable signal generator, coupled to the oscillator, configured to provide the enable signal.

8. The dll device of claim 7, wherein the enable signal generator is further coupled to the delay line, the replica circuit, the phase detector and the delay controller, and is configured to enable the delay line, the replica circuit, the phase detector and the delay controller via the enable signal.

9. An operating method for a delay locked loop device, the operating method comprising:

receiving an input clock and delaying the input clock in response to a multi-bit delay code to provide a delayed clock;

generating a feedback clock according to the delay clock;

comparing the input clock and the feedback clock to generate a delay control signal; and

generating the delay code at a first time point based on a control clock according to the delay control signal, delaying a replica delay time length to provide the delay code at a second time point, and adjusting the timing of the input clock at the second time point,

wherein a period of the control clock is adjusted to be greater than the replica delay time length.

10. The method of operation of claim 9, further comprising:

providing a further delay code at a third point in time after said second point in time,

wherein a length of time between the third point in time and the first point in time is substantially equal to a period of the control clock.

11. The method of operation of claim 9, further comprising:

adjusting the replica delay time length according to a transistor skew generated by a process of the delay locked loop device, wherein the transistor skew is determined by a threshold voltage value in a transistor.

12. The method of operation of claim 11 wherein the replica delay time length is increased in accordance with slow skew in the transistor skew, wherein the replica delay time length is decreased in accordance with fast skew in the transistor skew.

13. The method of operation of claim 9, further comprising:

and providing the control clock according to an enabling signal.

Technical Field

The present invention relates to a delay locked loop device and an operating method thereof, and more particularly, to a delay locked loop device and an operating method thereof applicable to any input clock period.

Background

Generally, a delay-locked loop (DLL) is set to adjust the received input clock to the desired delay clock within a predetermined period. However, in the case where the input clock has a small period, the DLL frequently undergoes an over shift (over shift), thereby causing the delay clock to suffer from insufficient delay or excessive delay. In the case of an input clock having a large period, the DLL may improve the excessive skew, but may fail to adjust the received input clock to the desired delay clock within a default period.

Therefore, designing a delay locked loop device suitable for any period of the input clock is one of the subjects of the research and study of those skilled in the art.

Disclosure of Invention

The invention provides a delay phase-locked loop device suitable for any period of an input clock and an operation method of the delay phase-locked loop device.

The delay locked loop device of the invention comprises a delay line, a replica circuit, a phase detector and a delay controller. The delay line is configured to receive an input clock and delay the input clock in response to a multi-bit delay code to provide a delayed clock. The replica circuit is coupled to the delay line. The replica circuit is configured to receive the delayed clock and generate a feedback clock according to the delayed clock. The phase detector is coupled to the replica circuit. The phase detector is configured to receive the input clock and the feedback clock and compare the input clock and the feedback clock to generate a delay control signal. The delay controller is coupled to the phase detector and the delay line. The delay controller is configured to generate a delay code at a first time point according to a delay control signal based on a control clock, delay a replica delay time length to provide the delay code to the delay line at a second time point, and cause the delay line to adjust a timing of the input clock at the second time point. The period of the control clock is adjusted to be greater than the replica delay time length.

The operation method of the invention is suitable for the delay phase-locked loop device. The operation method comprises the following steps: receiving an input clock and delaying the input clock in response to a multi-bit delay code to provide a delayed clock; generating a feedback clock according to the delay clock; comparing the input clock with the feedback clock to generate a delay control signal; and generating a delay code at a first time point based on the control clock according to the delay control signal, delaying the replica delay time length to provide the delay code at a second time point, and adjusting the timing of the input clock at the second time point, wherein the period of the control clock is adjusted to be greater than the replica delay time length.

Based on the above, the period of the control clock is adjusted to be greater than the replica delay time length, and the dll apparatus and the operating method can provide the delay code based on the control clock, so that the delay code adjusts the phase of the input clock after the replica delay time length. Therefore, the dll apparatus and the operating method of the present invention can be applied to any cycle of the input clock.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 is a schematic diagram of a delay locked loop device according to a first embodiment of the present invention;

FIG. 2A is a timing diagram of signals applied to an input clock having a minimum period according to an embodiment of the present invention;

FIG. 2B is a timing diagram of signals applied to an input clock having a maximum period according to an embodiment of the present invention;

FIG. 3A is a timing diagram of signals applied to slow skew according to one embodiment of the present invention;

FIG. 3B is a timing diagram of signals applied to fast skew according to one embodiment of the present invention;

FIG. 4 is a diagram illustrating a delay locked loop device according to a second embodiment of the present invention;

FIG. 5 is a schematic diagram of a delay locked loop device according to a third embodiment of the present invention;

fig. 6 is a flow chart illustrating a method of operation according to an embodiment of the present invention.

Description of the reference numerals

100. 200, 300 delay phase-locked loop devices;

110 a delay line;

120, a replica circuit;

130, a phase detector;

140 a delay controller;

150, an oscillator;

160, an enable signal generator;

d _ CLK delay clock;

DCD is a delay code;

DCS delaying control signals;

DN, UP are delay instructions;

ES, enabling signal;

FB _ CLK feeding back the clock;

i _ CLK is an input clock;

RDT is the replica delay time length;

s110 to S140, step;

t1, first time point;

t2, second time point;

t3, third point in time.

Detailed Description

Some embodiments of the invention will now be described in detail with reference to the drawings, wherein like reference numerals are used to refer to like or similar elements throughout the several views. These examples are only a part of the present invention and do not disclose all possible embodiments of the present invention. Rather, these embodiments are merely exemplary of the devices within the scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic diagram of a dll apparatus according to a first embodiment of the invention. The delay locked loop device 100 includes a delay line 110, a replica (replica) circuit 120, a phase detector 130, and a delay controller 140. The delay line 110 receives the input clock I _ CLK and delays the input clock I _ CLK in response to the multi-bit delay code DCD to provide a delayed clock D _ CLK. The replica circuit 120 is coupled to the delay line 110. The replica circuit 120 receives the delayed clock D _ CLK from the delay line 110 and generates the feedback clock FB _ CLK according to the delayed clock D _ CLK. The phase detector 130 is coupled to the replica circuit 120. The phase detector 130 receives the input clock I _ CLK and the feedback clock FB _ CLK, and compares the input clock I _ CLK and the feedback clock FB _ CLK to generate the delay control signal DCS.

Delay controller 140 is coupled to phase detector 130 and delay line 110. The delay controller 140 generates the delay code DCD at a first time point according to the delay control signal DCS based on the control clock CTRL _ CLK. In this embodiment, the delay control signal DCS includes delay commands UP, DN. The delay controller 140 increases the value of the delay code DCD according to the delay command UP. The delay line 110 increases the delay of the input clock I _ CLK according to the increased value of the delay code DCD. On the other hand, the delay controller 140 decreases the value of the delay code DCD according to the delay instruction DN. The delay line 110 decreases the delay of the input clock I _ CLK according to the reduced value of the delay code DCD. The delay controller 140 delays the replica delay time length RDT when generating the delay code DCD at the first time point to provide the delay code DCD to the delay line 110 at the second time point. Therefore, the delay line 110 adjusts the timing of the input clock I _ CLK at the second time point. In the present embodiment, the period of the control clock CTRL _ CLK is adjusted to be greater than the replica delay time length RDT and less than the replica delay time length RDT plus the time length of the period of the input clock I _ CLK. Next, after the second time point, the delay controller 140 provides another delay code DCD based on the control clock CTRL _ CLK.

It is worth mentioning that the period of the control clock CTRL _ CLK is adjusted to be larger than the replica delay time length RDT. That is, the dll device 100 follows the replica delay time length RDT to adjust the period of the control clock CTRL _ CLK, and the period of the control clock CTRL _ CLK is slightly larger than the replica delay time length RDT. The delay controller 140 is capable of generating another delay code DCD immediately after the feedback clock FB _ CLK is provided (i.e., during a time interval of at least one cycle of the input clock I _ CLK). For example, the period of the control clock CTRL _ CLK is adjusted to be greater than the replica delay time length RDT and less than the replica delay time length RDT plus the time length of a single input clock I _ CLK period. For another example, the period of the control clock CTRL _ CLK is adjusted to be greater than the replica delay time length RDT and less than the replica delay time length RDT plus the time length of 2 cycles of the input clock I _ CLK. Therefore, the delay controller 140 can generate another delay code DCD immediately after the feedback clock FB _ CLK is provided (i.e., within a time interval of 1 or 2 cycles of the input clock I _ CLK). Therefore, the dll apparatus 100 does not have an over shift condition in the case where the input clock I _ CLK has a small period. In addition, in the case where the input clock I _ CLK has a larger period, the dll device 100 adjusts the period of the control clock CTRL _ CLK according to the replica delay time length RDT. Therefore, the delay locked loop device 100 does not extend the time length for adjusting the input clock I _ CLK to the desired delay clock D _ CLK. In this way, the dll device 100 can adapt to any period of the input clock I _ CLK, and can adjust the received input clock I _ CLK to the desired delayed clock D _ CLK within a predetermined default period.

For example, referring to fig. 1 and fig. 2A together, fig. 2A is a signal timing diagram applied to an input clock having a minimum period according to an embodiment of the present invention. The timing diagram of the signal of the present embodiment is suitable for the dll apparatus 100. The delay controller 140 increases the value of the delay code DCD according to the delay command UP to increase the delay of the input clock I _ CLK. On the other hand, the delay controller 140 decreases the value of the delay code DCD according to the delay instruction DN to decrease the delay of the input clock I _ CLK. In the present embodiment, the delay controller 140 generates the delay code DCD at a first time point t1 according to the delay control signal DCS based on the control clock CTRL _ CLK. In the present embodiment, the delay controller 140 generates the delay code DCD associated with the delay control signal DCS based on a rising edge of the control clock CTRL _ CLK. In some embodiments, the delay controller 140 generates the delay code DCD associated with the delay control signal DCS based on a falling edge (falling edge) of the control clock CTRL _ CLK. The delay line 110 adjusts the timing of the input clock I _ CLK at a second time point t 2. The second time point t2 has a delay of the replica delay time length RDT with respect to the first time point t 1. In the present embodiment, the period of the control clock CTRL _ CLK is adjusted to be greater than the replica delay time length RDT. Therefore, the delay controller 140 generates another delay code DCD at a third time point t3 after the second time point t2 based on the control clock CTRL _ CLK. The length of time between the third time point t3 and the first time point t1 is substantially equal to the period of the control clock CTRL _ CLK.

In the present embodiment, the period of the control clock CTRL _ CLK depends on the replica delay time length RDT. Therefore, the delay controller 140 can generate another delay code DCD within a time interval of a period of the single input clock I _ CLK or a period of the single feedback clock FB _ CLK (the period of the input clock I _ CLK is substantially equal to the period of the feedback clock FB _ CLK) after the feedback clock FB _ CLK is provided. Therefore, the dll apparatus 100 does not have an excessive skew condition when the input clock I _ CLK has a minimum period.

For example, referring to fig. 1, fig. 2A and fig. 2B together, fig. 2B is a signal timing diagram applied to an input clock having a maximum period according to an embodiment of the present invention. The signal timing diagram of fig. 2B is also applicable to the dll apparatus 100. In the present embodiment, the replica delay time length RDT of fig. 2A is the same as the replica delay time length RDT of fig. 2B. Therefore, in the present embodiment, the period of the control clock CTRL _ CLK of fig. 2B may be equal to the period of the control clock CTRL _ CLK shown in fig. 2A. That is, therefore, in the case where the input clock I _ CLK has the largest period, the dll device 100 adjusts the period of the control clock CTRL _ CLK according to the replica delay time length RDT. Therefore, the delay locked loop device 100 does not extend the time length for adjusting the input clock I _ CLK to the desired delay clock D _ CLK.

Referring to fig. 1, fig. 3A and fig. 3B, fig. 3A is a timing diagram of signals applied to slow skew according to an embodiment of the present invention. FIG. 3B is a timing diagram of signals applied to fast skew according to an embodiment of the present invention. The signal timing diagram of fig. 3A and the signal timing diagram of fig. 3B are also applicable to the dll apparatus 100. In the present embodiment, the replica delay time length RDT is adjusted according to a transistor skew (skew) generated by the manufacturing process of the dll device 100. Transistor skew depends on the value of the threshold voltage in the transistor. For example, based on the manufacturing process of the dll device 100, when the transistors of the dll device 100 have larger threshold voltage values, this means that the dll device 100 has a slow skew (slow skew) condition, which causes the dll device 100 to have larger delay. The replica delay time length RDT is increased with slow skew as shown in fig. 3A. Since the replica delay time length RDT is increased with slow skew, the period of the control clock CTRL _ CLK is also increased.

For another example, when the transistors of the dll device 100 have smaller threshold voltage values, this means that the dll device 100 has a fast skew (fast skew) condition, which causes the dll device 100 to have smaller delay. The replica delay time length RDT is reduced with fast skew as shown in fig. 3B. Since the replica delay time length RDT is decreased with fast skew, the period of the control clock CTRL _ CLK is also decreased.

Referring to fig. 4, fig. 4 is a schematic diagram of a dll apparatus according to a second embodiment of the invention. Unlike the first embodiment, the delay locked loop device 200 further includes an oscillator 150. In the present embodiment, the oscillator 150 is coupled to the delay controller 140. The oscillator 150 provides a control clock CTRL _ CLK. In the present embodiment, the oscillator 150 receives the enable signal ES. The oscillator 150 is enabled according to the enable signal ES, and further provides the control clock CTRL _ CLK.

Referring to fig. 5, fig. 5 is a schematic diagram of a dll apparatus according to a third embodiment of the invention. Unlike the second embodiment, the dll apparatus 300 further includes an enable signal generator 160. In the present embodiment, the enable signal generator 160 is coupled to the oscillator 150. The enable signal generator 160 provides an enable signal ES. In the present embodiment, the enable signal generator 160 is further coupled to the delay line 110, the replica circuit 120, the phase detector 130 and the delay controller 140. The enable signal generator 160 also enables the delay line 110, the replica circuit 120, the phase detector 130 and the delay controller 140 through the enable signal ES.

Referring to fig. 1 and fig. 6, fig. 6 is a flowchart illustrating an operation method according to an embodiment of the invention. In step S110, the delay line 110 receives the input clock I _ CLK and delays the input clock I _ CLK in response to the multi-bit delay code DCD to provide a delayed clock D _ CLK. In step S120, the replica circuit 120 generates the feedback clock FB _ CLK according to the delayed clock D _ CLK. In step S130, the phase detector 130 compares the input clock I _ CLK and the feedback clock FB _ CLK to generate the delay control signal DCS. In step S140, based on the control clock, the delay controller 140 generates the delay code DCD at a first time point according to the delay control signal DCS, delays the replica delay time length to provide the delay code DCD at a second time point. And the delay line 110 adjusts the timing of the input clock I _ CLK at a second point in time. The implementation details of steps S110 to S140 of this embodiment can be sufficiently taught in at least the embodiments of fig. 1 to 3B, and therefore cannot be reiterated here.

In summary, the period of the control clock is adjusted to be greater than the replica delay time length, and the dll apparatus and the operating method can provide the delay code based on the control clock, so that the delay code adjusts the phase of the input clock after the replica delay time length. In this way, the dll apparatus and the operating method of the present invention can be applied to any cycle of the input clock, and can adjust the received input clock to the desired delay clock within a predetermined default cycle.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.