阅读说明：本技术 用于动态控制处理器的处理电路的电流消耗的系统、装置和方法 (System, apparatus and method for dynamically controlling current consumption of processing circuitry of a processor ) 是由 阿维纳什·N·阿南塔克里希南 阿美亚·安巴德卡 安库什·瓦尔玛 宁录·安琪儿 尼尔·罗森茨威 于 2020-03-19 设计创作，主要内容包括：在一个实施例中,一种装置包括：多个知识产权(IP)电路,该多个IP电路中的每一者包括配置寄存器,来存储动态电流预算；以及与多个IP电路耦合的功率控制器,该功率控制器包括动态电流共享控制电路,来接收关于要在多个IP电路中的至少一些上执行的工作负载的电流扼制提示信息并且至少部分基于此来为多个IP电路中的每一者生成动态电流预算。描述和要求保护了其他实施例。(In one embodiment, an apparatus comprises: a plurality of Intellectual Property (IP) circuits, each of the plurality of IP circuits comprising a configuration register to store a dynamic current budget; and a power controller coupled with the plurality of IP circuits, the power controller comprising a dynamic current sharing control circuit to receive current throttling hint information regarding workloads to be executed on at least some of the plurality of IP circuits and to generate a dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.)

1. An apparatus, comprising:

a plurality of Intellectual Property (IP) circuits, each of the plurality of IP circuits comprising a configuration register to store a dynamic current budget; and

a power controller coupled with the plurality of IP circuits, the power controller comprising a dynamic current sharing control circuit to receive current throttling hint information regarding workloads to be executed on at least some of the plurality of IP circuits and to generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon.

2. The apparatus of claim 1, wherein the power controller comprises a plurality of second configuration registers to store the current throttling hint information, wherein the dynamic current sharing control circuitry is to determine the dynamic current budgets for the plurality of IP circuits based on the current throttling hint information and one or more parameters of the apparatus.

3. The apparatus of claim 2, wherein the power controller comprises an interface to enable software to write the current throttling hint information to the plurality of second configuration registers.

4. The apparatus of claim 3, wherein the power controller is to receive the current throttling hint information from the software based on heuristic information regarding usage of the plurality of IP circuits during execution of the workload.

5. The apparatus of claim 2, wherein the dynamic current sharing control circuit is to determine the dynamic current budget for the plurality of IP circuits further based on a configured maximum current budget for each of the plurality of IP circuits.

6. The apparatus of claim 5, wherein, for a first workload, the dynamic current sharing control circuit is to:

setting a dynamic current budget for a first IP circuit to a configured maximum current budget for the first IP circuit; and is

Setting a dynamic current budget for a second IP circuit to be less than a configured maximum current budget for the second IP circuit.

7. The apparatus of claim 6, wherein for a second workload, the dynamic current sharing control circuit is to:

setting a dynamic current budget for the first IP circuit to be less than a configured maximum current budget for the first IP circuit; and is

Setting a dynamic current budget for the second IP circuit to a configured maximum current budget for the second IP circuit.

8. The apparatus of claim 6, wherein the first IP circuitry comprises a core and the second IP circuitry comprises a graphics processor.

9. The apparatus of claim 6, wherein, in response to a throttling signal from the power controller, the first IP circuitry is to limit operation to a configured maximum current budget for the first IP circuitry and the second IP circuitry is to limit operation to a dynamic current budget for the second IP circuitry.

10. The apparatus of claim 9, wherein the second IP circuit is to throttle one or more clock cycles of a clock signal in response to the throttle signal based on the dynamic current budget.

11. The apparatus of claim 1, wherein the dynamic current sharing circuit is to provide an opportunistic current budget to at least one of the plurality of IP circuits during a throttling event that enables the at least one IP circuit to exceed a dynamic current budget of the at least one IP circuit.

12. An apparatus, comprising:

a plurality of processing circuits to execute instructions;

a summing circuit coupled to the plurality of processing circuits, the summing circuit receiving a plurality of digital current values, each digital current value corresponding to a measured current from one of the plurality of processing circuits, the summing circuit generating a total current value from the plurality of digital current values; and

a current controller coupled to the summing circuit, the current controller to filter the aggregate current value and compare the filtered aggregate current value to a threshold, wherein the current controller is to send a throttle signal to the plurality of processing circuits when the filtered aggregate current value exceeds the threshold.

13. The device of claim 12, wherein each of the plurality of processing circuits is to independently throttle operations in response to the throttle signal.

14. The device of claim 13, wherein each of the plurality of processing circuits is to independently throttle operations in response to the throttle signal according to a configuration value stored in a configuration storage of the respective processing circuit.

15. The apparatus of claim 12, further comprising a plurality of integrated voltage regulators coupled with the plurality of processing circuits, wherein the plurality of integrated voltage regulators are to provide the plurality of digital current values to the summing circuit.

16. The apparatus of claim 12, wherein the current controller comprises:

a low pass filter to filter the total current value;

a digital comparator to compare the filtered total current value to the threshold value; and

a pulse lengthening circuit coupled to receive a comparison signal from the digital comparator and to output the throttling signal based at least in part on the comparison signal.

17. The apparatus of claim 16, wherein the pulse lengthening circuit is to maintain the throttling signal for a remaining duration of a throttling window after the filtered current value falls below the threshold.

18. The apparatus of claim 12, further comprising:

a plurality of current controllers, each current controller associated with one of the plurality of voltage regulators; and

a power controller coupled to the plurality of voltage regulators, wherein the power controller is to convert the filtered current values from each of the plurality of current controllers to power values, combine the power values into a summed power value, filter the summed power value, and send a second throttle signal to at least some of the plurality of processing circuits when the filtered summed power value exceeds a threshold power value.

19. A system, comprising:

a system on a chip (SoC), comprising:

a plurality of core devices and at least one graphics processing device, each of the plurality of core devices and the at least one graphics processing device comprising configuration register means for storing a dynamic current budget; and

a power control device coupled with the plurality of core devices and the at least one graphics processing device, the power control device comprising an interface device to receive current throttling hint information from a software entity regarding a workload to be executed on the SoC, the power control device further comprising a dynamic current sharing control device to generate the dynamic current budget for the plurality of core devices and the at least one graphics processing device based at least in part on the current throttling hint information; and

a memory device coupled with the SoC.

20. The system of claim 19, wherein the power control means comprises a plurality of second configuration register means for storing the current throttling hint information, and the dynamic current sharing control means is to determine solved current budgets for the plurality of core means and the at least one graphics processing means based on the current throttling hint information and one or more parameters of the SoC.

21. The system of claim 20, wherein the dynamic current sharing control means is to determine the dynamic current budget based on a solved current budget for the plurality of core devices and the at least one graphics processing device and a configured maximum current budget for each of the plurality of core devices and the at least one graphics processing device.

22. A method, comprising:

receiving, in a power controller of a processor, current throttling hints information about a workload from a software entity;

calculating a dynamic maximum current budget for each of a plurality of processing circuits of the processor based on the current throttling hints information and configured maximum current budget values for the plurality of processing circuits;

sending the dynamic maximum current budget to each of the plurality of processing circuits; and is

In response to determining that the current consumption level of the processor exceeds a threshold, send a throttling signal to the plurality of processing circuits to cause the plurality of processing circuits to throttle activities based on the dynamic maximum current budget.

23. The method of claim 22, further comprising:

receiving the current throttling prompt message in the power controller via an interface; and is

Storing the current throttling hint information in a set of configuration registers of the power controller.

24. The method of claim 22, further comprising determining a resolved throttle value for the plurality of processing circuits based on the current throttle hint information and die specific information.

25. The method of claim 24, further comprising calculating the dynamic maximum current budget for each of the plurality of processing circuits further based on solved throttle values for the plurality of processing circuits.

26. The method of claim 22, further comprising:

throttling a first processing circuit of the plurality of processing circuits in response to the throttling signal; and is

In response to the throttle signal, a second processing circuit of the plurality of processing circuits is enabled to execute unconstrained.

27. A computer readable storage medium comprising computer readable instructions which, when executed, implement a method as claimed in any one of claims 22 to 26.

Technical Field

Embodiments relate to power management of a processor.

Background

Advances in semiconductor processing and logic design have allowed for an increase in the amount of logic that may be present on an integrated circuit device. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or a complete system on individual integrated circuits. Furthermore, as the density of integrated circuits has increased, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies and their hardware requirements also contribute to increased energy consumption of computing devices. Indeed, some studies indicate that computing devices consume a significant percentage of the entire power supply for one country (e.g., the united states). As a result, there is a critical need for energy efficiency and conservation associated with integrated circuits. These requirements will follow from servers, desktop computers, notebooks, Ultrabooks^TMTablet device, mobile phone, processor and embedded deviceIn-line systems and the like have become more prevalent (from inclusion in typical computers, automobiles, and televisions to biotechnology) and have grown.

Drawings

FIG. 1 is a block diagram of a portion of a system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a processor according to an embodiment of the invention.

FIG. 3 is a block diagram of a multi-domain processor according to another embodiment of the invention.

FIG. 4 is an embodiment of a processor including multiple cores.

FIG. 5 is a block diagram of a micro-architecture of a processor core according to one embodiment of the invention.

FIG. 6 is a block diagram of a micro-architecture of a processor core according to another embodiment.

FIG. 7 is a block diagram of a micro-architecture of a processor core according to yet another embodiment.

FIG. 8 is a block diagram of a micro-architecture of a processor core according to another embodiment.

FIG. 9 is a block diagram of a processor according to another embodiment of the invention.

FIG. 10 is a block diagram of a representative SoC, according to an embodiment of the present invention.

FIG. 11 is a block diagram of another example SoC, according to an embodiment of the present invention.

FIG. 12 is a block diagram of an example system that can be used with embodiments.

FIG. 13 is a block diagram of another example system that may be used with embodiments.

FIG. 14 is a block diagram of a representative computer system.

FIG. 15 is a block diagram of a system according to an embodiment of the invention.

Fig. 16 is a block diagram illustrating an IP core development system used to fabricate integrated circuits to perform operations, according to an embodiment.

FIG. 17 is a block diagram of a computing system according to an embodiment of the invention.

FIG. 18 is a flow diagram of a method according to an embodiment of the invention.

FIG. 19 is a flow diagram of a method according to one embodiment of the invention.

Fig. 20 is a flow chart of a method according to another embodiment of the invention.

FIG. 21 is a block diagram of a processor according to an embodiment of the invention.

Fig. 22 is a block diagram of a control arrangement according to another embodiment of the invention.

FIG. 23 is a flow diagram of a method according to an embodiment of the invention.

Fig. 24 is a flow chart of a method according to another embodiment of the invention.

Detailed Description

In various embodiments, a processor is configured to dynamically determine an independently controllable maximum current consumption capability for each of a plurality of processing circuits of the processor. For example, the processor may be a multi-core processor or other system on chip (SoC) including various different processing circuits including general purpose processing cores, graphics processors, and so forth. With embodiments herein, the power controller may dynamically determine an independent current consumption limit for each processing circuit based at least in part on information received from a software entity (e.g., an operating system or other scheduler) or the application itself. This information may identify the relative priority or importance of the different processing circuits for a given workload, which may provide dynamic, independent, and controllable current consumption values on a per core (or other processing circuit) basis.

In this way, throttling of individual processing circuits may be performed independently when a power surge is encountered during operation, in order to have as limited an impact on the workload in execution as possible. In contrast, conventional processing circuit throttling occurs with a predefined amount of static throttling when a power surge occurs. Such a static arrangement is set to satisfy the entire spectrum of workload behavior and is not optimal for any given situation. Rather, with embodiments, by dynamically configuring the allowed current consumption of individual processing circuits, optimal throttling behavior may be achieved for any given workload in execution.

As a high level example, consider the first workload scenario, which is core-centric and has a smaller amount of graphics processing. Consider the second workload scenario, where cores are not heavily used and graphics processors are highly used. By means of appropriate prompting information provided by the software entity, a dynamic and controllable determination of the maximum current consumption level of these different processing circuits may be provided and implemented. Thus, for a first workload in which cores may be performing work that affects workload responsiveness, such cores may not be throttled to the extent that the graphics processor is throttled. Conversely, for the second workload case, where the graphics processor may be performing user-visible work, the throttling level to the core may be higher than for the graphics processor. In this way, different processing circuits may be throttled in different ways based on different workloads that may be executing.

By way of example, the software interface enables a software entity, such as runtime software, drivers, firmware, or other software entities, to provide dynamic programming of throttling information to optimize current sharing between different processing circuits of the processor. In this way, performance may be improved in current-constrained scenarios.

Although the following embodiments are described with reference to energy conservation and energy efficiency in a particular integrated circuit (e.g., in a computing platform or processor), other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from better energy efficiency and energy conservation. For example, the disclosed embodiments are not limited to any particular type of computer system. That is, the disclosed embodiments may be used in many different system types, ranging from server computers (e.g., tower servers, rack servers, blade servers, microservers, etc.), communication systems, storage systems, desktop computers of any configuration, laptops, notebooks, to tablet computers (including 2:1 tablet devices, tablet phones, etc.), and may also be used in other devices, such as handheld devices, systems on chip (SoC), and embedded applications. Some examples of handheld devices include cellular phones, such as smart phones, internet protocol devices, digital cameras, Personal Digital Assistants (PDAs), and handheld PCs. Embedded applications may generally include microcontrollers, Digital Signal Processors (DSPs), network computers (netpcs), set-top boxes, network hubs, Wide Area Network (WAN) switches, wearable devices, or any other system capable of performing the functions and operations taught below. Additionally, embodiments may be implemented in mobile terminals having standard voice functionality, such as mobile phones, smart phones, and tablet phones, and/or in non-mobile terminals without standard wireless voice functionality communication capabilities, such as many wearable devices, tablet devices, laptops, desktop computers, microservers, servers, and so forth. Additionally, the apparatus, methods, and systems described herein are not limited to physical computing devices, but may also relate to software optimization for energy conservation and efficiency. As will become readily apparent in the following description, embodiments of the methods, apparatus and systems described herein (whether in terms of hardware, firmware, software or a combination thereof) are critical to the "green technology" future, e.g., for power conservation and energy efficiency in products covering a large portion of the us economy.

Referring now to FIG. 1, shown is a block diagram of a portion of a system in accordance with an embodiment of the present invention. As shown in FIG. 1, the system 100 may include various components including a processor 110, the processor 110 being shown as a multi-core processor. The processor 110 may be coupled to the power supply 150 via an external voltage regulator 160, which voltage regulator 160 may perform a first voltage conversion to provide a main regulated voltage to the processor 110.

As can be seen, processor 110 may be a processor that includes multiple cores 120_a-120_nThe single die processor of (1). In addition, each core may be associated with an integrated voltage regulator (integrated volt)age regulator，IVR)125_a-125_nIn association, the integrated voltage regulator receives a main regulated voltage and generates an operating voltage to be provided to one or more agents of a processor associated with the IVR. Thus, an IVR implementation may be provided to allow fine-grained control of voltage and thus power and performance of each individual core. In this way, each core may operate at independent voltage and frequency, which enables great flexibility and provides a wide opportunity to balance power consumption with performance. In some embodiments, the use of multiple IVRs enables the grouping of components into separate power planes, such that power is regulated by the IVRs and supplied only to those components in the group. During power management, a given power plane of one IVR may be powered down or off when the processor is placed in some low power state, while another power plane of another IVR remains active or is fully powered.

Still referring to FIG. 1, additional components may be present within the processor, including an input/output interface 132, another interface 134, and an integrated memory controller 136. As can be seen, each of these components may be controlled by another integrated voltage regulator 125_xTo supply power. In one embodiment, the interface 132 may beA Quick Path Interconnect (QPI) Interconnect enables operations that provide point-to-point (PtP) links in a cache coherency protocol that includes multiple layers, including a physical layer, a link layer, and a protocol layer. Further, interface 134 may be via Peripheral Component Interconnect Express (PCIe)^TM) The protocol is used to communicate.

Also shown is a Power Control Unit (PCU) 138, which PCU 138 may include hardware, software, and/or firmware to perform power management operations with respect to processor 110. As can be seen, PCU 138 provides control information to external voltage regulator 160 via a digital interface to cause the voltage regulator to generate an appropriate regulated voltage. The PCU 138 also provides control information to the IVR 125 via another digital interface to control the generated operating voltage (or to cause the corresponding IVR to be disabled in a low power mode). In various embodiments, PCU 138 may include a variety of power management logic to perform hardware-based power management. Such power management may be fully processor controlled (e.g., controlled by various processor hardware and may be triggered by workload and/or power constraints, thermal constraints, or other processor constraints), and/or power management may be performed in response to an external source (e.g., a platform or managing power management sources or system software).

Further, while fig. 1 illustrates an implementation in which PCU 138 is a separate processing engine (which may be implemented as a microcontroller), it is to be understood that in some cases each core may include or be associated with a power control agent to independently control power consumption more autonomously in addition to or in place of a dedicated power controller. In some cases, a hierarchical power management architecture may be provided in which PCU 138 communicates with respective power management agents associated with each core 120.

One power management logic included in PCU 138 may be a dynamic current sharing control circuit configured to dynamically determine an independent maximum current consumption value for each core 120 and/or additional processing circuitry. As will be further described herein, this control circuit may provide a dynamically configurable maximum current consumption value to each core 120 to cause each core 120 to operate according to this constraint. As such, when PCU 138 identifies a condition that triggers a throttling event, a throttling signal may be sent to core 120. In turn, each core 120 may limit its operation to its dynamically identified maximum current consumption value. In this way, the different cores may operate in an asymmetric performance state, particularly when throttling events are identified, such that minimal impact on user-oriented workload occurs.

Although not shown for ease of illustration, it is to be understood that additional components may be present within the processor 110, such as additional control circuitry, as well as other components such as internal memory, such as one or more levels of a cache memory hierarchy, and so forth. Furthermore, although illustrated with an integrated voltage regulator in the implementation of fig. 1, embodiments are not so limited.

Note that the power management techniques described herein may be independent of and complementary to operating system-based (OS) power management (OSPM) mechanisms. According to one example OSPM technique, a processor may operate in various performance states or levels, so-called P-states (i.e., from P0 to PN). In general, the P1 performance state may correspond to the highest guaranteed performance state that the OS may request. Embodiments described herein may enable dynamic changes to the guaranteed frequency of P1 performance states based on a variety of inputs and processor operating parameters. In addition to this P1 state, the OS may request a higher performance state, the P0 state. This P0 state may thus be an opportunistic mode or a reinforced mode state where the processor hardware may configure the processor, or at least some portion thereof, to operate above the guaranteed frequency when power and/or thermal budgets are available. In many implementations, the processor may include a number of so-called bin frequencies (bin frequencies) above the P1 guaranteed maximum frequency that exceed the maximum peak frequency to a particular processor, which are fused or otherwise written into the processor during manufacturing. Further, according to one OSPM mechanism, the processor may operate in various power states or levels. With respect to power states, the OSPM mechanism may specify different power consumption states, commonly referred to as C-states, C0, C1 through Cn states. When a core is active, it runs in the C0 state, and when the core is idle, it may be placed in a core low power state, also referred to as a core non-zero C state (e.g., C1-C6 states), where each C state is at a lower power consumption level (so that C6 is a deeper low power state than C1, and so on).

It is to be understood that many different types of power management techniques may be used alone or in combination in different embodiments. As a representative example, the power controller may control the processor to scale by some form of dynamic voltage frequency (dynamic voltage fre)DVFS) in which the operating voltage and/or operating frequency of one or more cores or other processor logic may be dynamically controlled to reduce power consumption in some situations. In one example, an enhanced Intel SpeedStep available from Intel corporation of Santa Clara, Calif. may be utilized^TMTechniques to perform DVFS to provide optimal performance at the lowest power consumption level. In another example, an Intel TurboBoost may be utilized^TMTechniques to perform DVFS to enable one or more cores or other compute engines to operate above a guaranteed operating frequency based on conditions (e.g., workload and availability).

Another power management technique that may be used in some examples is dynamic swapping of workloads between different compute engines. For example, a processor may include asymmetric cores or other processing engines that operate at different power consumption levels, such that in a power constrained scenario, one or more workloads may be dynamically switched to execute on a lower power core or other compute engine. Another exemplary power management technique is Hardware Duty Cycle (HDC), which may cause cores and/or other computing engines to be periodically enabled and disabled according to a duty cycle, such that one or more cores may be set to inactive during an inactive period of the duty cycle and set to active during an active period of the duty cycle. While described with these particular examples, it is to be understood that many other power management techniques may be used in particular embodiments.

Embodiments may be implemented in processors for various markets, including server processors, desktop processors, mobile processors, and so forth. Referring now to FIG. 2, shown is a block diagram of a processor in accordance with an embodiment of the present invention. As shown in FIG. 2, processor 200 may include multiple cores 210_a-210_nThe multi-core processor of (1). In one embodiment, each such core may be an independent power domain and may be configured to enter and exit the active state and/or the maximum performance state based on workload. Various kinds ofThe cores may be coupled via an interconnect 215 to a system agent 220 that includes various components. As can be seen, system agent 220 may include a shared cache 230, where shared cache 230 may be a last level cache. Further, the system agent may include an integrated memory controller 240 to communicate with a system memory (not shown in FIG. 2), e.g., via a memory bus. The system agent 220 also includes various interfaces 250 and a power control unit 255, the power control unit 255 may include logic to perform the power management techniques described herein. In the illustrated embodiment, power control unit 255 includes a dynamic current share control circuit 258, which dynamic current share control circuit 258 may dynamically determine a dynamic current consumption value for each core 210 based at least in part on hints provided by software. Dynamic current sharing control circuitry 258 may communicate such dynamic current consumption values to core 210 for storage and internal use thereof to independently control its current consumption, particularly when a throttling event is identified.

Further, through interfaces 250a-250n, connections may be made to various off-chip components, such as peripherals, mass storage devices, and the like. Although shown with this particular implementation in the embodiment of fig. 2, the scope of the present invention is not limited in this regard.

Referring now to FIG. 3, shown is a block diagram of a multi-domain processor in accordance with another embodiment of the present invention. As shown in the embodiment of fig. 3, processor 300 includes multiple domains. In particular, the core domain 310 may include a plurality of cores 310₀-310_nThe graphics domain 320 may include one or more graphics engines, and the system agent domain 350 may further exist. In some embodiments, the system agent domain 350 may execute at a frequency independent of the core domain and may remain powered on at all times to handle power control events and power management, such that the domains 310 and 320 may be controlled to dynamically enter and exit high and low power states. Each of domains 310 and 320 may operate at different voltages and/or powers. Note that while only three domains are shown, it is to be understood that the scope of the present invention is not limited in this respect, and that additional domains may be present in other embodiments. E.g. a plurality ofCore domains may exist, each core domain including at least one core.

Generally, each core 310 may include a low level cache in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a Last Level Cache (LLC) 340₀-340_nA shared cache memory formed by a plurality of units. In various embodiments, LLC 340 may be shared between the cores and the graphics engine, as well as various media processing circuits. As can be seen, ring interconnect 330 thus couples the cores together and provides an interconnect between the cores, graphics domain 320, and system agent circuit 350. In one embodiment, interconnect 330 may be part of a core domain. However, in other embodiments, the ring interconnect may be of its own domain.

It can also be seen that the system agent field 350 can include a display controller 352, and that the display controller 352 can provide control of and interface to an associated display. It can also be seen that the system agent domain 350 can include a power control unit 355, which power control unit 355 can include logic to perform the power management techniques described herein. In the illustrated embodiment, power control unit 355 includes a dynamic current sharing control circuit 359 that independently determines a maximum current consumption level for each core 310 and graphics engine 320 based at least in part on hints information provided by software, as described herein.

As can also be seen in FIG. 3, processor 300 may also include an Integrated Memory Controller (IMC) 370, which IMC 370 may provide an interface to system memory such as Dynamic Random Access Memory (DRAM). Multiple interfaces 380₀-380_nMay be present to enable interconnections between the processor and other circuitry. For example, in one embodiment, at least one Direct Media Interface (DMI) interface may be provided, along with one or more PCIe interfaces^TMAn interface. In addition, to provide communication between other agents, such as additional processors or other circuitry, may also be providedOne or more QPI interfaces are provided. Although shown at this high level in the embodiment of fig. 3, understand the scope of the present invention is not limited in this regard.

Referring to FIG. 4, an embodiment of a processor including multiple cores is illustrated. Processor 400 includes any processor or processing device, such as a microprocessor, an embedded processor, a Digital Signal Processor (DSP), a network processor, a handheld processor, an application processor, a coprocessor, a system on a chip (SoC), or other device for executing code. Processor 400, in one embodiment, includes at least two cores, cores 401 and 402, which may include asymmetric cores or symmetric cores (illustrated embodiment). However, processor 400 may include any number of processing elements that may be symmetric or asymmetric.

In one embodiment, a processing element refers to hardware or logic for supporting a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a processing unit, a context unit, a logical processor, a hardware thread, a core, and/or any other element capable of maintaining a state (e.g., an execution state or an architectural state) for a processor. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor generally refers to an integrated circuit that may include any number of other processing elements, such as cores or hardware threads.

A core often refers to logic located on an integrated circuit that is capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread generally refers to any logic located on an integrated circuit that is capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. It can be seen that the boundaries between the nomenclature of hardware threads and cores can overlap when certain resources are shared and others are dedicated to the architectural state. Often, however, the cores and hardware threads are viewed by the operating system as separate logical processors, where the operating system is able to schedule operations on each logical processor separately.

As shown in fig. 4, physical processor 400 includes two cores, core 401 and core 402. Here, cores 401 and 402 are considered symmetric cores, i.e., cores having the same configuration, functional units, and/or logic. In another embodiment, core 401 comprises an out-of-order processor core and core 402 comprises an in-order processor core. However, cores 401 and 402 may be individually selected from any type of core, such as a native core, a software managed core, a core adapted to execute a native Instruction Set Architecture (ISA), a core adapted to execute a translated ISA, a co-designed core, or other known cores. Still further, the functional units illustrated in core 401 are described in more detail below, as the units in core 402 operate in a similar manner.

As shown, core 401 includes two hardware threads 401a and 401b, which may also be referred to as hardware thread slots 401a and 401 b. Thus, a software entity (e.g., an operating system) may, in one embodiment, view processor 400 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As mentioned above, a first thread may be associated with architecture state registers 401a, a second thread may be associated with architecture state registers 401b, a third thread may be associated with architecture state registers 402a, and a fourth thread may be associated with architecture state registers 402 b. Here, each of the architecture state registers (401a, 401b, 402a, and 402b) may be referred to as a processing element, a thread slot, or a thread unit, as described above. As shown, architecture state register 401a is replicated in architecture state register 401b, and thus is able to store individual architecture states/contexts for logical processor 401a and logical processor 401 b. Other smaller resources, such as instruction pointers and rename logic in allocator and renamer block 430, may also be replicated in core 401 for threads 401a and 401 b. Some resources, such as reorder buffers in reorder/retirement unit 435, ILTB 420, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page table base register(s), low level data cache and data TLB 415, execution unit(s) 440, and portions of out-of-order unit 435, may be fully shared.

Processor 400 often includes other resources that may be fully shared, shared through partitioning, or dedicated to processing elements. In fig. 4, an embodiment of a purely exemplary processor with illustrative logical units/resources of the processor is illustrated. Note that a processor may include or omit any of these functional units, as well as include any other known functional units, logic, or firmware not depicted. As shown, core 401 includes a simplified, representative out-of-order (OOO) processor core. In-order processors may be utilized in different embodiments. The OOO core includes a branch target buffer 420 to predict branches to be executed/taken, and an instruction-translation buffer (I-TLB) 420 to store address translation entries for instructions.

Core 401 also includes a decode module 425 coupled to fetch unit 420 to decode fetched elements. The fetch logic, in one embodiment, includes individual sequencers associated with thread slots 401a, 401b, respectively. Typically core 401 is associated with a first ISA that defines/specifies instructions executable on processor 400. Often, machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode) that references/specifies an instruction or operation to be performed. Decode module 425 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions through the pipeline for processing as defined by the first ISA. For example, decoder 425, in one embodiment, includes logic designed or adapted to identify a particular instruction, such as a transactional instruction. As a result of the recognition by decoder 425, architecture or core 401 takes certain predefined actions to perform the task associated with the appropriate instruction. It is important to note that: any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of these instructions may be new or old instructions.

In one example, allocator and renamer block 430 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 401a and 401b may be capable of out-of-order execution, where allocator and renamer block 430 also reserves other resources, such as a reorder buffer to track instruction results. Unit 430 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 400. Reorder/retirement unit 435 includes components (e.g., the reorder buffers, load buffers, and store buffers mentioned above) to support out-of-order execution and later in-order retirement of instructions that are executed out-of-order.

The scheduler and execution unit block(s) 440, in one embodiment, include a scheduler unit to schedule instructions/operations on the execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has a floating point execution unit available. A register file associated with the execution unit is also included to store information instruction processing results. Exemplary execution units include floating point execution units, integer execution units, jump execution units, load execution units, store execution units, and other known execution units.

A lower level data cache and data translation buffer (D-TLB) 450 is coupled to execution unit(s) 440. The data cache is also used to store recently used/operated on elements (e.g., data operands), which may be held in a memory coherency state. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break up physical memory into multiple virtual pages.

Here, cores 401 and 402 share access to a higher level or more distant cache 410, which is used to cache recently fetched elements. Note that higher level or farther refers to the cache level increasing or becoming farther away from the execution unit(s). In one embodiment, higher level cache 410 is a last level data cache, the last cache in a memory hierarchy on processor 400, such as a second or third level data cache. However, higher level cache 410 is not so limited, as it may be associated with or include an instruction cache. Instead, a trace cache, a type of instruction cache, may be coupled after decoder 425 to store recently decoded traces.

In the depicted configuration, processor 400 also includes a bus interface module 405 and a power controller 460, which may perform power management in accordance with embodiments of the present invention. In this scenario, bus interface 405 is used to communicate with devices external to processor 400 (e.g., system memory and other components).

Memory controller 470 may interface with other devices such as one or many memories. In an example, bus interface 405 includes a ring interconnect having a memory controller for interfacing with a memory and a graphics controller for interfacing with a graphics processor. In an SoC environment, even more devices (e.g., network interfaces, coprocessors, memory, graphics processors, and any other known computer device/interface) may be integrated on a single die or integrated circuit to provide a small form factor with high functionality and low power consumption.

Referring now to FIG. 5, shown is a block diagram of a micro-architecture of a processor core in accordance with one embodiment of the present invention. As shown in fig. 5, processor core 500 may be a multi-stage pipelined out-of-order processor. Core 500 may operate at various voltages based on a received operating voltage, which may be received from an integrated voltage regulator or an external voltage regulator.

As can be seen in FIG. 5, core 500 includes a front end unit 510, front end unit 510 operable to fetch instructions to be executed and prepare them for later use in the processor pipeline. For example, front end unit 510 may include fetch unit 501, instruction cache 503, and instruction decoder 505. In some implementations, front end unit 510 may also include trace caches, along with microcode storage and micro-operation storage. The fetch unit 501 may fetch macro-instructions (e.g., fetched from memory or instruction cache 503) and feed them to the instruction decoder 505 to be decoded into primitives (i.e., micro-operations for execution by the processor).

Coupled between the front end units 510 and the execution units 520 is an out-of-order (OOO) engine 515, which OOO engine 515 may be used to receive micro-instructions and prepare them for execution. More specifically, OOO engine 515 may include various buffers for reordering microinstruction flow and allocating the various resources needed for execution and for providing renaming of logical registers to storage locations within various register files (such as register file 530 and extended register file 535). Register file 530 may include separate register files for integer and floating point operations. The extended register file 535 may provide storage for vector size units, such as 256 or 512 bits per register. A set of Machine Specific Registers (MSRs) 538 may also be present and accessible to various logic within core 500 (as well as external to the core) for configuration, control, and additional operations.

Various resources may be present in execution units 520, including, for example, various integer, floating point, and Single Instruction Multiple Data (SIMD) logic units, as well as other specialized hardware. For example, such execution units may include one or more Arithmetic Logic Units (ALUs) 522 and one or more vector execution units 524, among other such execution units.

The results from the execution units may be provided to retirement logic, i.e., reorder buffer (ROB) 540. More specifically, ROB 540 may include various arrays and logic to receive information associated with instructions being executed. This information is then examined by ROB 540 to determine whether the instruction can be validly retired and the resulting data can be committed to the architectural state of the processor, or whether one or more exceptions occurred that prevent proper retirement of the instruction. Of course, ROB 540 may handle other operations associated with retirement.

As shown in fig. 5, ROB 540 is coupled to a cache 550, and cache 550 may be a lower level cache (e.g., an L1 cache) in one embodiment, although the scope of the invention is not limited in this respect. Additionally, execution units 520 may be directly coupled to cache 550. From cache 550, data communication may occur with higher level caches, system memory, and so forth. While shown with this high level in the embodiment of fig. 5, understand the scope of the present invention is not limited in this regard. For example, although the implementation of FIG. 5 is with respect to a network such asAn out-of-order machine such as the x86 Instruction Set Architecture (ISA), although the scope of the present invention is not limited in this respect. That is, other embodiments may be implemented in an in-order processor, a Reduced Instruction Set Computing (RISC) processor such as an ARM-based processor, or a processor of another type of ISA that may emulate instructions and operations of a different ISA via an emulation engine and associated logic circuits.

Referring now to FIG. 6, shown is a block diagram of a micro-architecture of a processor core in accordance with another embodiment. In the embodiment of FIG. 6, core 600 may be a low power core of a different microarchitecture, e.g., based onAtom^TMHaving a relatively limited pipeline depth designed to reduce power consumption. As can be seen, core 600 includes an instruction cache 610 coupled to provide instructions to an instruction decoder 615. Branch predictor 605 may be coupled to instruction cache 610. Note that instruction cache 610 may also be coupled to another level of cache memory, such as an L2 cache (not shown in fig. 6 for ease of illustration). In turn, instruction decoder 615 provides decoded instructions to issue queue 620 for storage and delivery to a given executionA row pipeline. The microcode ROM 618 is coupled to an instruction decoder 615.

The floating point pipeline 630 includes a floating point register file 632, which floating point register file 632 may include a plurality of architectural registers of a given bit width, such as 128, 256, or 512 bits. The pipeline 630 includes a floating point scheduler 634 to schedule instructions for execution on one of the pipeline's multiple execution units. In the illustrated embodiment, such execution units include an ALU 635, a scrambling unit 636, and a floating-point adder 638. In turn, the results generated in these execution units may be provided back to the buffers and/or registers of register file 632. It is of course to be understood that while shown with these several example execution units, in another embodiment there may be additional or different floating point execution units.

An integer pipeline 640 may also be provided. In the illustrated embodiment, pipeline 640 includes an integer register file 642, which integer register file 642 may include a plurality of architectural registers of a given bit width, such as 128 or 256 bits. Pipeline 640 includes an integer scheduler 644 to schedule instructions for execution on one of the multiple execution units of the pipeline. In the illustrated embodiment, such execution units include ALU 645, shifter unit 646, and jump execution unit 648. In turn, results generated in these execution units may be provided back to the buffers and/or registers of register file 642. It is, of course, to be understood that while shown with these several example execution units, in another embodiment there may be additional or different integer execution units.

The memory execution scheduler 650 may schedule memory operations for execution in an address generation unit 652, which address generation unit 652 is also coupled to the TLB 654. It can be seen that these structures may be coupled to a data cache 660, which data cache 660 may be an L0 and/or L1 data cache, which L0 and/or L1 data caches are in turn coupled to additional levels of a cache memory hierarchy, including an L2 cache memory.

To provide support for out-of-order execution, allocator/renamer 670 may be provided in addition to reorder buffer 680, reorder buffer 680 configured to reorder instructions executed out-of-order for in-order retirement. While shown with this particular pipeline architecture in the illustration of fig. 6, it is to be understood that many variations and alternatives are possible.

Note that in a processor having asymmetric cores (e.g., according to the microarchitecture of fig. 5 and 6), workloads may be dynamically swapped between cores for power management reasons, as these cores, although of different pipeline design and depth, may have the same or related ISA. Such dynamic core swapping may be performed in a manner that is transparent to the user application (and possibly transparent to the kernel as well).

Referring to FIG. 7, a block diagram of a micro-architecture of a processor core is shown, according to yet another embodiment. As shown in FIG. 7, core 700 may include a multi-stage ordered pipeline to execute at very low power consumption levels. As one such example, the processor 700 may have a microarchitecture designed in accordance with ARM Cortex A53, available from ARM holdings, Inc. of Senyvale, Calif. In one implementation, an 8-stage pipeline may be provided that is configured to execute both 32-bit and 64-bit codes. Core 700 includes a fetch unit 710, which fetch unit 710 is configured to fetch instructions and provide them to a decode unit 715, where decode unit 715 may decode instructions (e.g., macro-instructions of a given ISA, such as ARMv8 ISA). Also note that a queue 730 may be coupled to the decode unit 715 to store decoded instructions. The decoded instruction is provided to issue logic 725, where at issue logic 725 the decoded instruction may be issued to a given one of the plurality of execution units.

With further reference to FIG. 7, issue logic 725 may issue instructions to one of a plurality of execution units. In the illustrated embodiment, these execution units include an integer unit 735, a multiplication unit 740, a floating point/vector unit 750, a dual issue unit 760, and a load/store unit 770. The results of these different execution units may be provided to a write-back unit 780. It is to be understood that while a single write-back unit is shown for ease of illustration, in some implementations, separate write-back units may be associated with each execution unit. Further, it is to be understood that while each of the units and logic shown in FIG. 7 is represented at a high level, particular implementations may include more or different structures. Processors designed with one or more cores with pipelines (as shown in FIG. 7) may be implemented in many different end products, extending from mobile devices to server systems.

Referring to FIG. 8, a block diagram of a micro-architecture of a processor core is shown, according to another embodiment. As shown in fig. 8, core 800 may include a multi-stage multi-issue out-of-order pipeline to execute at a very high performance level (which may occur at a higher power consumption level than core 700 of fig. 7). As one such example, the processor 800 may have a microarchitecture designed in accordance with ARM Cortex A57. In one implementation, a 15 (or more) stage pipeline may be provided that is configured to execute both 32-bit and 64-bit code. Further, the pipeline may provide 3 wide (or wider) and 3 issue (or more) operations. Core 800 includes fetch unit 810, fetch unit 810 configured to fetch instructions and provide them to decoder/renamer/reprimator 815, decoder/renamer/reprimator 815 may decode instructions (e.g., macro instructions of the ARMv8 instruction set architecture), rename register references within the instructions, and (eventually) reprimate the instructions to selected execution units. The decoded instructions may be stored in a queue 825. Note that while a single queue structure is shown in FIG. 8 for ease of illustration, it is to be understood that separate queues may be provided for each of a plurality of different types of execution units.

Also shown in FIG. 8 is issue logic 830, wherein decoded instructions stored in the queue 825 may be issued from the issue logic 830 to selected execution units. The issue logic 830 may also be implemented in particular embodiments, with separate issue logic for each of a plurality of different types of execution units to which the issue logic 830 is coupled.

The decoded instruction may be issued to a given one of the plurality of execution units. In the illustrated embodiment, these execution units include one or more integer units 835, multiplication units 840, floating point/vector units 850, branch units 860, and load/store units 870. In an embodiment, floating point/vector unit 850 may be configured to handle 128 or 256 bits of SIMD or vector data. In addition, floating point/vector execution unit 850 may perform IEEE-754 double precision floating point operations. The results of these different execution units may be provided to a write back unit 880. Note that in some implementations, separate write-back units may be associated with each of the execution units. Further, it is to be understood that while each of the units and logic shown in FIG. 8 is represented at a high level, particular implementations may include more or different structures.

Note that in processors with asymmetric cores (e.g., according to the microarchitecture of fig. 7 and 8), workloads may be dynamically swapped for power management reasons, as these cores, although of different pipeline design and depth, may have the same or related ISA. Such dynamic core swapping may be performed in a manner that is transparent to the user application (and possibly transparent to the kernel as well).

Processors designed with one or more cores with pipelines (as shown in any one or more of fig. 5-8) may be implemented in many different end products, extending from mobile devices to server systems. Referring now to FIG. 9, shown is a block diagram of a processor in accordance with another embodiment of the present invention. In the embodiment of fig. 9, processor 900 may be a SoC that includes multiple domains, each of which may be controlled to operate at independent operating voltages and operating frequencies. As a specific illustrative example, processor 900 may be available from Intel corporation based onArchitecture Core^TMSuch as i3, i5, i7 or another such processor. However, other low power processors, such as those available from ultramicro semiconductor corporation (AMD) of Senneville, Calif., ARM-based designs from ARM Consortium, Inc. or their licensees, or MIPS technologies, Inc. of Senneville, Calif., or their licenseesThe MIPS-based design of the adopter may instead exist in other embodiments, such as an apple a7 processor, a highpass dragon processor, or a texas instruments OMAP processor. Such an SoC may be used in low power systems, such as smart phones, tablet computers, Ultrabook computers^TMA computer, or other portable computing device or connected device.

In the high-level view shown in FIG. 9, processor 900 includes multiple core units 910₀-910_n. Each core unit may include one or more processor cores, one or more cache memories, and other circuitry. Each core unit 910 may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions), the MIPS instruction set, the ARM instruction set (with optional additional extensions such as NEON)), or other instruction sets, or combinations thereof. Note that some of the core units may be heterogeneous resources (e.g., of different designs). Further, each such core may be coupled to a cache memory (not shown), which in one embodiment may be a shared level (L2) cache memory. Non-volatile storage 930 may be used to store various programs and other data. For example, such a storage device may be used to store at least some portions of microcode, boot information such as a BIOS, other system software, and so forth.

Each core unit 910 may also include an interface (e.g., a bus interface unit) to enable interconnection to additional circuitry of the processor. In an embodiment, each core unit 910 is coupled to a coherent fabric that may act as a primary cache coherent on-chip interconnect, which in turn is coupled to a memory controller 935. Further, the memory controller 935 controls communication with a memory (not shown in fig. 9 for ease of illustration) such as a DRAM.

In addition to core units, there are additional processing engines within the processor, including at least one graphics unit 920, where the graphics unit 920 may include one or more Graphics Processing Units (GPUs) to perform graphics processing and possibly general purpose operations on the graphics processor (so-called GPGPU operations). Further, at least one image signal processor 925 may be present. The signal processor 925 may be configured to process incoming image data received from one or more capture devices internal to the SoC or off-chip.

Other accelerators may also be present. In the illustration of fig. 9, video encoder 950 may perform encoding operations including encoding and decoding of video information, such as providing hardware acceleration support for high-definition video content. A display controller 955 may also be provided to accelerate display operations, including providing support for internal and external displays of the system. In addition, a security processor 945 may be present to perform security operations such as secure boot operations, various cryptographic operations, and so on.

Each cell may have its power consumption controlled via a power manager 940, which power manager 940 may include control logic to perform the various power management techniques described herein.

In some embodiments, SoC 900 may also include a non-coherent architecture coupled to a coherent architecture to which various peripherals may be coupled. One or more of the interfaces 960a-960d may enable communication with one or more off-chip devices. Such communication may be via various communication protocols, such as PCIe^TM、GPIO、USB、I²C. UART, MIPI, SDIO, DDR, SPI, HDMI, and other types of communication protocols. Although shown at this high level in the embodiment of fig. 9, understand the scope of the present invention is not limited in this regard.

Referring now to fig. 10, a block diagram of a representative SoC is shown. In the illustrated embodiment, SoC1000 may be a multi-core SoC configured for low-power operation to be optimized for incorporation into a smartphone or other low-power device (such as a tablet or other portable computing device). As an example, SoC1000 may be implemented with asymmetric or different types of cores, such as a combination of higher power and/or low power cores, such as an out-of-order core and an in-order core. In various embodiments, these cores may be based onArchitecture^TMCore design or ARM architecture design. In still other embodiments, the same or different types of data may be implemented in a given SoCAnd ARM cores.

As can be seen in FIG. 10, SoC1000 includes a core having a plurality of first cores 1012₀-1012₃The first core domain 1010. In an example, the cores may be low power cores such as ordered cores. In one embodiment, these first cores may be implemented as ARM Cortex a53 cores. In turn, these cores are coupled to cache memories 1015 of the core domain 1010. Further, the SoC1000 includes a second core domain 1020. In the illustration of fig. 10, the second core domain 1020 has a plurality of second cores 1022₀-1022₃. In an example, the cores may be cores that consume more power than the first core 1012. In an embodiment, the second core may be an out-of-order core, which may be implemented as an ARM Cortex A57 core. In turn, these cores are coupled to a cache memory 1025 of the core domain 1020. Note that while the example shown in fig. 10 includes 4 cores in each domain, it is to be understood that in other examples more or fewer cores may be present in a given domain.

With further reference to fig. 10, a graphics domain 1030 is also provided, the graphics domain 1030 may include one or more Graphics Processing Units (GPUs) configured to independently execute graphics workloads (e.g., provided by one or more cores of the core domains 1010 and 1020). As an example, in addition to providing graphics and display rendering operations, GPU domain 1030 may also be used to provide display support for various screen sizes.

As can be seen, the various domains are coupled to a coherent interconnect 1040, which coherent interconnect 1040 may be a cache coherent interconnect architecture in an embodiment, which is in turn coupled to an integrated memory controller 1050. In some examples, coherent interconnect 1040 may include a shared cache memory, such as an L3 cache. In an embodiment, memory controller 1050 may be a direct memory controller to provide multiple channels of communication with off-chip memory, such as multiple channels of DRAM (not shown in FIG. 10 for ease of illustration).

In different examples, the number of core domains may vary. For example, for a low power SoC suitable for inclusion into a mobile computing device, a limited number of core domains such as shown in fig. 10 may exist. Further, in such low power socs, the core domain 1020 including higher power cores may have a smaller number of such cores. For example, in one implementation, two cores 1022 may be provided to enable operation at reduced power consumption levels. In addition, different core domains may also be coupled to the interrupt controller to enable dynamic swapping of workloads between different domains.

In still other embodiments, a greater number of core domains and additional optional IP logic may be present, as the SoC may be scaled to higher performance (and power) levels for inclusion into other computing devices (e.g., desktops, servers, high performance computing systems, base stations, etc.). As one such example, 4 core domains may be provided, each with a given number of out-of-order cores. Furthermore, in addition to optional GPU support (which may take the form of a GPGPU as an example), one or more accelerators may also be provided to provide optimized hardware support for specific functions (e.g., web services, network processing, switching, etc.). Furthermore, input/output interfaces may also be present to couple such accelerators to off-chip components.

Referring now to fig. 11, shown is a block diagram of another example SoC. In the embodiment of fig. 11, SoC 1100 may include various circuitry to enable high performance for multimedia applications, communications, and other functions. As such, SoC 1100 is suitable for incorporation into a wide variety of portable and other devices, such as smartphones, tablet computers, smart TVs, and the like. In the illustrated example, the SoC 1100 includes a Central Processor Unit (CPU) field 1110. In an embodiment, multiple individual processor cores may be present in the CPU domain 1110. As one example, CPU domain 1110 may be a four-core processor with 4 multithreaded cores. Such processors may be homogeneous or heterogeneous processors, such as a mix of low power and high power processor cores.

In turn, a GPU domain 1120 is provided to perform high-level graphics processing in one or more GPUs to handle graphics and compute APIs. In addition to high-level computations that may occur during execution of multimedia instructions, the DSP unit 1130 may also provide one or more low-power DSPs to handle low-power multimedia applications, such as music playback, audio/video, and so forth. Further, the communication unit 1140 may include various components to provide connectivity via various wireless protocols, e.g., cellular communication (including 3G/4G LTE), such as Bluetooth^TMSuch as wireless local area protocol, IEEE 802.11, etc.

In addition, multimedia processor 1150 may be used to perform capture and playback of high-definition video and audio content, including processing of user gestures. The sensor unit 1160 may include a plurality of sensors and/or sensor controllers to interface to the various off-chip sensors present in a given platform. The image signal processor 1170 may have one or more separate ISPs to perform image processing on captured content from one or more cameras of the platform, including still cameras and video cameras.

The display processor 1180 may provide support for connection to a high definition display of a given pixel density, including the ability to wirelessly transmit content for playback on such a display. In addition, location unit 1190 may include a GPS receiver with support for multiple GPS constellations to provide highly accurate positioning information obtained with such a GPS receiver to applications. It is to be understood that while shown with this particular set of components in the example of fig. 11, many variations and alternatives are possible.

Referring now to FIG. 12, shown is a block diagram of an example system that can be used with an embodiment. It can be seen that system 1200 can be a smart phone or other wireless communicator. The baseband processor 1205 is configured to perform various signal processing with respect to communication signals to be transmitted from or received by the system. Further, baseband processor 1205 is coupled to application processor 1210, and application processor 1210 may be the main CPU of the system to execute the OS and other system software, as well as user applications such as many well-known social media and multimedia apps. Application processor 1210 may also be configured to perform various other computing operations for the device and to perform the power management techniques described herein.

In turn, the applications processor 1210 may be coupled to a user interface/display 1220, such as a touch screen display. Further, applications processor 1210 may be coupled to a memory system that includes non-volatile memory (i.e., flash memory 1230) and system memory (i.e., Dynamic Random Access Memory (DRAM) 1235). It is also seen that application processor 1210 is further coupled to a capture device 1240, such as one or more image capture devices that can record video and/or still images.

Still referring to fig. 12, a Universal Integrated Circuit Card (UICC) 1240 is also coupled to the application processor 1210, the UICC 1240 including a subscriber identity module and possibly a secure storage and a cryptographic processor. System 1200 may also include a security processor 1250, where security processor 1250 may be coupled to application processor 1210. A plurality of sensors 1225 may be coupled to the application processor 1210 to enable input of various sensed information, such as accelerometers and other environmental information. The audio output device 1295 can provide an interface to output sound, such as in the form of voice communications, played or streaming audio data, and so forth.

As also illustrated, a Near Field Communication (NFC) contactless interface 1260 is provided that communicates in the NFC near field via an NFC antenna 1265. Although separate antennas are shown in fig. 12, it is to be understood that in some implementations, one antenna or different sets of antennas may be provided to enable various wireless functions.

PMIC 1215 is coupled to application processor 1210 to perform platform-level power management. To do so, PMIC 1215 may issue power management requests to application processor 1210 to enter certain low power states as needed. Further, based on platform constraints, PMIC 1215 may also control the power levels of other components of system 1200.

To enable communications to be sent and received, various circuitry may be coupled between the baseband processor 1205 and the antenna 1290. Specifically, a Radio Frequency (RF) transceiver 1270 and a Wireless Local Area Network (WLAN) transceiver 1275 may be present. In general, RF transceiver 1270 may be used to receive and transmit wireless data and calls according to a given wireless communication protocol (e.g., a 3G or 4G wireless communication protocol), such as according to Code Division Multiple Access (CDMA), global system for mobile communication (GSM), Long Term Evolution (LTE), or other protocols. Further, a GPS sensor 1280 may be present. Other wireless communications may also be provided, such as reception or transmission of radio signals (e.g., AM/FM) and other signals. Local wireless communication may also be achieved via WLAN transceiver 1275.

Referring now to FIG. 13, shown is a block diagram of another example system that may be used with an embodiment. In the illustration of fig. 13, system 1300 may be a mobile low-power system, such as a tablet computer, a 2:1 tablet device, a tablet phone, or other convertible or stand-alone tablet system. As shown, SoC 1310 is present and may be configured to operate as an application processor for the device and perform the power management techniques described herein.

Various devices may be coupled to SoC 1310. In the illustrated illustration, the memory subsystem includes flash memory 1340 and DRAM 1345 coupled to SoC 1310. Further, a touch panel 1320 is coupled to the SoC 1310 to provide display capabilities and user input via touch, including providing a virtual keyboard on the display of the touch panel 1320. To provide wired network connectivity, the SoC 1310 is coupled to an ethernet interface 1330. A peripheral hub (peripheral hub)1325 is coupled to the SoC 1310 to enable interfacing with various peripheral devices, such as may be coupled to the system 1300 by any of various ports or other connectors.

In addition to internal power management circuitry and functions within SoC 1310, PMIC 1380 is also coupled to SoC 1310 to provide platform-based power management, e.g., based on whether the system is powered by battery 1390 or AC power via AC adapter 1395. In addition to this power supply based power management, PMIC 1380 may also perform platform power management activities based on environmental and usage conditions. Further, PMIC 1380 may communicate control and status information to SoC 1310 to cause various power management actions within SoC 1310.

Still referring to fig. 13, to provide wireless capability, a WLAN unit 1350 is coupled to SoC 1310 and, in turn, to an antenna 1355. In various implementations, WLAN unit 1350 may provide communications according to one or more wireless protocols.

As also illustrated, a plurality of sensors 1360 may be coupled to the SoC 1310. These sensors may include various accelerometers, environmental and other sensors, including user gesture sensors. Finally, an audio codec 1365 is coupled to the SoC 1310 to provide an interface to an audio output device 1370. It will of course be understood that while shown in fig. 13 in this particular implementation, many variations and alternatives are possible.

Referring now to FIG. 14, a diagram such as a notebook, Ultrabook is shown^TMOr other small form factor systems. The processor 1410, in one embodiment, includes a microprocessor, multi-core processor, multi-threaded processor, ultra-low voltage processor, embedded processor, or other known processing element. In the illustrated implementation, the processor 1410 acts as a main processing unit and central hub to communicate with many of the various components of the system 1400. As one example, processor 1400 is implemented as a SoC.

The processor 1410, in one embodiment, communicates with a system memory 1415. As an illustrative example, system memory 1415 is implemented via multiple memory devices or modules to provide a given amount of system memory.

To provide persistent storage for information such as data, applications, one or more operating systems, etc., a mass storage device 1420 may also be coupled to the processor 1410. In various embodiments, to enable thinner and lighter system designs and to improve system responsiveness, this mass storage may be implemented via the SSD or may be implemented primarily with a Hard Disk Drive (HDD), with a smaller amount of SSD storage acting as an SSD cache to enable non-volatile storage of context states and other such information during a power loss event so that a fast power-up may occur upon a re-transmission of system activity. Also shown in FIG. 14, a flash device 1422 may be coupled to the processor 1410, for example via a Serial Peripheral Interface (SPI). This flash device may provide non-volatile storage for system software, including basic input/output software (BIOS), as well as other firmware of the system.

Various input/output (I/O) devices may be present within the system 1400. In particular, shown in the embodiment of FIG. 14 is a display 1424, which may be a high definition LCD or LED panel that also provides a touch screen 1425. In one embodiment, the display 1424 may be coupled to the processor 1410 via a display interconnect, which may be implemented as a high performance graphics interconnect. Touch screen 1425 may be coupled to processor 1410 via another interconnect, which in one embodiment may be I²And C is interconnected. As also shown in FIG. 14, in addition to the touchscreen 1425, user input via touch may also occur via a touchpad 1430, which touchpad 1430 may be configured within the housing and may also be coupled to the same I as the touchscreen 1425²And C is interconnected.

Various sensors may be present within the system and may be coupled to the processor 1410 in different ways for perceptual computing and other purposes. Certain inertial and environmental sensors may pass through sensor hub 1440 (e.g., via I)²C interconnect) is coupled to the processor 1410. In the embodiment shown in fig. 14, these sensors may include an accelerometer 1441, an Ambient Light Sensor (ALS) 1442, a compass 1443, and a gyroscope 1444. Other environmental sensors can include one or more thermal sensors 1446, which thermal sensors 1446 are coupled to the processor 1410 via a system management bus (SMBus) bus in some embodiments.

As can also be seen in fig. 14, various peripherals may be coupled to the processor 1410 via a Low Pin Count (LPC) interconnect. In the illustrated embodiment, various components may be coupled through an embedded controller 1435. Such components can include a keyboard 1436 (e.g., coupled via a PS2 interface), a fan 1437, and a thermal sensor 1439. In some embodiments, touch pad 1430 may also be coupled to EC 1435 via a PS2 interface. In addition, a security processor, such as Trusted Platform Module (TPM) 1438, may also be coupled to processor 1410 via this LPC interconnect.

The system 1400 may communicate with external devices in a variety of ways, including wirelessly. In the embodiment shown in fig. 14, there are various wireless modules, each of which may correspond to a radio configured for a particular wireless communication protocol. One way to use for wireless communication in short distances, such as the near field, may be via NFC unit 1445, which NFC unit 1445 may communicate with processor 1410 via an SMBus in one embodiment. Note that via this NFC unit 1445, devices in close proximity to each other can communicate.

As can also be seen in fig. 14, the additional wireless units may include other short-range wireless engines, including a WLAN unit 1450 and a bluetooth unit 1452. Wi-Fi can be implemented with the WLAN unit 1450^TMCommunication, whereas short-range Bluetooth can take place via the Bluetooth unit 1452^TMAnd (4) communication. These units may communicate with the processor 1410 via a given link.

Further, wireless wide area communication (e.g., according to a cellular or other wireless wide area protocol) may occur via a WWAN unit 1456, which in turn may be coupled to a Subscriber Identity Module (SIM) 1457. Further, to enable receipt and use of location information, a GPS module 1455 may also be present. Note that in the embodiment shown in FIG. 14, the WWAN unit 1456 and the integrated capture device, such as the camera module 1454, may communicate via a given link.

The integrated camera module 1454 may be contained in a cover. To provide audio input and output, the audio processor may be implemented via a Digital Signal Processor (DSP) 1460, which DSP 1460 may be coupled to the processor 1410 via a High Definition Audio (HDA) link. Similarly, the DSP 1460 may communicate with an integrated coder/decoder (CODEC) and amplifier 1462, which in turn may be coupled to an output speaker 1463, which output speaker 1463 may be implemented within the housing. Similarly, the amplifier and CODEC 1462 can be coupled to receive audio input from a microphone 1465, which microphone 1465 can be implemented in one embodiment via a dual array microphone (e.g., a digital microphone array) to provide high quality audio input, enabling voice activated control of various operations within the system. Note also that audio output can be provided from the amplifier/CODEC 1462 to the headphone jack 1464. While shown with these particular components in the embodiment of fig. 14, understand the scope of the present invention is not limited in this regard.

Embodiments may be implemented in many different system types. Referring now to FIG. 15, shown is a block diagram of a system in accordance with an embodiment of the present invention. As shown in fig. 15, multiprocessor system 1500 is a point-to-point interconnect system, and includes a first processor 1570 and a second processor 1580 coupled via a point-to-point interconnect 1550. As shown in fig. 15, each of processors 1570 and 1580 may be multi-core processors, including first and second processor cores (i.e., processors 1574a and 1574b and processor cores 1584a and 1584b), although many more cores may be present in a processor. Further, each of the processors 1570 and 1580 may also include a Graphics Processor Unit (GPU)1573, 1583 to perform graphics operations. Also, dynamic maximum current determination and control as described herein may be performed using software-provided hints, e.g., hints regarding priority of processing levels for a given workload between the core and the GPU. To this end, each processor may include a PCU 1575, 1585 to perform processor-based power management, including dynamic current, to dynamically determine a maximum current consumption level individually for each core and GPU based at least in part on hints provided by software, as described herein.

Still referring to FIG. 15, the first processor 1570 also includes a Memory Controller Hub (MCH) 1572 and point-to-point (P-P) interfaces 1576 and 1578. Similarly, the second processor 1580 includes a MCH 1582 and P-P interfaces 1586 and 1588. As shown in fig. 15, MCH's 1572 and 1582 couple the processors to respective memories, namely a memory 1532 and a memory 1534, memory 1532 and memory 1534 may be portions of system memory (e.g., DRAM) locally attached to the respective processors. First processor 1570 and second processor 1580 may be coupled to chipset 1590 via P-P interconnects 1562 and 1564, respectively. As shown in FIG. 15A, chipset 1590 includes P-P interfaces 1594 and 1598.

Furthermore, chipset 1590 includes an interface 1592 to couple chipset 1590 with a high performance graphics engine 1538 via a P-P interconnect 1539. In turn, chipset 1590 may be coupled to a first bus 1516 via an interface 1596. As shown in fig. 15A, various input/output (I/O) devices 1514 may be coupled to first bus 1516 along with a bus bridge 1518, where bus bridge 1518 couples first bus 1516 to a second bus 1520. Various devices may be coupled to second bus 1520 including, for example, a keyboard/mouse 1522, communication devices 1526, and a data storage unit 1528 (e.g., a disk drive or other mass storage device), wherein the data storage unit 1528 may include code 1530, in one embodiment. Additionally, an audio I/O1524 may be coupled to second bus 1520. Embodiments may be incorporated into other types of systems including mobile devices, such as smart cellular phones, tablet computers, netbooks, ultrabooks, etc^TMAnd so on.

Fig. 16 is a block diagram illustrating an IP core development system 1600, which IP core development system 1600 may be used to fabricate integrated circuits to perform operations according to embodiments. IP core development system 1600 may be used to generate modular, reusable designs that may be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SoC integrated circuit). Design facility 1630 may generate software simulations 1610 of IP core designs in a high-level programming language (e.g., C/C + +). Software simulation 1610 may be used to design, test, and verify the behavior of an IP core. A Register Transfer Level (RTL) design may then be created or synthesized from the simulation model. RTL design 1615 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is executed with the modeled digital signals. In addition to RTL design 1615, lower level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation may vary.

The RTL design 1615 or equivalent may also be synthesized by the design facility into a hardware model 1620, where the hardware model 1620 may take the form of a Hardware Description Language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to validate the IP core design. The IP core design may be stored for transport to a third party manufacturing facility 1665 using non-volatile memory 1640 (e.g., a hard disk, flash memory, or any other non-volatile storage medium). Alternatively, the IP core design may be transmitted over a wired connection 1650 or a wireless connection 1660 (e.g., via the internet). Fabrication facility 1665 may then fabricate an integrated circuit based at least in part on the IP core design. The integrated circuit being fabricated may be configured to perform operations in accordance with at least one embodiment described herein.

Referring now to FIG. 17, shown is a block diagram of a computing system in accordance with an embodiment of the present invention. As shown in fig. 17, system 1700 may be any type of computing system, ranging from small portable devices such as smartphones, tablet computers, and the like, to larger devices including laptop computers, desktop computers, server computers, and the like.

In any case, at the high level shown in fig. 17, the system 1700 includes a system-on-chip (SoC)1710, which may be implemented as a multi-core processor or any other type of SoC. Included within SoC 1710 are a plurality of Intellectual Property (IP) circuits 1720₀-1720₂. In an embodiment, each IP circuit 1720 may be a processing core, a graphics processor, or any other type of homogeneous or heterogeneous processing circuit, such as a specialized processing unit, a fixed function unit, or the like. In thatIn one particular embodiment, assume that IP circuit 1720_0,1Is a general purpose processing core, and the IP circuit 1720₂Is a graphics processor that may be formed, in some cases, from multiple individual graphics processing units.

Depending on the particular workload being executed within SoC 1710, some processing circuits may be more important to the workload than other processing circuits. Thus, with embodiments herein, different IP circuits may be allowed a controlled amount of current consumption based at least in part on hints information received from software 1740 that may provide a workload to execute. By providing this workload, the software 1740 has a priori and more knowledge of the nature of the workload and the importance and likely relative current consumption of the different IP circuits. As such, embodiments include an interface 1745 to provide current consumption information based on runtime heuristics from software 1740 to Power Control Unit (PCU) 1730.

In various embodiments, PCU 1730 may be implemented as a dedicated hardware circuit, one of multiple cores, a microcontroller, or any other hardware circuit. In the illustrated embodiment, PCU 1730 includes a plurality of configuration registers 1736₀-1736₂. In an embodiment, a given configuration register 1736 may be associated with a respective IP circuit 1720 to store current throttling information received from software 1740 for the respective IP circuit. Note that this information may take different forms in different embodiments. In some cases, such information may be based on priority information and may include a relative priority level for each IP circuit, e.g., in percentage units. In other cases, software 1740 may provide the actual maximum current value that would be implemented for the IP circuitry in a throttling situation. In other embodiments, this information may take other forms.

Still referring to fig. 17, PCU 1730 also includes a dynamic current share control circuit 1735. In embodiments herein, dynamic current share control circuitry 1735 may determine a resolved maximum current value for each individual IP circuit based, at least in part, on information stored in configuration registers 1736. In addition, control circuitry 1735 may further determine these resolved maximum current values based on die-specific information, including, for example, leakage information, process variation information, voltage/frequency curves, and the like. As such, the dynamic current sharing control circuitry 1735 may update the values written by the software 1740 based on this information to generate solved values from which throttle control values may be determined. These throttling control values may be sent to the corresponding IP circuits 1720. As shown in fig. 17, each of the processing circuits 1720 includes a configuration storage 1712 to store a respective throttle control value. Note that the throttle control value itself may take different forms in different embodiments. In some cases, this throttle control value may be implemented as a duty cycle value. In other cases, the throttling control value may be an allowed maximum current consumption or an allowed maximum operating frequency of the IP circuit, or the like. As described herein, the IP circuit 1720 may dynamically control its own operation in a throttling scenario based at least in part on this throttling control value stored in the configuration store 1712.

Note that additionally, in the illustration of fig. 17, there is a voltage regulator 1750, which is external to SoC 1720. Voltage Regulator (VR)1750 may be implemented to all IP circuits 1712 shown in FIG. 17_0-2And other circuitry of the SoC 1710. However, it is to be understood that in other cases, the control and current sharing implemented in the embodiments may be performed on a per voltage rail basis. That is, a voltage regulator 1750 or additional voltage regulators may be present that provide power through multiple independent voltage rails, each voltage rail coupled to one or more IP circuits and other logic of the processor. In this case, dynamic current share control circuitry 1735 may dynamically determine a current share throttling control value for each set of IP circuitry associated with a given voltage rail.

Still referring to FIG. 17, assume an implementation in which the maximum current drawn by the IP circuit 1720 (also referred to herein as IP1-IP3), respectively, is: maximum IP1. iccmax; ip2. iccmax; and ip3. iccmax. In addition, assume that VR 1750 can provide a total maximum current of: vr1. iccmax. In a high current VR, such as VR 1750, vr1.iccmax < ip1.iccmax + ip2.iccmax + ip3. iccmax. This undersize is done to limit the cost of the VR. To ensure correctness, PCU 1730 can trigger throttling when it detects that the maximum current capacity of voltage regulator 1750 is about to be exceeded. Such throttling may be performed actively based on a threshold that is slightly lower than the maximum current capability of the actual configuration. It is to be understood that while different implementations are possible, in an embodiment throttling may be achieved by gating the IP clock at a certain duty cycle. The duty cycle of such a scheme may be configured by PCU 1730.

In one embodiment, PCU 1730 can receive specific iccmax values via interface 1745 to which IP circuitry should be throttled when an iccmax violation is detected, i.e.: IP0_ ICCMAX _ WHEN _ threttled; IP1_ ICCMAX _ WHEN _ threttled; IP2_ ICCMAX _ WHEN _ threttled; the value to be stored in the configuration register 1736. Software may fill in these values based on runtime heuristics and may ensure that the current written here is not greater than the vr1.iccmax value.

In turn, PCU 1730, and more specifically dynamic current share control circuit 1735, can use die specific information (e.g., leakage, process variation, V/F curves) to update values written by software. Assume for this example that PCU 1730 considers software inputs and die specific information to determine the solved value: RESOLVED _ IP0_ ICCMAX _ WHEN _ THROTTLED, RESOLVED _ IP1_ ICCMAX _ WHEN _ THROTTLED; and RESOLVED _ IP2_ ICCMAX _ WHEN _ THROTTLED. The dynamic current share control circuit 1735 may then calculate a duty cycle value for throttling the IP circuit based on these finally solved values and the configured maximum current value (iccmax). The duty cycle in this case can be calculated as: duty _ cycle _ ip _ n is reduced _ IPn _ ICCMAX _ WHEN _ threttled/IPn. For IP0, this results in a duty _ cycle _ IP _0 ═ RESOLVED _ IP0_ ICCMAX _ WHEN _ threttled/ip0. ICCMAX.

PCU 1730 may then program the duty cycle for throttling within configuration register 1712. Depending on the platform/SoC level heuristics, the IP _ N _ ICCMAX _ WHEN _ threttled value may be changed to obtain optimal runtime behavior.

As a specific example, assume a pattern-intensive workload, where IP circuit 1720₂Is graphics processingDevice and IP circuit 1720_0,1Is a general purpose processor. In such an arrangement, the graphics driver may provide hints information via interface 1745 to indicate that the graphics processor (and interconnect circuitry) should be provided with its maximum configuration current consumption, while the cores may be throttled. To this end, the graphics driver may provide the configured maximum current consumption values for the graphics processor and interconnect, while the remaining current budget may be allocated to the cores. In this way, when the maximum current consumption limit is reached, the cores may be throttled, but the graphics processors and interconnects may continue to run unrestricted, improving graphics workload.

In another case with core compute intensive workloads, the opposite behavior may occur by allocating maximum current consumption values for the cores and interconnects and allocating the remaining current consumption budget to the graphics processor. In this way, when a power spike is identified, the graphics processor may be throttled, but the core and interconnect may still operate unconstrained, thereby improving core-based workload. In one embodiment, the software may utilize the utilization information to identify the core or graph bound workload. It is to be understood that while shown at this high level in the embodiment of fig. 17, many variations and alternatives are possible.

Referring now to FIG. 18, shown is a flow diagram of a method in accordance with an embodiment of the present invention. As shown in fig. 18, method 1800 is a method for performing dynamic current sharing among multiple IP circuits based at least in part on software-based information about the workload being executed. More specifically, method 1800 may be performed in coordination among various agents including software to be executed by a workload and corresponding hardware, including a hardware-based power controller and one or more IP circuits on which at least some portions of the workload may be executed. As such, method 1800 may be performed by hardware circuitry, firmware, software, and/or combinations thereof.

As shown, in method 1800, software agent 1810 may have a workload to execute and may determine (block 1815) a maximum current budget (and/or maximum current priority) for each such IP circuit based on the heuristics. As shown, software 1810 can provide this information to power controller 1820 via an interface, which power controller 1820 can store this information in a corresponding configuration register, i.e., a current throttle configuration register. In turn, PCU 1820, and more particularly dynamic current share control circuitry 1830, may read this information and determine a maximum current budget for each IP circuit based on this information and die parameters and characteristics. The power controller 1820 may then send this information for programming the corresponding configuration registers of the IP circuitry 1840. Then, during operation of the workload, when the power controller 1820 actively identifies a maximum current condition, it sends a throttling signal to the IP circuit 1840. In turn, the IP circuit 1840 may throttle operations to remain within the maximum current budget identified in its configuration registers. It is to be understood that while shown at this high level in the embodiment of fig. 18, many variations and alternatives are possible.

Referring now to FIG. 19, shown is a flow diagram of a method in accordance with one embodiment of the present invention. As shown in FIG. 19, method 1900 is a method for interfacing between a power controller and a software entity having a priori knowledge of a workload to be performed. Method 1900 in fig. 19 is from the perspective of a power controller, such that method 1900 may be performed by hardware circuitry, firmware, software, and/or combinations thereof.

As shown in FIG. 19, method 1900 begins by receiving current throttling prompt information for a workload (block 1910). More specifically, the power controller may receive this hint information from the software entity via the interface. Although different embodiments are possible, in one embodiment the interface may be a mailbox interface of a power controller to which a software entity may write. In another embodiment, a software entity may perform a configuration register write, e.g., to a Machine Specific Register (MSR) operation, to provide this current throttling hint information. Note that the current throttling hint information may take various forms, including priority information for different processing circuits, e.g., in the form of a percentage or the like.

At block 1920, the power controller stores this current throttle hint information into a set of configuration registers of the power controller. Next at block 1930, the power controller may determine a resolved throttle value for the processing circuit. More specifically, these resolved throttle values may be based on current throttle hint information and various parameters of the processor, including die-based parameters and operating characteristics, such as voltage/frequency curves, and the like. In some cases, the power controller may override the current throttling hints information present in the configuration registers with these resolved throttling values. In other cases, the solved throttle value may be stored in another location.

In any event, control next passes to block 1940, where a dynamic maximum current budget may be calculated for each processing circuit. Such a calculated current budget may be based on the solved throttling value for a given processing circuit and a maximum current budget configured for the processor. To this end, the power controller may include or may be associated with another set of configuration registers that store a maximum current budget for each processing circuit. Note that the maximum current information for this configuration may be stored during a pre-boot environment, e.g., by given firmware.

Still referring to FIG. 19, at block 1950, the dynamic maximum current budget may be transmitted to the processing circuit. It is to be understood that in response to receiving a given maximum dynamic maximum current budget, the processing circuit may store such values in a configuration register and may control operations to remain at or below this dynamic maximum current budget when a throttling condition is identified. Note that these dynamic maximum current budgets are relevant only during throttling events. That is, a given processing circuit may be allowed to exceed its programmed maximum current budget during normal operation, but adhere to this limitation during a throttling condition.

Still referring to fig. 19, during normal operation of the processor, the power controller may receive various telemetry or sensor information. Specifically, as shown in block 1960, such information may be regarding voltage, current, power, and thermal conditions of the processor. As part of its power control operation, the power controller may determine at diamond 1970 whether the total current consumption of the processor exceeds a given threshold. Note that this threshold may be set to a value below the configured maximum current consumption of the processor, so that active control of current consumption may occur.

If it is determined that the total current exceeds this threshold, control passes to block 1980, where a throttle signal may be sent to the processing circuit. In response to receiving this throttling signal, the processing circuit may control its operation to ensure that its current consumption does not exceed the dynamic maximum current budget. In this way, each processing circuit may operate with an independently and dynamically controllable level of current consumption to improve workload execution even when a throttling condition is identified. This is because by dynamically controlling the current consumption levels independently based on the relative priorities of given processing circuits, processing circuits that are indispensable to a particular workload may not be throttled at all, or at least be throttled less than other (less indispensable) processing circuits, during execution of such a workload. It is to be understood that while shown at this high level in the embodiment of fig. 19, many variations and alternatives are possible.

Referring now to FIG. 20, shown is a flow diagram of a method in accordance with another embodiment of the present invention. As shown in FIG. 20, method 2000 is a method for dynamically controlling current consumption within a processing circuit based on a dynamic current budget. As such, method 2000 may be performed by hardware circuitry, such as a processing core, a graphics processor, or other processing circuitry, or by firmware, software and/or a combination thereof executing on such circuitry.

The method 2000 begins by receiving a dynamic current budget from a power controller (block 2010). Note that this dynamic current budget may take different forms in various implementations, including the form of duty cycle information, as described herein. Regardless of the form, at block 2020, the processing circuit stores this dynamic current budget in a maximum current configuration register. Thereafter, the processing circuit may begin (or continue) operation in the configured performance state (block 2030). For example, the processing circuit may be configured to operate in a performance state having a given operating frequency and operating voltage under the control of a power controller or other control circuit. During operation in the performance state of this configuration, it may be determined at diamond 2040 whether a throttle signal is received from the power controller.

In this case, control passes to a block 2050, where the processing circuit may throttle its operation. More specifically, the processing circuit may control its operation to maintain its current consumption no greater than the dynamic current budget. In some cases, the processing circuit may include internal power control logic that may determine operating parameter changes to achieve this current consumption maintenance. As one example, the processing circuit may throttle operations by throttling some clock signals so that operations are slowed down, thereby reducing current consumption by operating at the throttled clock rather than the configured operating frequency. For example, every other clock cycle may be squashed, or other duty cycle control or reduction of clock cycles may occur.

Note that in some cases where other processing circuits do not consume their full current consumption levels, it is possible that the processing circuit may receive an opportunistic current budget from the power controller. Thus, at diamond 2060, it is determined whether an opportunistic current budget has been received. If not, the processing circuit may continue to operate in the throttling condition until it receives a release of the throttling signal (as determined at diamond 2080).

Conversely, if an opportunistic current budget is received, control passes to block 2070, where the processing circuitry may increase its operation. For example, the processing circuit may terminate clock throttling to consume an opportunistic current budget. It is to be understood that while shown at this high level in the embodiment of fig. 20, many variations and alternatives are possible.

In some cases, some cores or other processing circuits may operate with high current consumption. In one arrangement where all cores or other processing circuits are allocated an equal amount of overall package current budget, performance penalties may exist because any core operating beyond the allocated current limit will be throttled via internal or local control operations. However, at the same time, in the event that one or more other cores or processing circuits are operating at a level below their assigned current limit, there is a current margin left unused.

To avoid such concerns, embodiments may provide performance optimization within platforms with constrained power delivery solutions. To this end, embodiments may implement control techniques with global current control, allowing one or more cores or other processing circuits to exceed their individual threshold levels as long as the overall current limit of the package is not exceeded. In this way, embodiments may enhance performance because some cores or other processing circuits may operate at a higher current consumption level (than configured) while the entire processor remains operating within limits.

To this end, embodiments may perform fast current sensing on the load side (e.g., as implemented within an integrated voltage regulator) to provide high speed measurement of actual current consumption. This measurement of current consumption may be output from the integrated voltage regulator as a digital output. In turn, the individual current values from the multiple voltage regulators may then be summed. This summed value may then undergo digital filtering. The resulting filtered value is then compared to a threshold value. Assuming that the overall current consumption represented by this filtered value is less than this threshold, no throttling may occur. If the overall current consumption represented by the filtered value exceeds a threshold, one or more of the domains may be throttled to remain within limits. Note that this throttling may be performed independently (or not) in each domain based on the actual current consumption of each domain and its individual configuration limitations, as described herein. Also, as discussed further above, each domain may perform different throttling operations, such as clock throttling or otherwise controlling operating frequency, operating voltage, and so forth.

By way of example, the actual current consumption may be detected without maintaining a detailed model. Thus, multiple domains may be scaled, and the time constant may be adjusted to minimize unnecessary throttling. Further, embodiments may achieve such performance optimization without any runtime adjustments to the system. Additionally, as described herein, embodiments may be extended to multiple external voltage regulators by converting current to power and summing the results of the contributions of such multiple voltage regulators. Embodiments may also be used for more complex power delivery limitations, such as suppression of energy in the resonant frequency, to improve minimum operating voltage performance.

Referring now to FIG. 21, shown is a block diagram of a processor in accordance with an embodiment of the present invention. As shown in FIG. 21, processor 2100 includes a plurality of cores 2110₀-2110_nThe multi-core processor of (1). Additional processing engines may be present, including a graphics engine 2115. An interconnect 2120, such as a ring interconnect, may be present and used to couple core 2110 and other components together. As shown in the embodiment of FIG. 21, each of these domains may be run from a given integrated voltage regulator 2130₀-2130_xPower is received. Based on the load presented by these domains, the voltage regulator 2130 may measure real-time digital current (using circuitry operating at high speed (e.g., 400 MHz)). In turn, each integrated voltage regulator 2130 provides digital current values to summing circuit 2140, which summing circuit 2140 sums the values into an overall current value. Note that in some embodiments, summing circuit 2140 may be implemented in a distributed manner.

Still referring to fig. 21, this total current value is provided to current controller 2150. In various embodiments, controller 2150 can be implemented as a dedicated circuit separate from both core 2110 and a power controller for the processor (not shown in fig. 21 for ease of illustration). In other cases, controller 2150 can be implemented within a power controller. In any case, as shown, controller 2150 provides the received total current value to filter 2155, which filter 2155 may be implemented as a low pass filter in one embodiment to perform digital filtering on this total current value. This filtering operation may be performed according to an average time window stored in window store 2158. In one embodiment, this time value causes low pass filter 2155 to operate as a 20 nanosecond low pass filter. The filtered current values are provided to a digital comparator 2160, which digital comparator 2160 performs a comparison with threshold current values stored in a threshold storage 2162. If it is determined that the filtered measured current value exceeds the threshold, a throttling condition is thereby identified and communicated to the pulse lengthening circuit 2170, which pulse lengthening circuit 2170 may issue throttling signals to various domains according to the throttling window duration provided by the throttling window storage 2180. In other cases, a band pass filter may be used in place of the low pass filter to reduce the energy in the resonant frequency band.

In an embodiment, the pulse lengthening circuit 2170 may be configured to reduce ringing or hysteresis of the control mechanism. That is, the pulse lengthening circuit 2170 may cause the throttling signal to be active for a given throttling window duration after a throttling event is detected (identified when the filtered measured current value exceeds a threshold value). Even if throttling is initiated upon this event and then the measured current drops below the threshold (due to throttling occurring in one or more cores or other processing circuits), the pulse lengthening circuit 2170 maintains an active throttling signal for at least the length of the throttling window duration to avoid hysteresis or ringing. In various embodiments, the length of this throttling window duration may be programmable, and in some embodiments, the pulse lengthening circuit 2170 may be an optional component. That is, in other cases, hysteresis or other control schemes may be applied to the throttle signal. It is to be understood that while shown at this high level in the embodiment of fig. 21, many variations and alternatives are possible.

As described above, multiple instances of a current controller as in fig. 21 may be provided for each of multiple voltage regulators, and in turn, multiple instances may be coupled to a power controller. Such a power controller may perform power control for a power supply source that provides power to a plurality of voltage regulators. That is, in a given computing platform, a single power supply may exist to power multiple external voltage regulators, such as multiple voltage regulators residing on a motherboard, where each voltage regulator provides a given regulated voltage for use by on-chip and off-chip components. As with the discussion above, it is possible for the individual voltage regulators to operate at a higher level when one or more other of the voltage regulators are operating at a lower level. This is due to the fact that the single power supply source providing power to these individual voltage regulators has sufficient capacity to do so, provided that not all of the voltage regulators exceed their individual threshold levels.

Referring now to fig. 22, shown is a block diagram of a control arrangement in accordance with another embodiment of the present invention. As shown in fig. 22, a plurality of current controllers 2250 are provided, each associated with a given voltage regulator. More specifically, as shown, a first current controller 2250₁And providing a first voltage level (e.g., V)_CC) And a second current controller 2250, and a second voltage regulator (not shown) are connected to the first current controller 2250₂And providing a second (e.g. auxiliary) voltage level (e.g. V)_Aux) Is associated with a second voltage regulator (not shown). Note that the controller 2250 is shown at a high level as including a respective low pass filter 2252, digital comparator 2254 and downsampler 2256, but it is understood that these controllers may be configured as shown in fig. 21. Note that downsampler 2256 may be optional in some embodiments. At a high level, when the received measured current exceeds a threshold level, a corresponding throttling signal is provided to the individual domains powered by this voltage regulator, as described above.

Further, the current controller 2250 performs down-sampling of the measured current consumption via the down-sampler 2256, which in turn is provided to the power controller 2260. The power controller 2260 may be implemented as dedicated circuitry or within a power controller of the processor. In any event, power controller 2260 is via converter 2265_1-2Converting a plurality of incoming digital current values into power values, these converters 2265_1-2Based on the voltage delivered by a given voltage regulator (i.e., the regulated voltage minus any delivery losses (e.g., I)₁R₁) Current-to-power conversion via multiplication operations to provide digital power values to summer 2270, which summer 2270 sums the digital power values. Note that in other embodiments, power controller 2260 may receive the current value directly, without including electricityA flow controller 2250.

This summed power value is then provided to a low pass filter 2275, which low pass filter 2275 may operate for a longer time window duration according to the average time window stored in window storage 2276. This filtered power value is, in turn, provided to a digital comparator 2280, which digital comparator 2280 compares it to the threshold value received from threshold storage 2282. When it is determined in the digital comparator 2280 that the filtered measured power value exceeds the threshold value, a throttling event is indicated and communicated to the pulse lengthening circuit 2290. In general, the pulse extension circuit 2290 may operate in the same manner as the pulse extension circuit 2170 discussed above, albeit at different choke window durations depending on the value stored in the choke window storage 2295. As such, the pulse lengthening circuit 2290 sends throttling signals to the powered domains based at least in part on the comparison output of the digital comparator 2280 to cause them to take appropriate throttling activity. It is to be understood that while shown at this high level in the embodiment of fig. 22, many variations and alternatives are possible.

Referring now to FIG. 23, shown is a flow diagram of a method in accordance with an embodiment of the present invention. More specifically, as shown in FIG. 23, method 2300 is a method for performing dynamic current consumption control as described herein. As such, method 2300 may be performed by hardware circuitry, firmware, software, and/or combinations thereof, and may be implemented using dedicated hardware circuitry for a processor and/or in association with power control circuitry, for example.

As shown, method 2300 begins by receiving a plurality of digital current values for a plurality of processing circuits (block 2310). More specifically, the summing circuits may receive these digital current values from respective integrated voltage regulators, where each voltage regulator is associated with a processing circuit, such as a core, a graphics unit, an interconnect circuit, and so forth. It is to be understood that in other cases, the number of integrated voltage regulators may be less than the processing circuits, such that one or more of the integrated voltage regulators may provide digital current values for a plurality of circuits.

In any case, at block 2320, the summing circuit sums the plurality of digital current values to obtain a total current value. Next, control passes to block 2330 where this total current value may be filtered. As one example, a low pass filter, such as implemented in a power controller as described herein, may perform filtering of this total current value according to a programmable time constant. Next, it is determined at diamond 2340 whether this filtered total current value exceeds a threshold value. If not, no further operations occur in this iteration of the control loop and the method 2300 may continue to operate to ensure that the current consumption of the processor is maintained within appropriate levels.

Still referring to FIG. 23, if instead it is determined that the filtered total current value exceeds the threshold value, control passes to a block 2350 where a throttle signal is sent to the processing circuit. It is to be understood that in response to this throttle signal, at least one of the processing circuits, and possibly a plurality of processing circuits, may throttle its operation accordingly. For example, each processing circuit may be configured with a configured maximum current consumption value. In response to the throttle signal, the processing circuit may throttle its operation to ensure that its current consumption falls below the maximum current consumption value of this configuration. With the arrangement as described herein, processor operation may continue without throttling as long as the filtered total current value is less than the threshold value. In this case, one or more processing circuits may operate at a current consumption level that exceeds their configured maximum current consumption value, while one or more other processing circuits operate at a current consumption level that is below their configured maximum current consumption value. Although shown at this high level in the embodiment of fig. 23, many variations and alternatives are possible.

It is to be understood that the fast current information obtained herein further may be used to perform additional power control techniques, such as controlling the level of a power supply that powers multiple voltage regulators of a platform. Referring now to FIG. 24, shown is a flow diagram of a method in accordance with another embodiment of the present invention. More specifically, as shown in fig. 24, method 2400 is another method for performing dynamic current consumption control as described herein. As such, method 2400 may be performed by hardware circuitry, firmware, software, and/or combinations thereof, e.g., may be implemented using dedicated hardware circuitry of a processor and/or in connection with power control circuitry.

As shown, method 2400 begins by receiving a filtered aggregate current value from a current controller associated with a plurality of voltage regulators (block 2410). Next, control passes to block 2420 where these filtered total current values may be converted to power values. The power values may then be summed (block 2430). After summing the power values into a total power value, control passes to block 2440 where this total power value is filtered, e.g., according to a different time constant than the filtering of the current values described above.

Still referring to fig. 24, it is next determined at diamond 2450 whether this filtered power value exceeds a threshold. If not, no further operations occur in this iteration of the control loop, and the method 2400 may continue to operate to ensure that the current consumption of the processor is maintained within the appropriate levels. Conversely, if it is determined that the filtered power value exceeds the threshold, control passes to 2460 where a throttle signal is sent to the domain being powered, such as the processing circuit itself (or at least a subset of such circuits associated with a given one of the voltage regulators). It is to be understood that in response to this throttling signal, the powered domain may throttle operation accordingly, for example by reducing its operating parameters, such that the current demand is reduced.

The following examples relate to further embodiments.

In one example, an apparatus comprises: a plurality of IP circuits, each of the plurality of IP circuits comprising a configuration register to store a dynamic current budget; and a power controller coupled with the plurality of IP circuits, the power controller comprising a dynamic current sharing control circuit to receive current throttling hints information about workloads to be executed on at least some of the plurality of IP circuits and to generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon.

In an example, the power controller includes a plurality of second configuration registers to store the current throttling hint information, wherein the dynamic current sharing control circuit is to determine the dynamic current budget for the plurality of IP circuits based on the current throttling hint information and one or more parameters of the apparatus.

In an example, the power controller includes an interface to enable software to write the current throttling hint information to the plurality of second configuration registers.

In an example, the power controller is to receive the current throttling hint information from the software based on heuristic information regarding usage of the plurality of IP circuits during execution of the workload.

In an example, the dynamic current sharing control circuit is to determine the dynamic current budget for the plurality of IP circuits further based on a configured maximum current budget for each of the plurality of IP circuits.

In an example, for a first workload, the dynamic current sharing control circuit is to: setting a dynamic current budget for a first IP circuit to a configured maximum current budget for the first IP circuit; and setting a dynamic current budget for the second IP circuit to be less than a configured maximum current budget for the second IP circuit.

In one example, for a second workload, the dynamic current sharing control circuit is to: setting a dynamic current budget for the first IP circuit to be less than a configured maximum current budget for the first IP circuit; and setting the dynamic current budget for the second IP circuit to a configured maximum current budget for the second IP circuit.

In an example, the first IP circuitry includes a core and the second IP circuitry includes a graphics processor.

In an example, in response to a throttling signal from the power controller, the first IP circuitry is to limit operation to a configured maximum current budget of the first IP circuitry, and the second IP circuitry is to limit operation to a dynamic current budget of the second IP circuitry.

In an example, the second IP circuit is to throttle one or more clock cycles of a clock signal in response to the throttle signal based on the dynamic current budget.

In an example, the dynamic current sharing circuit is to provide an opportunistic current budget to at least one of the plurality of IP circuits during a throttling event that enables the at least one IP circuit to exceed a dynamic current budget of the at least one IP circuit.

In another example, a method comprises: receiving, in a power controller of a processor, current throttling hints information about a workload from a software entity; calculating a dynamic maximum current budget for each of a plurality of processing circuits of the processor based on the current throttling hints information and configured maximum current budget values for the plurality of processing circuits; sending the dynamic maximum current budget to each of the plurality of processing circuits; and in response to determining that the current consumption level of the processor exceeds a threshold, send a throttling signal to the plurality of processing circuits to cause the plurality of processing circuits to throttle activity based on the dynamic maximum current budget.

In an example, the method further comprises: receiving the current throttling prompt message in the power controller via an interface; and storing the current throttling hint information in a set of configuration registers of the power controller.

In an example, the method further includes determining a resolved throttle value for the plurality of processing circuits based on the current throttle hint information and die specific information.

In an example, calculating the dynamic maximum current budget for each of the plurality of processing circuits is further based on solved throttle values of the plurality of processing circuits.

In an example, the method further comprises: throttling a first processing circuit of the plurality of processing circuits in response to the throttling signal; and in response to the throttle signal, enabling a second processing circuit of the plurality of processing circuits to execute unconstrained.

In another example, a computer-readable medium comprising instructions for performing the method of any of the above examples.

In another example, a computer-readable medium including data is used by at least one machine to fabricate at least one integrated circuit to perform the method as in any one of the above examples.

In another example, an apparatus comprising means for performing the method of any of the above examples.

In another example, a system includes a SoC and a dynamic random access memory coupled with the SoC. The SoC may include: a plurality of cores and at least one graphics processor, each of the plurality of cores and the at least one graphics processor including a configuration register to store a dynamic current budget; and a power controller coupled with the plurality of cores and the at least one graphics processor, the power controller including an interface to receive current throttling hint information from a software entity regarding a workload to be executed on the SoC, the power controller further including dynamic current sharing control circuitry to generate the dynamic current budget for the plurality of cores and the at least one graphics processor based at least in part on the current throttling hint information.

In an example, the power controller includes a plurality of second configuration registers to store the current throttling hint information, and the dynamic current sharing control circuitry is to determine solved current budgets for the plurality of cores and the at least one graphics processor based on the current throttling hint information and one or more parameters of the SoC.

In an example, the dynamic current sharing control circuitry is to determine the dynamic current budget based on a solved current budget for the plurality of cores and the at least one graphics processor and a configured maximum current budget for each of the plurality of cores and the at least one graphics processor.

In an example, for a first workload, the dynamic current sharing control circuit is to: setting a dynamic current budget for at least one of the plurality of cores to a configured maximum current budget for the at least one core; and setting a dynamic current budget for the at least one graphics processor to be less than a configured maximum current budget for the at least one graphics processor.

In another example, an apparatus comprises: a plurality of processing circuits to execute instructions; a summing circuit coupled to the plurality of processing circuits, the summing circuit receiving a plurality of digital current values, each digital current value corresponding to a measured current from one of the plurality of processing circuits, and generating a total current value from the plurality of digital current values; and a current controller coupled to the summing circuit to filter the aggregate current value and compare the filtered aggregate current value to a threshold value, and to send a throttle signal to the plurality of processing circuits when the filtered aggregate current value exceeds the threshold value.

In an example, each of the plurality of processing circuits is to independently throttle an operation in response to the throttle signal.

In an example, each of the plurality of processing circuits is to independently throttle operations in response to the throttle signal according to a configuration value stored in a configuration storage of the respective processing circuit.

In an example, the apparatus further includes a plurality of integrated voltage regulators coupled with the plurality of processing circuits to provide the plurality of digital current values to the summing circuit.

In one example, the current controller includes: a low pass filter to filter the total current value; a digital comparator to compare the filtered total current value to the threshold value; and a pulse stretching circuit coupled to receive a comparison signal from the digital comparator and output the throttling signal based at least in part on the comparison signal.

In an example, the pulse lengthening circuit is to maintain the throttling signal for a remaining duration of a throttling window after the filtered current value falls below the threshold.

In one example, the apparatus further comprises: a plurality of current controllers, each current controller associated with one of the plurality of voltage regulators; and a power controller coupled to the plurality of voltage regulators. The power controller is to convert the filtered current values from each of the plurality of current controllers to power values, combine the power values into a summed power value, filter the summed power value, and send a second throttle signal to at least some of the plurality of processing circuits when the filtered summed power value exceeds a threshold power value.

It is to be understood that various combinations of the above examples are possible.

Note that the terms "circuitry" and "electronics" are used interchangeably herein. As used herein, these terms and the term "logic" are used to refer, either individually or in any combination, to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, processor circuitry, microcontroller circuitry, hardware logic circuitry, state machine circuitry, and/or any other type of physical hardware component. Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be arranged to perform the various methods and techniques described herein. Of course, the scope of the invention is not limited to communication devices, and other embodiments may be directed to other types of apparatuses for processing instructions, or one or more machine-readable media comprising instructions that in response to being executed on a computing device, cause the device to carry out one or more of the methods and techniques described herein.

Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. Embodiments may also be implemented in data and stored on a non-transitory storage medium, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform one or more operations. Still further embodiments may be implemented in a computer-readable storage medium that includes information which, when manufactured into a SoC or other processor, will configure the SoC or other processor to perform one or more operations. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, Solid State Drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritable (CD-RW), and magneto-optical disks, semiconductor devices such as read-only memory (ROM), Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), an erasable programmable read-only memory (EPROM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a magnetic or optical card, or any other type of media suitable for storing electronic instructions.

While the invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.