阅读说明：本技术 记录静电放电事件的电路和方法、集成电路、微控制单元 (Circuit and method for recording electrostatic discharge event, integrated circuit, and micro control unit ) 是由 温禄泉 于 2021-07-23 设计创作，主要内容包括：本申请实施例提供的一种记录静电放电事件的电路、集成电路、微控制单元和方法,所述电路包括检测电路,用于连接微控制单元MCU的待测端口,对所述待测端口的静电放电ESD信号进行检测,输出检测信号；泄放电路,用于根据所述检测信号对所述待测端口的ESD信号进行泄放；整形电路,用于对所述检测信号进行整形,将所述检测信号由模拟信号整形为数字信号；事件判断电路,用于根据所述整形后的检测信号判断是否产生了ESD事件,其中,若判断产生了ESD事件,则输出响应信号；响应电路,用于根据所述响应信号对所述ESD事件进行记录。采用本申请实施例提供的技术方案,可以对发生的ESD事件进行记录,便于后期对芯片的ESD事件分析跟踪。(The circuit comprises a detection circuit, a micro control unit and a control unit, wherein the detection circuit is used for connecting a port to be detected of a Micro Control Unit (MCU), detecting an electrostatic discharge (ESD) signal of the port to be detected and outputting a detection signal; the discharge circuit is used for discharging the ESD signal of the port to be detected according to the detection signal; the shaping circuit is used for shaping the detection signal and shaping the detection signal into a digital signal from an analog signal; an event judgment circuit for judging whether an ESD event is generated according to the shaped detection signal, wherein if the ESD event is judged to be generated, a response signal is output; and the response circuit is used for recording the ESD events according to the response signals. By adopting the technical scheme provided by the embodiment of the application, the generated ESD events can be recorded, and the analysis and tracking of the ESD events of the chip at the later stage are facilitated.)

1. A circuit for recording an electrostatic discharge event, comprising:

the detection circuit is used for connecting a port to be detected, detecting an electrostatic discharge (ESD) signal of the port to be detected and outputting a detection signal;

the discharge circuit is used for discharging the ESD signal of the port to be detected according to the detection signal;

the shaping circuit is used for shaping the detection signal and shaping the detection signal into a digital signal from an analog signal;

an event judgment circuit for judging whether an ESD event is generated according to the shaped detection signal, wherein if the ESD event is judged to be generated, a response signal is output;

and the response circuit is used for recording the ESD events according to the response signals.

2. The circuit of claim 1, wherein the response circuit comprises an ESD event register;

and the ESD event register is used for marking in the corresponding marking bit after receiving the response signal.

3. The circuit of claim 1, wherein the response circuit comprises an ESD interrupt circuit and an interrupt count circuit;

the ESD interruption circuit is used for generating an interruption signal after receiving the response signal;

the interrupt counting circuit is used for counting the interrupt signals.

4. The circuit of claim 1, wherein the response circuit comprises an ESD interrupt circuit and a display unit;

the ESD interruption circuit is used for generating an interruption signal after receiving the response signal;

and the display unit is used for displaying prompt information according to the interrupt signal, wherein the prompt information is used for prompting that an ESD event is generated.

5. The circuit of claim 1, wherein the response circuit comprises an ESD interrupt circuit and a memory;

the ESD interruption circuit is used for generating an interruption signal after receiving the response signal;

the memory is used for storing the generation times of the interrupt signal.

6. The circuit according to claim 1, wherein the number of the ports to be tested is N, and N is greater than or equal to 2;

the response circuit is specifically configured to record the ESD events corresponding to the N ports to be tested respectively according to the response signals corresponding to the N ports to be tested.

7. The circuit of claim 1,

the detection circuit comprises a capacitor and a resistor which are connected in series, wherein a first end and a second end of the capacitor are respectively connected with the port to be detected and a first end of the resistor, and a second end of the resistor is connected with VSS;

the bleeder circuit comprises an MOS device, the second end of the capacitor is connected with the grid electrode of the MOS device, and the source electrode and the drain electrode of the MOS device are respectively connected with the VSS and the port to be tested.

8. The circuit of claim 7, further comprising an inverter;

and the second end of the capacitor is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the grid electrode of the MOS device.

9. An integrated circuit comprising the circuit of any of claims 1-8 for recording an electrostatic discharge event.

10. A micro-control unit comprising a processor and a circuit for recording electrostatic discharge events as claimed in any one of claims 1 to 8.

11. A method of recording an electrostatic discharge event, comprising:

detecting an electrostatic discharge (ESD) signal of a port to be detected, and outputting a detection signal;

discharging the ESD signal of the port to be detected according to the detection signal;

shaping the detection signal, and shaping the detection signal into a digital signal from an analog signal;

judging whether an ESD event is generated according to the shaped detection signal, wherein if the ESD event is judged to be generated, a response signal is output;

and recording the ESD event according to the response signal.

Technical Field

The present application relates to the field of electronic technology, and in particular to a circuit, an integrated circuit, a micro control unit and a method for recording electrostatic discharge events.

Background

Static electricity is an objective natural phenomenon, and is generated in various ways, such as contact, friction, induction between electrical appliances and the like. Electrostatic Discharge (ESD) is a phenomenon in which electrostatic charges are transferred between two media with different electrostatic potentials. ESD is an over-speed discharge phenomenon that can instantaneously emit a large current and a high voltage.

An Input/Output (I/O) port of a Micro Controller Unit (MCU) is usually provided with an ESD detection circuit and an ESD bleeder circuit. When the port rises rapidly and the voltage reaches an ESD signal with a certain height, the ESD detection circuit can identify the ESD signal and start the discharge circuit (the discharge circuit presents extremely low impedance instantly), so that the voltage at the port is clamped in a safe range, and the internal circuit is protected from being damaged due to the fact that the internal circuit bears the excessively high voltage. When the external ESD signal falls back, the bleeder circuit resumes an off (open) state, waiting for the next ESD event.

However, in the prior art, each ESD event cannot be recorded by the MCU, so that the user cannot know whether the MCU has experienced the ESD event or how many times the MCU has experienced the ESD event.

Disclosure of Invention

In view of this, the present application provides a circuit, an integrated circuit, a micro control unit and a method for recording an ESD event, so as to solve the problem that in the prior art, an ESD event cannot be recorded by an MCU, and thus a user cannot know whether the MCU has experienced the ESD event or how many times the MCU has experienced the ESD event.

In a first aspect, an embodiment of the present application provides a circuit for recording an electrostatic discharge event, including:

the detection circuit is used for connecting a port to be detected of the MCU, detecting an electrostatic discharge (ESD) signal of the port to be detected and outputting a detection signal;

the discharge circuit is used for discharging the ESD signal of the port to be detected according to the detection signal;

the shaping circuit is used for shaping the detection signal and shaping the detection signal into a digital signal from an analog signal;

an event judgment circuit for judging whether an ESD event is generated according to the shaped detection signal, wherein if the ESD event is judged to be generated, a response signal is output;

and the response circuit is used for recording the ESD events according to the response signals.

Preferably, the response circuit comprises an ESD event register;

and the ESD event register is used for marking in the corresponding marking bit after receiving the response signal.

Preferably, the response circuit comprises an ESD interrupt circuit and an interrupt count circuit;

the ESD interruption circuit is used for generating an interruption signal after receiving the response signal;

the interrupt counting circuit is used for counting the interrupt signals.

Preferably, the response circuit includes an ESD interrupt circuit and a display unit;

the ESD interruption circuit is used for generating an interruption signal after receiving the response signal;

and the display unit is used for displaying prompt information according to the interrupt signal, wherein the prompt information is used for prompting that an ESD event is generated.

Preferably, the response circuit comprises an ESD interrupt circuit and a memory;

the ESD interruption circuit is used for generating an interruption signal after receiving the response signal;

the memory is used for storing the generation times of the interrupt signal.

Preferably, the memory is a memory inside the MCU and/or a memory outside the MCU.

Preferably, the number of the ports to be detected is N, and N is more than or equal to 2;

the response circuit is specifically configured to record the ESD events corresponding to the N ports to be tested respectively according to the response signals corresponding to the N ports to be tested.

Preferably, the detection circuit comprises a capacitor and a resistor which are connected in series, a first end and a second end of the capacitor are respectively connected with the port to be detected and a first end of the resistor, and a second end of the resistor is connected with VSS;

the bleeder circuit comprises an MOS device, the second end of the capacitor is connected with the grid electrode of the MOS device, and the source electrode and the drain electrode of the MOS device are respectively connected with the VSS and the port to be tested.

Preferably, an inverter is further included;

and the second end of the capacitor is connected with the input end of the phase inverter, and the output end of the phase inverter is connected with the grid electrode of the MOS device.

In a second aspect, an embodiment of the present application provides an integrated circuit including the circuit for recording an electrostatic discharge event according to any one of the first aspect.

In a third aspect, an embodiment of the present application provides a micro control unit, which includes a processor, a memory, and the circuit for recording an electrostatic discharge event according to any one of the first aspect.

In a fourth aspect, an embodiment of the present application provides a method for recording an electrostatic discharge event, including:

detecting an electrostatic discharge (ESD) signal of a port to be detected, and outputting a detection signal;

discharging the ESD signal of the port to be detected according to the detection signal;

shaping the detection signal, and shaping the detection signal into a digital signal from an analog signal;

judging whether an ESD event is generated according to the shaped detection signal, wherein if the ESD event is judged to be generated, a response signal is output;

and recording the ESD event according to the response signal.

By adopting the technical scheme provided by the embodiment of the application, the generated ESD events can be recorded, and the analysis and tracking of the ESD events of the chip at the later stage are facilitated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.

FIG. 1 is a schematic diagram of a circuit for recording an ESD event according to an embodiment of the present disclosure;

fig. 2A is a circuit diagram of a detection circuit and a bleeding circuit according to an embodiment of the present disclosure;

fig. 2B is a circuit diagram of another detection circuit and bleeding circuit provided in the embodiments of the present application;

FIG. 3 is a schematic diagram of another circuit for recording ESD events according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another circuit for recording ESD events according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another circuit for recording ESD events according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another circuit for recording ESD events according to an embodiment of the present disclosure;

fig. 7 is a flowchart illustrating a method for recording an electrostatic discharge event according to an embodiment of the present disclosure.

Detailed Description

For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.

It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of associative relationship that describes an associated object, meaning that three types of relationships may exist, e.g., A and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

The embodiment of the application provides a circuit, an integrated circuit, a micro control unit and a method for recording an electrostatic discharge event, aiming at the problem that in the prior art, an ESD event can not be recorded by an MCU, and then a user can not know whether the MCU has experienced the ESD event or how many times of the ESD event. The following description is made with reference to the accompanying drawings.

Referring to fig. 1, a schematic circuit diagram for recording an electrostatic discharge event according to an embodiment of the present application is provided. As shown in fig. 1, the circuit for recording the electrostatic discharge event comprises a detection circuit, a leakage circuit, a shaping circuit, an event judgment circuit and a response circuit. The output port of the detection circuit is respectively connected with the input port of the bleeder circuit and the input port of the shaping circuit; the output port of the shaping circuit is connected with the input port of the event judgment circuit; the output port of the judgment circuit is connected with the input port of the response circuit.

The detection circuit is used for connecting a port to be detected of the MCU, detecting an electrostatic discharge (ESD) signal of the port to be detected and outputting a detection signal. The discharge circuit is used for discharging the ESD signal of the port to be detected according to the detection signal output by the detection circuit.

For example, when the detection circuit detects that an ESD signal exists at a certain pin of the MCU chip, a driving signal is generated and transmitted to the bleeding circuit to open the bleeding channel. The ESD signal may be represented as a fast rising and transient voltage reaching a very high destructive signal, the driving signal being the detection signal. When the discharge channel of the discharge circuit is opened, the impedance of the discharge circuit is extremely low, a large part of ESD current is quickly discharged from the discharge channel, the voltage at the end of the discharge circuit is clamped in a certain range, and even if the discharge circuit is connected with the protected circuit in parallel, the excessive voltage cannot be generated on the protected circuit.

Referring to fig. 2A, a circuit diagram of a detection circuit and a bleeding circuit is provided in the embodiment of the present application. As shown in fig. 2A, the detection circuit 201 includes a capacitor C and a resistor R, which are connected in series with each other. Specifically, a first end of the capacitor C is connected to an I/O (port to be tested), a second end of the capacitor C is connected to a first end of the resistor R, and a second end of the resistor R is connected to VSS. The bleeding circuit 202 can be implemented by MOS devices. Specifically, the bleeder circuit 202 may employ an NMOS transistor. The second end of the capacitor C is connected with the grid G of the NMOS tube, and the source S and the drain D of the NMOS tube are respectively connected with VSS and I/O.

When the ESD voltage at the I/O exceeds a set threshold, the detection circuit 201 outputs a driving signal to the gate G of the NMOS transistor, so as to drive the NMOS transistor to be turned on, and discharge the ESD current at the I/O, thereby clamping the voltage at the I/O within a safe range.

Referring to fig. 2B, a circuit diagram of another detection circuit and a bleeder circuit is provided for embodiments of the present application. As shown in fig. 2B, it further includes an inverter 203 based on fig. 2A, an input end of the inverter 203 is connected to the second end of the capacitor C, and an output end of the inverter 203 is connected to the gate G of the NMOS transistor.

In a specific implementation, when the ESD voltage at the I/O exceeds a set threshold, the detection circuit 201 outputs a driving signal to the input end of the inverter 203, and the driving signal is transmitted to the gate G of the NMOS transistor after being processed by the inverter 203. After the driving signal is processed by the inverter 203, the driving capability of the driving signal can be enhanced.

It should be noted that fig. 2A and fig. 2B are only one possible implementation manner listed in the embodiments of the present application, and should not be taken as a limitation to the scope of the present application. For example, the MOS device of the inverter 203 may be implemented by a PMOS transistor in addition to an NMOS transistor, which is not limited by the embodiment of the present application.

And the shaping circuit is used for shaping the detection signal and shaping the detection signal into a digital signal from an analog signal. It is understood that the driving signal output by the detection circuit is an analog signal, and the shaping circuit can perform edge and pulse width detection on the driving signal, so as to convert the analog signal into a digital signal, i.e. into logic data 1 or 0.

And the event judgment circuit is used for judging whether an ESD event is generated according to the shaped detection signal, wherein if the ESD event is judged to be generated, a response signal is output. In some possible implementation manners, if the shaped detection signal is 1, it is determined that an ESD event is generated, and a response signal is output; and if the shaped detection signal is 0, judging that the ESD event is not generated, and not outputting a response signal.

And the response circuit is used for recording the ESD events according to the response signals. Specifically, if the event judgment circuit outputs a response signal indicating that an ESD event is generated, the response circuit records the ESD event. For example, information such as the number of times an ESD event occurred, the time, etc. may be recorded. This is not particularly limited by the examples of the present application.

Referring to fig. 3, a schematic diagram of another circuit for recording an electrostatic discharge event according to an embodiment of the present application is provided. As shown in fig. 3, in the embodiment of the present application, the response circuit includes an ESD event register. And the ESD event register is used for marking in the marking bit corresponding to the register after receiving the response signal, so as to record the ESD event.

Referring to fig. 4, a schematic diagram of another circuit for recording an electrostatic discharge event according to an embodiment of the present application is provided. As shown in fig. 4, in the embodiment of the present application, the response circuit includes an ESD interrupt circuit and an interrupt count circuit. The ESD interruption circuit is used for generating an interruption signal after receiving the response signal; and the interrupt counting circuit is used for counting the interrupt signals so as to record the ESD events.

The embodiment of the present application differs from the embodiment shown in fig. 3 in that ESD events are counted by generating an interrupt in the embodiment of the present application.

Referring to fig. 5, a schematic diagram of another circuit for recording an electrostatic discharge event according to an embodiment of the present application is provided. As shown in fig. 5, in the embodiment of the present application, the response circuit includes an ESD interrupt circuit and a display unit; an ESD interrupt circuit for generating an interrupt signal after receiving the response signal; and the display unit is used for displaying prompt information according to the interrupt signal, and the prompt information is used for prompting that the ESD event is generated.

In a specific implementation, the display unit may be an LCD display screen, and certainly, may also be other types of implementation units, which is not limited in this embodiment of the present application.

The embodiment of the present application is different from the embodiment shown in fig. 4 in that the occurrence of each ESD event is reminded in the embodiment of the present application. On one hand, the MCU can know the running environment condition of the MCU and evaluate the risk. And on the other hand, giving an ESD risk prompt on the human-computer interface.

Referring to fig. 6, a schematic diagram of another circuit for recording an electrostatic discharge event according to an embodiment of the present application is provided. As shown in fig. 6, in the embodiment of the present application, the response circuit includes an ESD interrupt circuit and a memory. An ESD interrupt circuit for generating an interrupt signal after receiving the response signal; the memory is used for storing the times of generation of the interrupt signals.

In particular, the memory may be a memory internal to the MCU or a memory external to the MCU. For example, it may be FLASH inside the MCU and/or EEPROM outside the MCU. If the response circuit receives the response signal, the ESD interruption circuit generates an interruption signal, an address is set in the internal FLASH or the external EEPROM as the number accumulation function of the ESD events, when the interruption function confirms that the ESD events occur, the address of the internal FLASH or the external EEPROM is written back by adding 1 to the value, therefore, the number of the ESD events experienced by the MCU can be continuously updated and recorded, and when the MCU fails, if the ESD experienced times of the MCU are analyzed, the MCU can be directly known by reading the data of the internal FLASH or the external EEPROM.

The embodiment of the present application is different from the embodiment shown in fig. 4 and 5 in that a memory is used to count interrupts in the embodiment of the present application; the number of ESD events can be indirectly recorded into the internal memory and/or the external memory, and the ESD failure analysis and tracking of the chip can be facilitated in the future.

It can be understood that the MCU usually includes a plurality of IO ports, and when the ESD event is recorded, the ESD events corresponding to the IO ports are recorded separately for later analysis. In a specific implementation, one bit of the ESD event register may correspond to one IO port. For example, if the MCU supports a maximum of 64 IO ports (including general GPIOs and power IO), the ESD event register has 64 bits corresponding to it. When an ESD event is detected by one of the IO ports, the corresponding bit is set to 1. The MCU can know which IO port has an ESD event by reading the ESD event register.

By adopting the technical scheme provided by the embodiment of the application, the generated ESD events can be recorded, and the analysis and tracking of the ESD events of the chip at the later stage are facilitated.

Corresponding to the above embodiments, the present application further provides an integrated circuit including the circuit for recording an electrostatic discharge event shown in the above embodiments. For details, reference may be made to the description of the above embodiments, and for brevity, detailed description is omitted here.

Corresponding to the above embodiments, the embodiments of the present application further provide a micro control unit, which includes a processor, a memory, and the circuit for recording the electrostatic discharge event shown in the above embodiments. For details, reference may be made to the description of the above embodiments, and for brevity, detailed description is omitted here.

Corresponding to the above embodiments, the embodiments of the present application further provide a method for recording an electrostatic discharge event.

Referring to fig. 7, a flowchart of a method for recording an electrostatic discharge event according to an embodiment of the present application is further provided. As shown in fig. 7, it mainly includes the following steps.

Step S701: detecting an electrostatic discharge (ESD) signal of a port to be detected, and outputting a detection signal;

step S702: discharging the ESD signal of the port to be detected according to the detection signal;

step S703: shaping the detection signal, and shaping the detection signal into a digital signal from an analog signal;

step S704: judging whether an ESD event is generated according to the shaped detection signal, wherein if the ESD event is judged to be generated, a response signal is output;

step S705: and recording the ESD event according to the response signal.

It should be noted that the contents of the method embodiment of the present application and the contents of the circuit embodiment described above may be referred to each other, and for brevity, are not described herein again.

By adopting the technical scheme provided by the embodiment of the application, the generated ESD events can be recorded, and the analysis and tracking of the ESD events of the chip at the later stage are facilitated.

In specific implementation, the present application further provides a computer storage medium, where the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided in the present application when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).

In a specific implementation, an embodiment of the present application further provides a computer program product, where the computer program product includes executable instructions, and when the executable instructions are executed on a computer, the computer is caused to perform some or all of the steps in the foregoing method embodiments.

In the embodiments of the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, and means that there may be three relationships, for example, a and/or B, and may mean that a exists alone, a and B exist simultaneously, and B exists alone. Wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" and similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, at least one of a, b, and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

Those of ordinary skill in the art will appreciate that the various elements and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided by the present invention, any function, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only an embodiment of the present invention, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.