阅读说明：本技术 一种基于双核处理器的电机驱动测试方法和电机驱动器 (Motor drive test method based on dual-core processor and motor driver ) 是由 石增辉 王超然 马俊 毛永乐 乔洪凯 于 2020-05-22 设计创作，主要内容包括：本发明涉及一种基于双核处理器的电机驱动测试方法和电机驱动器,属于电路控制技术领域。所述双核处理器包括第一核和第二核,所述方法包括：所述第一核接收来自电机驱动测试系统的测试启动命令；所述第一核根据所述测试启动命令,确定测试类型、测试指标和测试时间；所述第一核根据所述测试类型、所述测试指标和所述测试时间,生成测试指令并向所述第二核发送所述测试指令；所述第一核接收来自所述第二核的所述测试指令对应的测试结果；所述第一核将所述测试结果返回给所述电机驱动测试系统。本发明提供一种基于双核处理器的电机驱动测试方法和电机驱动器,使得测试得到的结果可能与电机正常运行时的数据保持一致,从而提高电机驱动测试的准确度。(The invention relates to a motor drive test method based on a dual-core processor and a motor driver, and belongs to the technical field of circuit control. The dual-core processor includes a first core and a second core, the method comprising: the first core receives a test starting command from a motor drive test system; the first core determines a test type, a test index and test time according to the test starting command; the first core generates a test instruction according to the test type, the test index and the test time and sends the test instruction to the second core; the first core receives a test result corresponding to the test instruction from the second core; and the first core returns the test result to the motor drive test system. The invention provides a motor drive test method based on a dual-core processor and a motor driver, so that the result obtained by testing can be consistent with the data of a motor in normal operation, and the accuracy of the motor drive test is improved.)

1. A motor driving test method based on a dual-core processor, wherein the dual-core processor comprises a first core and a second core, and the motor driving test method is characterized by comprising the following steps:

the first core receives a test starting command from a motor drive test system;

the first core determines a test type, a test index and test time according to the test starting command;

the first core generates a test instruction according to the test type, the test index and the test time and sends the test instruction to the second core;

the first core receives a test result corresponding to the test instruction from the second core;

and the first core returns the test result to the motor drive test system.

2. The motor drive test method according to claim 1,

the first core receives a test start command from a motor drive test system, including:

a first intellectual property core preset in the dual-core processor receives a test starting command of the motor drive test system through a preset interface;

and the first intellectual property core sends the test starting command to the first core through a preset bus protocol.

3. The motor drive test method according to claim 2,

the first core returns the test result to the motor drive test system, including:

the first core sends the test result to the first intellectual property core through the bus protocol;

and the first intellectual property core sends the test result to the motor drive test system through the interface.

4. The motor drive test method according to claim 1,

after the first core sends a test instruction to the second core, the method further comprises:

the second core generates a control output signal according to the test instruction;

the second core sends the control output signal to a second intellectual property core preset in the dual-core processor;

and the second intellectual property core converts the control output signal into a corresponding electric signal and transmits the electric signal corresponding to the control output signal to an amplifying circuit of a driving circuit.

5. The motor drive test method according to claim 1,

before the first core is to receive a test result corresponding to the send test instruction from the second core, the method further includes:

a third intellectual property core preset in the dual-core processor receives the electric signal sent by the driving circuit;

the third intellectual property core converts the received electrical signals into the test results;

the third intellectual property core sends the test result to the second core;

the second core sends the test result to the first core.

6. The motor drive test method according to claim 1,

the first core determines a test type, a test index and test time according to the test starting command, and the method comprises the following steps:

the first core analyzes the test starting command to obtain test starting information which can be read by the first core;

and the first core determines the test type, the test index and the test time according to the test starting information.

7. The motor drive test method according to claim 1,

the first core generates a test instruction according to the test type, the test index and the test time, and the method comprises the following steps:

the first core determines a timed interrupt cycle and an instruction type of the test instruction according to the test type, wherein the instruction type comprises: one or more of a triangle wave command, a sine wave command, and a step command;

the first core determines the amplitude required by generating the test instruction according to the test index;

the first core determines the number of interrupt cycles according to the test time, the timed interrupt cycle and the instruction type;

and the first core generates the test instruction according to the instruction type, the amplitude required by generating the test instruction and the number of the interrupt cycles.

8. A motor driver based on a dual-core processor is characterized in that,

the motor driver includes: a first core, a second core and a drive circuit;

the first core is used for receiving a test starting command from the motor drive test system; determining a test type, a test index and test time according to the test starting command; generating a test instruction according to the test type, the test index and the test time, and sending the test instruction to the second core;

the second core is used for generating a control output signal according to the test instruction; converting the control output signal into a corresponding electric signal, and transmitting the electric signal corresponding to the control output signal to the driving circuit; receiving an electric signal returned by the driving circuit; converting the returned electrical signal into a test result; returning the test result to the first core;

the first core is further configured to receive a test result corresponding to the sending test instruction from the second core; and returning the test result to the motor drive test system.

9. The motor driver of claim 8,

the motor driver further includes: a first intellectual property core;

the first intellectual property core is used for receiving a test starting command of the motor drive test system through a preset interface; and sending the test starting command to the first core through a preset bus protocol.

10. The motor driver of claim 8,

the motor driver further includes: a second intellectual property core and a third intellectual property core;

the second intellectual property core is used for receiving a control output signal sent by the second core; converting the control output signal into a corresponding electric signal, and transmitting the electric signal corresponding to the control output signal to an amplifying circuit of the driving circuit;

the third intellectual property core is used for receiving the electric signal sent by the driving circuit; converting the received electrical signal into the test result; and sending the test result to the second core.

Technical Field

The invention relates to the technical field of circuit control, in particular to a motor drive testing method and a motor driver based on a dual-core processor.

Background

In order to meet the increasing demands of users, at present, a dual-core processor is adopted for many motors, wherein one core in the dual-core processor serves as a main control core, and the other core serves as a motor driving core.

The existing motor drive test method specifically includes that a motor drive test system sends test instructions to a motor driver through a test interface, and the motor driver executes the test instructions and feeds test results back to the motor drive test system.

In the testing process, the command issued to the motor driver is a motor driving testing system, but in actual use, the command issued to the motor driver is used as a main controller. The working modes and principles of the main controller and the motor drive test system are different, so that the result obtained by the test is possibly inconsistent with the data of the motor in normal operation, and the accuracy of the motor drive test is reduced.

Disclosure of Invention

In view of the foregoing analysis, the present invention aims to provide a motor drive test method and a motor driver based on a dual-core processor, so that the result obtained by the test may be consistent with the data when the motor normally operates, thereby improving the accuracy of the motor drive test.

The purpose of the invention is mainly realized by the following technical scheme:

in a first aspect, an embodiment of the present invention provides a motor driving test method based on a dual-core processor, where the dual-core processor includes a first core and a second core, and includes:

the first core receives a test starting command from a motor drive test system;

the first core determines a test type, a test index and test time according to the test starting command;

the first core generates a test instruction according to the test type, the test index and the test time and sends the test instruction to the second core;

the first core receives a test result corresponding to the test instruction from the second core;

and the first core returns the test result to the motor drive test system.

Further, the first core receives a test start command from a motor drive test system, including:

a first intellectual property core preset in the dual-core processor receives a test starting command of the motor drive test system through a preset interface;

and the first intellectual property core sends the test starting command to the first core through a preset bus protocol.

Further, the first core returns the test result to the motor drive test system, including:

the first core sends the test result to the first intellectual property core through the bus protocol;

and the first intellectual property core sends the test result to the motor drive test system through the interface.

Further, after the first core sends a test instruction to the second core, the method further comprises:

the second core generates a control output signal according to the test instruction;

the second core sends the control output signal to a second intellectual property core preset in the dual-core processor;

and the second intellectual property core converts the control output signal into a corresponding electric signal and transmits the electric signal corresponding to the control output signal to an amplifying circuit of a driving circuit.

Further, before the first core is to receive a test result corresponding to the sending test instruction from the second core, the method further includes:

a third intellectual property core preset in the dual-core processor receives the electric signal sent by the driving circuit;

the third intellectual property core converts the received electrical signals into the test results;

the third intellectual property core sends the test result to the second core;

the second core sends the test result to the first core.

Further, the determining, by the first core, the test type, the test index, and the test time according to the test start command includes:

the first core analyzes the test starting command to obtain test starting information which can be read by the first core;

and the first core determines the test type, the test index and the test time according to the test starting information.

Further, the generating, by the first core, a test instruction according to the test type, the test index, and the test time includes:

the first core determines a timed interrupt cycle and an instruction type of the test instruction according to the test type, wherein the instruction type comprises: one or more of a triangle wave command, a sine wave command, and a step command;

the first core determines the amplitude required by generating the test instruction according to the test index;

the first core determines the number of interrupt cycles according to the test time, the timed interrupt cycle and the instruction type;

and the first core generates the test instruction according to the instruction type, the amplitude required by generating the test instruction and the number of the interrupt cycles.

In a second aspect, an embodiment of the present application provides a motor driver based on a dual-core processor, where the motor driver includes: a first core, a second core and a drive circuit;

the first core is used for receiving a test starting command from the motor drive test system; determining a test type, a test index and test time according to the test starting command; generating a test instruction according to the test type, the test index and the test time, and sending the test instruction to the second core;

the second core is used for generating a control output signal according to the test instruction; converting the control output signal into a corresponding electric signal, and transmitting the electric signal corresponding to the control output signal to the driving circuit; receiving an electric signal returned by the driving circuit; converting the returned electrical signal into a test result; returning the test result to the first core;

the first core is further configured to receive a test result corresponding to the sending test instruction from the second core; and returning the test result to the motor drive test system.

Further, the motor driver further includes: a first intellectual property core;

the first intellectual property core is used for receiving a test starting command of the motor drive test system through a preset interface; and sending the test starting command to the first core through a preset bus protocol.

Further, the motor driver further includes: a second intellectual property core and a third intellectual property core;

the second intellectual property core is used for receiving a control output signal sent by the second core; converting the control output signal into a corresponding electric signal, and transmitting the electric signal corresponding to the control output signal to an amplifying circuit of the driving circuit;

the third intellectual property core is used for receiving the electric signal sent by the driving circuit; converting the received electrical signal into the test result; and sending the test result to the second core.

The technical scheme of the invention has the beneficial effects that: the invention discloses a motor drive testing method based on a dual-core processor and a motor driver. In addition, the data interaction function of the main control core and the motor drive test system is independently integrated on an intellectual property core, and the interaction function of the motor drive core and the drive circuit is independently integrated on at least one intellectual property core, so that the program running time of the main control core and the motor drive core is compressed, and the signal transmission delay of the test system is reduced.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.

Fig. 1 is a schematic structural diagram of a motor driver in the prior art provided by the present invention;

fig. 2 is a flowchart of a motor drive testing method based on a dual-core processor according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a master core according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a connection structure between a motor drive core and an IP core according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a motor driver according to an embodiment of the present invention.

Detailed Description

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.

In the prior art, as shown in fig. 1, a dual-core processor is provided in a motor control, two cores of the processor are respectively denoted as a core 1 and a core 2, where the core 1 is provided with a master control software for controlling the whole motor as a master control core, and the core 2 is only used for controlling a motor driving circuit as a motor driving core. During testing, the motor drive test system directly sends a test instruction to the core 2 through the communication interface. The core 2 acquires data obtained after the motor driving circuit executes the command after executing the command, and returns the acquired data to the motor testing system through the communication interface. In principle, the method is based on a detection method in which the motor processor is a single core.

For a single-core processor, the processor needs to receive instructions from an external system both in actual use and in testing, and therefore the operating state of the processor in testing is the same as that in use.

For a dual-core processor, when in actual use, the core 1 serving as a main control core inevitably sends instructions to the core 2 according to the overall operation state of the motor in the operation process so as to adjust various operation parameters of the motor in real time. At this time, if the motor test system still sends an instruction to the core 2, the operating state of the core 2 during the test is inevitably different from the operating state in actual use, so that the test result is inaccurate, and even potential safety hazards are buried for later use.

Specifically, when a response test is carried out, whether the motor driver can rapidly adjust the working state of the motor according to an algorithm when the load changes is observed by applying different loads to the motor, and the response performance of the driver is evaluated. For the prior art, the drive test system can only send preset instructions to the core 2, and the instructions cannot be adjusted in real time according to the overall running condition of the motor, so that the test result is different from the actual use state. For example, in practical use, due to the limitation condition set by the built-in program in the master core, the response performance of the driver is the best when the load is less than a. If the instruction is directly sent to the core 2 by the drive test system, which means that there is no limitation set by the built-in program in the main control core, when the load is greater than a, the response performance is still probably the best. Once the daily work of the driver is guided by the test result, it is likely to cause the circuit overload, and further cause various uncertain accidents, thereby causing the equipment damage and even causing safety accidents.

To this end, an embodiment of the present invention provides a motor drive test method based on a dual-core processor, as shown in fig. 2, including the following steps:

in step 201, a first core receives a test start command from a motor drive test system.

In the embodiment of the invention, a ZYNQ dual-core processor is adopted as the processor of the motor and comprises a first core and a second core. The core 1 corresponding to the first core is a master control core, and the core 2 corresponding to the second core is a drive control core. The first core connects the communication pin to a port with a corresponding communication function in the ZYNQ, and needs to initialize functions, working modes, enabling, bottom layer driving and the like of the communication port in an initialization process, so that the first core has the communication function and can call a bottom layer driving function.

Step 202, the first core determines a test type, a test index and test time according to the test starting command.

In the embodiment of the present invention, in view of that the protocols, algorithms, or data formats used by the first core and the motor drive test system may be different, when receiving the test start command, the first core needs to parse the test start command to obtain the test start information that can be read by the first core. And the first core determines the test type, the test index and the test time according to the test starting information. Wherein the test types include one or more of driver efficiency, harmonic analysis, three-phase imbalance degree analysis, interference analysis, and response testing.

And step 203, the first core generates a test instruction according to the test type, the test index and the test time and sends the test instruction to the second core.

In the embodiment of the invention, the first core needs to generate a test instruction in the test process so as to realize that the core 1 controls the core 2 to complete the test, thereby realizing that the working state of the core 2 is matched with the use state, and finally improving the accuracy of the motor drive test.

Specifically, the first core determines a timer interrupt cycle and an instruction type of the test instruction according to the test type, where the instruction type includes: one or more of a triangle wave command, a sine wave command, and a step command. And the first core determines the amplitude required by generating the test instruction according to the test index. And the first core determines the number of the interrupt middle period according to the test time, the timed interrupt period and the instruction type. And the first core generates a test instruction according to the instruction type, the amplitude required by generating the test instruction and the number of interrupt cycles.

In embodiments of the present invention, a timed interrupt cycle is used for instruction generation. The mathematical expression of the triangular wave test instruction is as follows:

y＝kt

in the formula, y represents a triangular wave command amplitude, k represents a triangular wave command slope, and t represents a test time. Accordingly, the triangular wave instruction generation process can be represented by the following equation:

y＝nkΔt

in the formula, Δ t represents the period of timer interruption, and n represents the number of timer interruptions counted.

The sine wave test instruction mathematical expression is as follows:

y＝A sin(2πft)

in the formula, t represents a test time, y represents a sine wave command at the time t, a represents a sine wave amplitude, and f represents a sine wave test command frequency. Accordingly, the sine wave command generation process can be represented by the following equation:

y＝A sin(nΔt×2πf)

in the formula, Δ t represents the period of timer interruption, and n represents the number of timer interruptions counted.

Therefore, compared with the prior art in which a module for generating a test instruction is integrated on the first core, in the embodiment of the present invention, the motor drive test system does not need to be provided with a module for generating a test instruction, so that the software scale of the motor drive test system is reduced.

The module for generating the test command is arranged on the first core, which may cause the first core to have time delay during operation, and is not beneficial to the control of the motor by the first core. In order to improve the operation efficiency of the first core and the running time of the compression program, in the embodiment of the invention, a first intellectual property core (IP core) is arranged in the dual-core processor in advance, one end of the first IP core is connected with the motor drive test system through a preset Interface, and the other end of the first IP core is connected through a bus protocol, wherein the bus protocol comprises an AXI (Advanced eXtensible Interface). The first IP core is a circuit function module designed by an FPGA (Field-Programmable Gate Array) in a ZYNQ dual-core processor.

During testing, the first core originally receives and sends data through the read and write registers in the ARM core to receive the test start command and return the test result, as shown in fig. 3. After the first IP core is arranged, the first IP core is in butt joint with the motor drive test system so as to replace a read register and a write register in the ARM core to receive a test starting command and return a test result. Therefore, the first IP core is arranged, so that the operation efficiency and the running time of the compression program of the first core are improved by reducing the data processing amount of the first core.

In step 204, the first core receives a test result corresponding to the test instruction from the second core.

In the embodiment of the invention, the second core generates the control output signal according to the test instruction, converts the control output signal into a corresponding electric signal, and sends the electric signal to the amplifying circuit of the driving circuit. And finally, converting the electric signal returned by the driving circuit into a test result and returning the test result to the first core.

In order to improve the operation efficiency of the second core and the running time of the compression program, the second IP core and the third IP core are preset in the ZYNQ dual-core processor. The second IP core is used for replacing the second core to convert the control output signal into a corresponding electric signal and transmitting the electric signal corresponding to the control output signal to the amplifying circuit of the driving circuit. And the third IP core is used for replacing the second core to receive the electric signal sent by the driving circuit and converting the received electric signal into a test result. It should be noted that a plurality of third IP cores may be provided depending on the circuit configuration. The second IP core and the third IP core respectively perform data interaction with the second core through a bus protocol, and the bus comprises an AXI.

Specifically, as shown in fig. 4, the PWM (Pulse width modulation) output IP core is the second IP core, and both the current collection IP core and the counter IP core are the third IP cores. The drive circuit includes an amplifying circuit, a current sampling circuit, and a counter circuit. Pulse width modulation) output IP core is corresponding to an amplifying circuit during testing, a current collecting IP core is corresponding to a current sampling circuit, and a counter IP core is corresponding to a counter circuit. The IP cores shown in FIG. 4 are all circuit functional modules designed by FPGA in a ZYNQ dual-core processor.

Each IP core carries out data interaction with the core 2 through an AXI bus, the core 2 acquires information such as current, a counter and the like through the current acquisition IP core and the counter IP core and then synthesizes the information with a test instruction to obtain a control output signal PWM, the core 2 outputs the control output signal PWM to the PWM output IP core through the AXI bus, and the PWM output IP core outputs the information to an amplifying circuit in an electric signal mode, so that closed-loop control of the motor is realized.

And step 205, the first core returns the test result to the motor drive test system.

In the embodiment of the invention, the first core firstly sends the test result to the first IP core through the bus, and then the first IP core sends the test result to the motor drive test system.

As shown in fig. 5, an embodiment of the present invention provides a motor driver including: a first core 501, a second core 502, a driving circuit 503, a first intellectual property core 504, a second intellectual property core 505 and a third intellectual property core 506.

The first core 501 is used for receiving a test start command from a motor drive test system; determining a test type, a test index and test time according to the test starting command; and generating a test instruction and sending the test instruction to the second core according to the test type, the test index and the test time.

The second core 502 is configured to generate a control output signal according to the test instruction; converting the control output signal into a corresponding electrical signal, and transmitting the electrical signal corresponding to the control output signal to the driving circuit 503; receive the electrical signal returned by the driving circuit 503; converting the returned electric signal into a test result; the test results are returned to the first core 501.

The first core 501 is further configured to receive a test result corresponding to the sending test instruction from the second core 502; and returning the test result to the motor drive test system.

The first intellectual property core 504 is configured to receive a test start command of the motor drive test system through a preset interface; the test start command is sent to the first core 501 through a preset bus protocol.

The second intellectual property core 505 is configured to receive the control output signal sent by the second core 502; the control output signal is converted into a corresponding electrical signal, and the electrical signal corresponding to the control output signal is transmitted to the amplifying circuit of the driving circuit 503.

The third intellectual property core 506 is used for receiving the electric signal sent by the driving circuit; converting the received electrical signal into a test result; the test results are sent to the second core 502.

The first intellectual property core 504, the second intellectual property core 505 and the third intellectual property core 506 are all circuit functional modules designed by an FPGA in a ZYNQ dual-core processor.

Those skilled in the art will appreciate that all or part of the processes for implementing the methods in the above embodiments may be implemented by a computer program, which is stored in a computer-readable storage medium, to instruct associated hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.