阅读说明：本技术 使用异质电源的带隙基准电路和具有该电路的电子设备 (Band gap reference circuit using heterogeneous power source and electronic device having the same ) 是由 金敬珉 薛亥植 姜旋律 金允洪 徐丞民 李炫知 郑演焕 于 2021-04-01 设计创作，主要内容包括：本发明公开了一种带隙基准电路,包括：第一电流发生器,被配置为生成与温度成比例的第一电流；第二电流发生器,被配置为将通过对第一电流进行镜像而获得的第二电流输出到形成参考电压的第一节点；第一电阻器,该第一电阻器与第一节点连接并被提供有第二电流；以及第一双极结型晶体管(BJT),该第一BJT包括与第一电阻器连接的发射极节点、被提供有第一电源的基极节点、以及被提供有与第一电源不同的第二电源的集电极节点。(The invention discloses a band gap reference circuit, comprising: a first current generator configured to generate a first current proportional to temperature; a second current generator configured to output a second current obtained by mirroring the first current to a first node forming a reference voltage; a first resistor connected to the first node and supplied with a second current; and a first Bipolar Junction Transistor (BJT) including an emitter node connected to the first resistor, a base node supplied with a first power source, and a collector node supplied with a second power source different from the first power source.)

1. A bandgap reference circuit comprising:

a first current generator configured to generate a first current proportional to temperature;

a second current generator configured to output a second current obtained by mirroring the first current to a first node forming a reference voltage;

a first resistor connected with a first node and supplied with a second current; and

a first Bipolar Junction Transistor (BJT) including an emitter node connected to the first resistor, a base node supplied with a first power source, and a collector node supplied with a second power source different from the first power source.

2. The bandgap reference circuit of claim 1, wherein the first power supply is an analog ground for signal processing in the analog domain.

3. The bandgap reference circuit of claim 1, wherein said second power supply is a digital ground for signal processing in the digital domain.

4. The bandgap reference circuit of claim 1, wherein a base node of the first BJT is connected to a first pad and a collector node of the first BJT is connected to a second pad.

5. The bandgap reference circuit of claim 4, wherein the first pad is connected to a first pin of an interface module by a first pad bond,

wherein the second pad is connected to a second pin of the interface module by a second pad bond,

wherein the first pin is connected to the common ground of the setup module via the first pin, an

Wherein the second pin is connected to the common ground of the setup module via the second pin.

6. The bandgap reference circuit of claim 1, wherein said first current generator comprises:

a second BJT including an emitter node connected to a second node;

a second resistor connected with a third node;

a third BJT comprising an emitter node connected to the second resistor;

an amplifier configured to amplify a difference between a voltage of the second node and a voltage of the third node and output the amplified result to a fourth node;

a first transistor connected between a power supply node and the second node and configured to operate in response to a voltage of the fourth node; and

a second transistor connected between the power supply node and the third node and configured to output the first current in response to a voltage of the fourth node.

7. The bandgap reference circuit of claim 6, wherein said second current generator comprises:

a third transistor connected between the power supply node and the first node and configured to output the second current in response to a voltage of the fourth node.

8. The bandgap reference circuit of claim 6, wherein the second BJT comprises a base node provided with the first power supply and a collector node provided with the second power supply, an

Wherein the third BJT includes a base node provided with the first power supply and a collector node provided with the second power supply.

9. The bandgap reference circuit of claim 8, wherein the first through third BJTs are PNP type BJTs.

10. The bandgap reference circuit of claim 1, further comprising:

a current source configured to output a reference current based on a reference voltage of the first node.

11. An electronic device, comprising:

a Bipolar Junction Transistor (BJT) formed at a semiconductor substrate; and

a digital circuit formed at the semiconductor substrate and configured to operate in a digital domain,

wherein the BJT includes:

a collector node connected to the semiconductor substrate and sharing a first power supply with a digital node of the digital circuit;

a base node connected to a first conductive region formed by implanting first impurities into the semiconductor substrate and supplied with a second power supply different from the first power supply; and

an emitter node connected to a second conductive region formed by implanting a second impurity into the first conductive region, and connected to a resistor supplied with a current proportional to a temperature from the mirror current generator.

12. The electronic device of claim 11, wherein the first power supply is a digital ground for signal processing in the digital domain, and

wherein the second power supply is an analog ground for signal processing in the analog domain.

13. The electronic device of claim 11, further comprising:

a first pad connected to a collector node of the BJT and configured to receive the first power supply from a first pin; and

a second pad connected with a base node of the BJT and configured to receive the second power supply from a second pin.

14. The electronic device according to claim 11, wherein the semiconductor substrate is a P-type semiconductor substrate, the first impurity is an N-type impurity, and the second impurity is a P-type impurity.

15. An electronic device, comprising:

a first circuit configured to operate based on a first power source;

a second circuit configured to operate based on a second power supply different from the first power supply; and

a bandgap reference circuit configured to generate a reference voltage for operation of the first and second circuits based on the first and second power supplies,

wherein the bandgap reference circuit comprises:

a first current generator configured to generate a first current proportional to temperature;

a second current generator configured to output a second current obtained by mirroring the first current to a first node forming a reference voltage;

a first resistor connected with a first node and supplied with a second current; and

a Bipolar Junction Transistor (BJT) comprising an emitter node connected to the first resistor, a base node supplied with the first power supply, and a collector node supplied with the second power supply.

16. The electronic device of claim 15, wherein the first power supply is a digital ground for signal processing in the digital domain, and

wherein the second power supply is an analog ground for signal processing in the analog domain.

17. The electronic device of claim 15, further comprising:

a third circuit configured to operate based on the first power supply, the second power supply, and the reference voltage.

18. The electronic device of claim 15, further comprising:

a first pad connected to a base node of the BJT and the first circuit and configured to receive the first power supply from a first pin of an interface module; and

a second pad connected to a collector node of the BJT and the second circuit, and configured to receive the second power supply from a second pin of the interface module.

19. The electronic device of claim 15, wherein the bandgap reference circuit further comprises:

a first current source configured to output a first reference current based on the reference voltage; and

a second current source configured to output a second reference current based on the reference voltage.

20. The electronic device of claim 19, further comprising:

a pixel voltage generator configured to output a pixel voltage based on the reference voltage and the first reference current;

a ramp generator configured to output a ramp power supply based on the second reference current;

a pixel array driven based on the pixel voltage and configured to output a plurality of image signals; and

a plurality of comparators configured to compare the plurality of image signals with the ramp power supply, respectively, to output a plurality of comparison signals, respectively.

Technical Field

Example embodiments of the present disclosure relate to a bandgap reference circuit, and more particularly, to a bandgap reference circuit based on a heterogeneous power supply (two or more different types of power supplies) driving transistors and an electronic device including the same.

Background

Semiconductor devices may include various circuits for generating, processing, or storing data. The circuits of the semiconductor device may operate based on a reference voltage supplied from an external power supply or any other circuit. For example, the reference voltage may vary depending on external factors such as temperature. The semiconductor device may include a bandgap reference circuit for reducing or preventing abnormal operation of a circuit of the semiconductor device and ensuring reliability thereof. A bandgap reference circuit is a circuit that generates a reference voltage that is insensitive to process-voltage-temperature (PVT) (or PVT variations).

Within one semiconductor chip, a bandgap reference circuit may be affected by noise from the circuit, with the circuit and bandgap reference circuit sharing the same substrate. In particular, with high integration and miniaturization of semiconductor chips, the influence of noise on the bandgap reference circuit increases. Therefore, a method capable of improving the reliability of the bandgap reference circuit is required.

Disclosure of Invention

Example embodiments of the present disclosure provide a bandgap reference circuit that is insensitive to PVT, reduces noise, and improves reliability of a reference voltage by applying heterogeneous power supplies (e.g., analog and digital power supplies) to transistors of the bandgap reference circuit, and an electronic device including the bandgap reference circuit.

According to an example embodiment, a bandgap reference circuit includes: a first current generator generating a first current proportional to temperature; a second current generator that outputs a second current obtained by mirroring the first current to a first node forming a reference voltage; a first resistor connected to the first node and supplied with a second current; and a first Bipolar Junction Transistor (BJT) including an emitter node connected to the first resistor, a base node supplied with a first power source, and a collector node supplied with a second power source different from the first power source.

According to an example embodiment, an electronic device includes: a Bipolar Junction Transistor (BJT) formed at a semiconductor substrate; and a digital circuit formed at the semiconductor substrate and operating in a digital domain. The BJT includes: a collector node connected to the semiconductor substrate and sharing the first power supply with a digital node of the digital circuit; a base node connected to a first conductive region formed by implanting first impurities into a semiconductor substrate and supplied with a second power supply different from the first power supply; and an emitter node connected to a second conductive region formed by implanting a second impurity into the first conductive region, and connected to a resistor supplied with a current proportional to a temperature from the mirror current generator.

According to an example embodiment, an electronic device includes: a first circuit operating based on a first power supply; a second circuit operating based on a second power supply different from the first power supply; and a bandgap reference circuit generating a reference voltage for operation of the first circuit and the second circuit based on the first power supply and the second power supply. The bandgap reference circuit includes: a first current generator generating a first current proportional to temperature; a second current generator that outputs a second current obtained by mirroring the first current to a first node forming a reference voltage; a first resistor connected to the first node and supplied with a second current; and a Bipolar Junction Transistor (BJT) including an emitter node connected to the first resistor, a base node supplied with the first power source, and a collector node supplied with the second power source.

Drawings

The above and other objects and features of the present disclosure will become apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a block diagram illustrating an electronic device according to an example embodiment of the present disclosure.

Fig. 2 is a block diagram illustrating in detail an electronic system including the electronic device of fig. 1.

Fig. 3 is a block diagram illustrating the bandgap reference circuit of fig. 1 in detail.

Fig. 4 is a circuit diagram showing the bandgap reference circuit of fig. 3 in detail.

Fig. 5 is a diagram for describing an electronic apparatus to which a heterogeneous power source is applied from a setup module.

Fig. 6 is a diagram illustrating the electronic apparatus of fig. 5 in detail.

Fig. 7 is a diagram illustrating in detail an electronic device according to an example embodiment.

Fig. 8 is a diagram illustrating in detail an electronic device according to an example embodiment.

Fig. 9 is a block diagram illustrating in detail an electronic system according to an example embodiment of the present disclosure.

Fig. 10 is a circuit diagram showing the bandgap reference circuit of fig. 9 in detail.

Fig. 11 is a diagram illustrating the electronic apparatus of fig. 9 in detail.

Fig. 12 is a graph showing PTAT current measured at a bandgap reference circuit that introduces DC noise.

Fig. 13 is a graph showing the distribution of a reference voltage at a bandgap reference circuit in which DC noise is introduced.

Fig. 14 is a graph showing the standard deviation of a reference voltage at a bandgap reference circuit that introduces DC noise.

Fig. 15 is a graph showing gain and phase at a bandgap reference circuit that introduces AC noise.

Fig. 16A and 16B are graphs showing waveforms of reference voltages at a bandgap reference circuit to which AC noise is introduced.

Fig. 17 is a block diagram illustrating an image sensor device according to an example embodiment of the present disclosure.

Fig. 18 is a block diagram illustrating an electronic system according to an example embodiment of the present disclosure.

Detailed Description

Hereinafter, example embodiments of the present disclosure may be described in detail and clearly so that those skilled in the art can easily implement the present disclosure. Hereinafter, for convenience of description, similar components are denoted by using the same or similar reference numerals.

In the following drawings or detailed description, a module may be shown in the drawings or may be connected with any other component except for the components in the specific embodiment. Modules or components may be connected directly or indirectly. Modules or components may be connected by communications or may be physically connected.

Fig. 1 is a block diagram illustrating an electronic device ED according to an example embodiment of the present disclosure. Referring to fig. 1, an electronic device ED that generates a data signal based on power supplied from an external module (not shown) is shown. For example, the electronic device ED may be an electronic device comprised in a device such as a computer, a laptop, a smart phone, a digital camera or a tablet.

Electronic device ED may include bandgap reference circuit 10, analog circuit 20, digital circuit 30, and/or analog and digital circuit 40, and may be provided with analog ground AGND, digital ground DGND, and power supply voltage V by an external module_SS. The electronic device ED may output a data signal based on the operation of the internal circuits 10, 20, 30, and/or 40. For example, the data signal may include at least one of the following various information: such as images, video, sound, text, location and distance.

For example, analog ground AGND may be a signal used for signal processing in the analog domain. For example, analog ground AGND may be a ground voltage in the analog domain. Digital ground DGND may be a signal used for signal processing in the digital domain. For example, digital ground DGND may be the ground voltage in the digital domain.

In an example embodiment, the noise of digital ground DGND may be different from the noise of analog ground AGND. For example, digital ground DGND may be connected to circuitry of the digital domain; since noise from the operation of the circuitry of the digital domain is introduced to digital ground DGND, the noise of digital ground DGND may be generated more frequently or more than the noise of analog ground AGND. For example, the noise of the digital ground DGND may be noise of a DC component or noise of an AC component.

The bandgap reference circuit 10 may generate a reference voltage V_REFThe circuit of (1). Reference voltage V_REFMay be a bandgap reference voltage. Reference voltage V_REFMay be a voltage for operation of at least one of the analog circuit 20, the digital circuit 30, and the analog and digital circuits 40. For example, in the case where analog circuit 20 is a comparator that determines whether an input value exceeds a reference value, reference voltage V is set_REFMay be a reference value provided to the comparator.

At a reference voltage V_REFIn the case where the value is different from the value expected at the time of design, the electronic device ED may operate abnormally or may output an incorrect data signal. In order to ensure reliability of a data signal output from the electronic device ED, the bandgap reference circuit 10 needs to have strong characteristics in terms of external factors (e.g., temperature variation, noise, or leakage current). That is, the bandgap reference circuit 10 may need to generate a reference voltage V that is insensitive to process-voltage-temperature (PVT) (or PVT variations)_REF. This will be described more fully with reference to fig. 3.

The analog circuitry 20 may be circuitry operating in the analog domain. For example, the analog circuit 20 may be based on the power supply voltage V_SSAnd analog ground AGND. The digital circuit 30 may be a circuit operating in the digital domain. For example, the digital circuit 30 may be based on the power supply voltage V_SSAnd digital ground DGND. The analog and digital circuits 40 may be circuits operating in the analog and digital domains. For example, analog and digital circuitry 40 may be based on power supply voltage V_SSAnalog ground AGND, and digital ground DGND. For example, analog and digital circuits 40 may be circuits such as analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.

In an example embodiment, electronic device ED may output based on the operation of at least one of analog circuitry 20, digital circuitry 30, and analog and digital circuitry 40And outputting the data signal. For example, it may be based on a reference voltage V_REFTo output a data signal. In order to ensure the reliability of the data signal output from the electronic device ED, it is necessary to generate a reference voltage V insensitive to PVT_REFThe bandgap reference circuit 10.

Fig. 2 is a block diagram illustrating in detail an electronic system ES including the electronic device ED of fig. 1. Referring to fig. 2, the electronic system ES may be connected with the setting module SM through a pin connection. The electronic system ES may be a system that performs a specific operation. For example, the electronic system ES may be a device such as a computer, a laptop computer, a smart phone, a digital camera, or a tablet computer.

The electronic system ES may comprise an electronic device ED and an interface module IM. The electronic device ED may comprise a bandgap reference circuit 10, an analog circuit 20, a digital circuit 30, an analog and digital circuit 40, a first pad (pad 1) and/or a second pad (pad 2). Since the bandgap reference circuit 10, the analog circuit 20, the digital circuit 30, and the analog and digital circuits 40 have been described with reference to fig. 1, they will not be described again.

The electronic device ED may be connected to the interface module IM via a first pad (pad) and a second pad. The electronic device ED may receive a first power source through the first pad and a second power source through the second pad.

In an example embodiment, the first power received through the first pad may be applied to the bandgap reference circuit 10, the analog circuit 20, and the analog and digital circuits 40. For example, the first power supply may be analog ground AGND.

In an example embodiment, the second power received through the second pad may be applied to the digital circuit 30 and the analog and digital circuits 40. For example, the second power supply may be digital ground DGND.

The interface module IM may comprise a first pin and a second pin. The first pin may be connected with a first pad of the electronic device ED by a first pad bond. The second pin may be connected with a second pad of the electronic device ED by a second pad bond. That is, in the electronic system ES, analog ground AGND and digital ground DGND may be sent through separate paths.

However, the interface module IM according to an example embodiment of the present disclosure is not limited thereto. For example, the interface module IM may also comprise means for transmitting a power supply voltage V such as that of fig. 1_SSSuch as a signal pin (e.g., a third pin). That is, the interface module IM may be a module that receives a signal such as power or data from or outputs a signal such as power or data to the outside of the electronic system ES.

The setup module SM may be a module providing a common ground CGND to the electronic system ES. The common ground CGND may be a power source used in the electronic system ES. For example, common ground CGND may be a voltage used as a reference to generate grounds AGND and DGND within electronic system ES.

In an example embodiment, the first pin of the interface module IM may be connected with the common ground CGND of the setup module SM by a first pin connection. A second pin of the interface module IM may be connected to the common ground CGND of the setup module SM via a second pin connection. That is, the electronic system ES may receive the power corresponding to the analog ground AGND and the power corresponding to the digital ground DGND through different paths.

Fig. 3 is a block diagram illustrating the bandgap reference circuit 10 of fig. 1 in detail. Referring to fig. 3, the bandgap reference circuit 10 may include a Proportional To Absolute Temperature (PTAT) current generator 11, a mirror current generator 12, and/or a reference voltage generator 13.

The PTAT current generator 11 may generate a PTAT current I_PTAT. PTAT current I_PTATMay be a current whose amplitude increases in proportion to the absolute temperature. The mirror current generator 12 may be electrically connected to the PTAT current generator 11. The current generator 12 may be coupled to the PTAT current I of the PTAT current generator 11_PTATThe mirroring is performed. That is, the mirror current generator 12 may generate a mirror PTAT current I_PTAT。

The reference voltage generator 13 may receive the mirrored PTAT current I from the mirrored current generator 12_PTATThe reference voltage generator 13 may include a semiconductor device having a voltage inversely proportional to an absolute temperature. The reference voltage generator 13 may be mirror basedLike PTAT current I_PTATAnd the characteristics of the semiconductor device to generate a reference voltage V which is insensitive to absolute temperature_REF。

For example, in the case of an increase in absolute temperature, the PTAT current I is mirrored_PTATMay be increased and the voltage of the semiconductor device may be decreased. Therefore, the influence due to the increase in absolute temperature can be cancelled out. Conversely, with a decreasing absolute temperature, the voltage of the semiconductor device may increase while mirroring the PTAT current I_PTATCan be reduced. Therefore, the influence due to the decrease in absolute temperature can be cancelled out. This will be described more fully with reference to fig. 4.

Fig. 4 is a circuit diagram showing the bandgap reference circuit 10 of fig. 3 in detail. Referring to fig. 4, the bandgap reference circuit 10 may include a PTAT current generator 11, a mirror current generator 12, and a reference voltage generator 13.

The PTAT current generator 11 may include a first resistor R1, transistors Q1, Q2, M1 and M2, and/or an amplifier AMP. Can provide a power supply voltage V_SSAnd ground GND to PTAT current generator 11. In an example embodiment, each of the transistors Q1 and Q2 may be a Bipolar Junction Transistor (BJT). For example, the transistors Q1 and Q2 may be PNP type BJTs, but the disclosure is not limited thereto. For example, transistors Q1 and Q2 may be NPN type BJTs.

The transistor Q1 may be connected at a first input node N₁₁And ground GND, and may operate in response to ground GND. For example, the transistor Q1 may include a first input node N₁₁A connected emitter node and a base node and a collector node connected to ground GND.

The transistor Q2 may be connected between the first resistor R1 and the ground GND, and may operate in response to the ground GND. For example, the transistor Q2 may include an emitter node connected to the first resistor R1 and a base node and a collector node connected to ground GND.

The first resistor R1 may be connected at the second input node N₁₂And transistor Q2. The amplifier AMP may amplify the first input node N₁₁Voltage of and secondInput node N₁₂And may pass through the output node N_OThe amplified difference is output. Transistor M1 may be connected to have a supply voltage V_SSAnd a first input node N₁₁And may be responsive to the output node N_OOperates with the voltage of (c). The transistor M2 may be connected to have a power supply voltage V_SSAnd a second input node N₁₂And may be responsive to the output node N_OOperates with the voltage of (c). For example, transistor M2 may be responsive to output node N_OVoltage generating PTAT current I_PTAT. The transistor M2 can supply the PTAT current I_PTATTo the second input node N12.

The mirror current generator 12 may include a transistor M3. Supply voltage V_SSAnd an output node N_OMay be supplied to the mirror current generator 12. The transistor M3 may be responsive to the output node N_OVoltage generating mirror PTAT current I_PTAT. Transistor M3 may mirror PTAT current I_PTATOutput to the reference node N_REF. Reference node N_REFMay be to form a reference voltage V_REFThe node of (2).

The reference voltage generator 13 may include a second resistor R2 and a transistor Q3. The reference voltage generator 13 may pass through a reference node N_REFIs supplied with a mirrored PTAT current I_PTAT. The reference voltage generator 13 may be provided with a ground GND. In an example embodiment, the transistor Q3 may be a BJT. For example, the transistor Q3 may be a PNP type BJT.

The second resistor R2 may be connected to a reference node N_REFAnd (4) connecting. The second resistor R2 may be provided with a mirror current I by the mirror current generator 12_PTAT. The transistor Q3 may be connected between the second resistor R2 and the ground GND, and may operate in response to the ground GND. For example, the transistor Q3 may include an emitter node connected to the second resistor R2 and a base node and a collector node connected to ground GND.

The reference voltage generator 13 may be based on a mirrored PTAT current I_PTATAnd the voltage V of transistor Q3_BE3GeneratingReference voltage V insensitive to absolute temperature_REF. Reference voltage V_REFThe characteristic of insensitivity to absolute temperature will be more fully described with reference to equation 1 below.

V_REF＝I_PTATR2+V_BE3

[ equation 1]

Equation 1 above is a table showing the reference voltage V_REFEquation (c) of (c). I is_PTATIs a mirrored PTAT current I output from a mirrored current generator 12_PTAT. R2 is the resistance value of the second resistor R2. V_BE3Is the value of the voltage between the emitter node and the base node of transistor Q3. V_BE3May have a value inversely proportional to the absolute temperature based on the device characteristics.

Because of the mirrored PTAT current I_PTATBased on the PTAT current I generated by the PTAT current generator 11_PTATSo assuming "a" is the gain of transistor Q1 and n x a is the gain of transistor Q2, PTAT current I_PTATCan be represented by the following equation 2.

Equation 2 above is a representation of PTAT current I_PTATEquation (c) of (c). V_BE1Is the value of the voltage between the emitter node and the base node of transistor Q1. V_BE2Is the value of the voltage between the emitter node and the base node of transistor Q2. R1 is the resistance of the first resistor R1. "n" is the ratio of the gain of transistor Q2 to the gain of transistor Q1. V_TIs a thermal voltage. Since the thermal voltage is proportional to the absolute temperature, the PTAT current I_PTATMay have a magnitude proportional to absolute temperature.

Return to equation 1 above because I_PTATHas a value proportional to absolute temperature, and V_BE3Has a value that decreases as the absolute temperature increases, so fluctuations in the absolute temperature can be cancelled out. For example, in the case of an increase in absolute temperature, because of I_PTATIncrease by V_BE3Reduce, so the absolute temperature can be eliminatedIncrease in degree to reference voltage V_REFThe influence of (c). On the contrary, in the case of a decrease in absolute temperature, since I_PTATIs reduced to V_BE3Increase, so that the increase in absolute temperature can be offset against the reference voltage V_REFThe influence of (c). That is, the reference voltage V_REFMay have a value that is insensitive to changes in absolute temperature.

Fig. 5 is a diagram for describing the electronic device ED to which the heterogeneous power is applied from the setup module SM. Referring to fig. 5, an electronic device ED to which a heterogeneous power source is applied through pad bonding and pin connection and a setup module SM are shown. The setup module SM may have a common ground CGND. The setup module SM may provide the grounds AGND and DGND to the electronic device ED through separate pin connections and separate pad bonds.

The analog ground AGND of the electronic device ED may be obtained by including a series of resistors R_X1、R_X2And R_X3Is connected to a common ground CGND. Digital ground DGND of electronic device ED may be implemented by including a series of resistors R_X1、R_X2And R_X3Is connected to the common ground CGND. Here, the resistor R_X1May be an internal resistor of the electronic device ED. Resistor R_X2May be a resistor corresponding to the pad bond. Resistor R_X3May be a resistor corresponding to the pin connection.

In example embodiments, the electronic device ED may be a semiconductor chip including a plurality of circuits formed on one semiconductor substrate. The terminals of the ground terminals AGND and DGND of the electronic device ED may be used as separate terminals at the time of design. However, when electronic device ED is fabricated on a semiconductor substrate, an unwanted resistive connection may occur between the terminal of analog ground AGND and the terminal of digital ground DGND.

In an example embodiment, digital ground DGND may be a source of power that generates noise as compared to analog ground AGND. Noise from digital ground DGND may be transferred to analog ground AGND through an unwanted resistive connection. The effect of noise from digital ground DGND on analog ground AGND can be represented by equation 3 below.

Equation 3 above is an indication of the effect AGND of noise from digital ground DGND on analog ground AGND_nEquation (c) of (c). DGND_NIs the noise of the randomly assumed digital ground DGND. Herein, R is_X1Is the internal resistance value of the electronic device ED. R_X2Is a resistance value corresponding to the bonding of the pad. R_X3Is a resistance value corresponding to the pin connection. R_X4Is a value corresponding to the resistive connection that occurs between the terminal of analog ground AGND and the terminal of digital ground DGND.

For example, when DGND_nIs 100mV, R_X1、R_X2And R_X3100m omega and RX4 is 10 omega, AGND calculated using equation 3 above_NMay be 2.9 mV.

As described above, in the electronic device ED, an unnecessary resistive connection may occur between the terminal of the analog ground AGND and the terminal of the digital ground DGND. A circuit that operates based on analog ground AGND (e.g., bandgap reference circuit 10 of fig. 4) may operate abnormally due to resistive connection (e.g., reference voltage V may be generated that exceeds a value expected at design time_REF). Therefore, a method of reducing the effect of noise from digital ground DGND on analog ground AGND may be desirable.

Fig. 6 is a diagram illustrating the electronic device ED of fig. 5 in detail. Referring to fig. 6, a manufacturing process diagram corresponding to a portion of an electronic device ED formed on a semiconductor substrate is shown. The electronic device ED may comprise a transistor "Q" and a digital circuit 30. Transistor "Q" may include a collector node CC, a base node BB, and an emitter node EE. The digital circuit 30 may include a digital node XX. Transistor "Q" may be part of a bandgap reference circuit 10 included in electronic device ED. For example, the transistor "Q" may be one of the transistors Q1, Q2, and Q3 of fig. 4.

The transistors "Q" of the electronic device ED and the digital circuit 30 may be formed on the same semiconductor substrate. The semiconductor substrate may be connected to digital node XX of digital circuit 30 and collector node CC of transistor "Q". The digital node XX may be provided with a digital ground DGND. Collector node CC may be provided with analog ground AGND.

The first conductive region may be formed by implanting first impurities into the semiconductor substrate. The first conductive region may be connected to a base node BB of the transistor "Q". The base node may be provided with an analog ground AGND. The base node BB may be connected to the collector node CC.

The second conductive region may be formed by implanting second impurities into the first conductive region. The second conductive region may be connected to an emitter node EE of the transistor "Q". Emitter node EE can be connected to any other node or element. For example, where transistor "Q" is transistor Q1 of fig. 4, emitter node EE may be connected to node N₁₁And (4) connecting. For example, in the case where the transistor "Q" is the transistor Q2 of fig. 4, the emitter node EE may be connected with the first resistor R1. For example, in the case where the transistor "Q" is the transistor Q3 of fig. 4, the emitter node EE may be connected with the second resistor R2.

In example embodiments, the semiconductor substrate may be a P-type semiconductor substrate. The first impurity may be an N-type impurity. The first conductive region may be an N-type region. The second impurity may be a P-type impurity. The second conductive region may be a P-type region.

As shown in FIG. 6, an undesirable resistive connection (e.g., R) may occur between digit dot XX and collector node CC through the semiconductor substrate_X4). Since noise of the digital ground DGND is introduced to the analog ground AGND through the unnecessary resistance connection, a method of reducing the influence according to the unnecessary resistance connection (for example, a method of increasing the value corresponding to the unnecessary resistance connection) is required.

Fig. 7 is a diagram illustrating in detail an electronic device ED according to an example embodiment. An example embodiment in which the influence according to the unnecessary resistance connection is reduced will be described with reference to fig. 7. The transistor "Q" and the digital circuit 30 formed at the semiconductor substrate are similar to the transistor "Q" and the digital circuit 30 described with reference to fig. 6, and thus, additional description will be omitted to avoid redundancy.

In an example embodiment, a resistance barrier (resistance barrier) may be inserted into a semiconductor substrate of the electronic device ED. When a resistive barrier is inserted, it corresponds to the resistive connection (e.g., R) between digital ground DGND and analog ground AGND_X4) The value of (c) may increase. Therefore, the effect of noise from digital ground DGND on analog ground AGND can be reduced.

Fig. 8 is a diagram illustrating in detail an electronic device ED according to an example embodiment. An example embodiment in which the influence according to the unnecessary resistance connection is reduced, a common ground CGND and a resistor R will be described with reference to fig. 8_X1、R_X2And R_X3Common ground CGND and resistor R similar to that described with reference to FIG. 5_X1、R_X2And R_X3Therefore, additional description will be omitted to avoid redundancy.

According to the example embodiment of fig. 8, the resistive barrier layer may be inserted into the semiconductor substrate of the electronic device ED and different pad bonds may be added. For example, as compared to the exemplary embodiment of fig. 7, electronic device ED of fig. 8 may correspond to a case where digital ground DGND is also connected to a pin corresponding to analog ground AGND through a different pad bond.

In example embodiments, the effect of noise from digital ground DGND on analog ground AGND may be reduced when a resistive barrier is inserted into electronic device ED and a different pad bond is added. For example, a resistor R_X5May be a resistor corresponding to a resistive barrier layer inserted into the semiconductor substrate of the electronic device ED. For example, a resistor R_X2May be a resistor corresponding to the added pad bond.

Due to the addition of the resistor R_X2And R_X5And a connection path between the grounds AGND and DGND, the influence of noise of the digital ground DGND on the analog ground AGND can be represented by the following equation 4.

Equation 4 above is an indication of the effect AGND of noise from digital ground DGND on analog ground AGND_nEquation (c) of (c). DGND_NIs the noise of the randomly assumed digital ground DGND. Herein, R is_X1Is the internal resistance value of the electronic device ED. R_X2Is a resistance value corresponding to the bonding of the pad. R_X3Is a resistance value corresponding to the pin connection. R_X5Is a resistance value corresponding to the resistance barrier layer of the semiconductor substrate inserted into the electronic device ED.

For example, when DGND_nIs 100mV, R_X1、R_X2And R_X3100m omega and RX5 of 500 omega, AGND calculated using equation 4 above_NMay be 20 μ V.

As described above, according to the example embodiment of fig. 8, in which the resistance blocking layer is inserted and the different pad bonding is added, the influence of the noise of the digital ground DGND on the analog ground AGND can be reduced. However, a process of adding a resistance blocking layer is also required, a pad for pad bonding is added, and noise introduced into analog ground AGND is not sufficiently reduced. Therefore, another approach is needed to reduce the noise introduced at the electronic device ED to the analog ground AGND.

Fig. 9 is a block diagram illustrating in detail an electronic system ES according to an exemplary embodiment of the present invention. Referring to fig. 9, an electronic system ES according to an example embodiment of the present disclosure is illustrated. The first pad, the second pad, the interface module IM, and the setup module SM are similar to those described with reference to fig. 2, and thus, additional description will be omitted to avoid redundancy.

The electronic device ED may include a bandgap reference circuit 100, an analog circuit 200, a digital circuit 300, and/or an analog and digital circuit 400. Unlike the electronic device ED of fig. 2, the bandgap reference circuit 100 of the electronic device ED may also be connected to a digital ground DGND and an analog ground AGND.

In an example embodiment, a first power received through the first pad may be applied to the bandgap reference circuit 100, the analog circuit 200, and the analog and digital circuits 400. For example, the first power supply may be analog ground AGND.

In an example embodiment, the second power received through the second pad may be applied to the bandgap reference circuit 100, the digital circuit 300, and the analog and digital circuits 400. For example, the second power supply may be digital ground DGND.

The bandgap reference circuit 100 according to the example embodiment of the present disclosure may operate based on a first power supply and a second power supply. When the bandgap reference circuit 100 operates based on both the first and second power supplies, the bandgap reference circuit 100 may generate a reference voltage V that is less sensitive to PVT (e.g., than the example embodiment of FIG. 2)_REF. The bandgap reference circuit 100 will be described more fully with reference to fig. 10.

Fig. 10 is a circuit diagram showing the bandgap reference circuit of fig. 9 in detail. Referring to fig. 10, a bandgap reference circuit 100 is shown that includes a PTAT current generator 110, a mirror current generator 120, and/or a reference voltage generator 130. Unlike bandgap reference circuit 10 of fig. 4, bandgap reference circuit 100 may also operate based on digital ground DGND. The transistors M1, M2 and M3, the amplifier AMP, and the resistors R1 and R2 are similar to the transistors M1, M2 and M3, the amplifier AMP, and the resistors R1 and R2 described with reference to fig. 4, and thus additional description will be omitted to avoid redundancy.

The transistor Q1 may be connected at a first input node N₁₁And ground GND, and may operate in response to analog ground AGND. For example, the transistor Q1 may include a first input node N₁₁A connected emitter node, a base node provided with analog ground AGND, and a collector node connected to digital ground DGND. In an example embodiment, the transistor Q1 may be a PNP type BJT.

Transistor Q2 may be connected between first resistor R1 and digital ground DGND, and may operate in response to analog ground AGND. For example, transistor Q2 may include an emitter node connected to first resistor R1, a base node provided with analog ground AGND, and a collector node connected to digital ground DGND. In an example embodiment, the transistor Q2 may be a PNP type BJT.

Transistor Q3 may be connected between second resistor R2 and digital ground DGND, and may operate in response to analog ground AGND. For example, transistor Q3 may include an emitter node connected to second resistor R2, a base node provided with analog ground AGND, and a collector node connected to digital ground DGND. In an example embodiment, the transistor Q3 may be a PNP type BJT.

In an example embodiment, the base node and the collector node of each of the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100 may be electrically separated from each other. For example, digital ground DGND may be provided to the collector node of at least one of transistors Q1, Q2, and Q3, while analog ground AGND may be provided to the base node thereof. Ground AGND and DGND in electronic device ED or electronic system ES may be electrically separated from each other. Ground AGND and DGND are electrically isolated from one another may mean a resistance value (e.g., R) corresponding to an undesired resistive connection between grounds AGND and DGND_X4) Is greatly increased.

For example, the effect of noise from digital ground DGND on analog ground AGND, AGND_nCan be calculated by using equation 3 above. For example, when the resistor R_X1、R_X2And R_X3R measured by experiment at 100m Ω each of_X4May be about 500k omega. At DGND_nAt 100mV, AGND is calculated using equation 3 above_nHas a value of about 60 nV. Calculated AGND_nThe value may be less than AGND calculated in other example embodiments (e.g., the example embodiments of fig. 5 and 8)_nThe value is obtained.

As described above, according to example embodiments of the present disclosure, there is provided the bandgap reference circuit 100 that provides a heterogeneous power supply to a transistor (e.g., at least one of Q1, Q2, and Q3). As the noise of digital ground DGND has a greatly reduced effect on analog ground AGND, bandgap reference circuit 100 may generate a reference voltage V that is less sensitive to PVT_REF。

Fig. 11 is a diagram illustrating the electronic device ED of fig. 9 in detail. An example embodiment of supplying a heterogeneous power source to the transistor "Q" will be described with reference to fig. 11. The transistor "Q" may be one of the transistors Q1, Q2, and Q3 of fig. 10. The transistor "Q" and the digital circuit 300 formed on the semiconductor substrate are similar to the transistor "Q" and the digital circuit 30 described with reference to fig. 6, and thus, additional description will be omitted to avoid redundancy.

Transistor "Q" of bandgap reference circuit 100 may include a collector node CC provided with digital ground DGND, a base node BB provided with analog ground AGND, and an emitter node EE connected to any other node or element. For example, unlike collector node CC of fig. 6 or 7, digital ground DGND may be provided to collector node CC. Collector node CC may be connected to digital node XX of digital circuit 300.

Instead of providing all nodes CC and BB of bandgap reference circuit 100 with the same ground (e.g., AGND), an electronic device ED may be provided in which the resistive connection between analog ground AGND and digital ground DGND is increased by providing digital ground DGND to collector node CC of bandgap reference circuit 100 and analog ground AGND to its base node BB. For example, an increase in the resistive connection between analog ground AGND and digital ground DGND may indicate an increase in the resistance between analog ground AGND and digital ground DGND, and thus the leakage current between analog ground AGND and digital ground DGND may be reduced.

FIG. 12 is a graph showing the PTAT current I measured at bandgap reference circuits 10 and 100 incorporating DC noise_PTATA graph of (a). Referring to FIG. 12, a graph showing DC noise of a digital ground DGND is shown, showing the PTAT current I measured when the same ground is applied to the bandgap reference circuit 10 according to the example embodiment of FIG. 4_PTATAnd shows the PTAT current I measured when different grounds are applied to the bandgap reference circuit 100 according to the exemplary embodiment of fig. 10_PTATA graph of (a). The graphs shown in fig. 12 share the same time axis.

Referring to a graph showing DC noise of the digital ground DGND, the horizontal axis represents time and the vertical axis represents voltage amplitude of the digital ground DGND. In an example embodiment, the magnitude of digital ground DGND may increase from-2V to 0.7V over time. Digital ground DGND may be provided to transistors Q1, Q2, and Q3 of bandgap reference circuit 10 or transistors Q1, Q2, and Q3 of bandgap reference circuit 100.

Reference shows the PTAT current I measured when the same ground is applied to the bandgap reference circuit 10_PTATThe horizontal axis represents time, and the vertical axis represents the magnitude of the current. The solid line represents the PTAT current I output from the transistor M2_PTAT. The dashed line indicates the mirrored PTAT current I output from transistor M3_PTAT。

In an example embodiment, in bandgap reference circuit 10 with digital ground DGND applied increasing from-2V to 0.7V, PTAT current I of transistor M2_PTATMay be nearly uniform while the mirror PTAT current I of transistor M3_PTATAnd may vary from about-43 mua to about-39 mua. That is, a bandgap reference circuit 10 that applies the same ground is less sensitive to PVT.

Reference shows the PTAT current I measured when different grounds are applied to the bandgap reference circuit 100_PTATThe horizontal axis represents time, and the vertical axis represents the magnitude of the current. The solid line indicates the PTAT current I output from the transistor M2_PTAT. The dashed line indicates the mirrored PTAT current I output from transistor M3_PTAT。

In an example embodiment, in bandgap reference circuit 100 with digital ground DGND applied increasing from-2V to 0.7V, PTAT current I of transistor M2_PTATMay be nearly uniform and the mirror PTAT current I of transistor M3_PTATOr may be nearly uniform. That is, bandgap reference circuits 100 with different grounds applied are less sensitive to PVT than bandgap reference circuits 10 with the same ground applied.

FIG. 13 is a graph showing the reference voltage V at the bandgap reference circuit 100 with DC noise introduced_REFA graph of the distribution of (c). Referring to FIG. 13, a graph showing a reference voltage V measured at the bandgap reference circuit 100 when any DC noise from digital ground DGND is introduced into the bandgap reference circuit 100 according to the exemplary embodiment of FIG. 10 is shown_REFA graph of the distribution of (c). The horizontal axis represents the reference voltage V_REFAnd the vertical axis represents the reference voltage V_REFDensity of distribution。

In an example embodiment, the reference voltage V measured at the bandgap reference circuit 100_REFMay have a normal distribution. Reference voltage V_REFMay have a minimum value, a maximum value, a mean value, and a standard deviation.

In an example embodiment, Table 1 below shows a reference voltage V measured when DC noise of digital ground DGND is introduced to bandgap reference circuit 100 in the range of-0.3V to 0.3V_REFStandard deviation, minimum and maximum values of.

[ Table 1]

DGND[V]	-0.3	-0.2	-0.1	0	0.1	0.2	0.3
								STDEV[V]	0.012732	0.012730	0.012729	0.012729	0.012729	0.012724	0.012733
VREF_Min	1.1949	1.1949	1.1949	1.1949	1.1949	1.1949	1.1949
								VREF_Max	1.2304	1.2304	1.2304	1.2304	1.2304	1.2304	1.2304

The reference voltage V measured at the bandgap reference circuit 100 where DC noise of the digital ground DGND is introduced will be described with reference to table 1_REF. The DGND provided to transistors Q1, Q2, and Q3 of bandgap reference circuit 100 may be increased from-0.3V to 0.3V in units of 0.1V. STDEV is a reference voltage V measured at corresponding DGND_REFStandard deviation of (2). V_{REF_Min}Is a reference voltage V measured at the corresponding DGND_REFIs measured. V_{REF_Max}Is a reference voltage V measured at the corresponding DGND_REFIs measured. Referring to the measurement values of table 1, the bandgap reference circuit 100 to which the heterogeneous power is applied can generate the reference voltage V insensitive to PVT even in the fluctuation of the digital ground DGND_REF。

FIG. 14 is a graph showing the reference voltage V at the bandgap reference circuit 100 with DC noise introduced_REFCurve of standard deviation ofAnd (6) line drawing. Referring to fig. 14, a graph showing the standard deviation STDEV in the bandgap reference circuit 100, which corresponds to the digital ground DGND of table 1 above, is shown.

The horizontal axis represents the magnitude of the digital ground DGND provided to transistors Q1, Q2, and Q3 of bandgap reference circuit 100, and the vertical axis represents the measured reference voltage V_REFStandard deviation of (2). Referring to the graph of fig. 14, the standard deviation STDEV has a relatively uniform value.

As described above, digital ground DGND may be a power source that often generates noise or generates a large amount of noise, as compared to analog ground AGND. However, as described with reference to fig. 12, 13, and 14, even if DC noise of the digital ground DGND is introduced to the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100 operating based on a heterogeneous power supply, the bandgap reference circuit 100 can generate the reference voltage V of uniform amplitude_REF. That is, the bandgap reference circuit 100 according to the example embodiment of the present disclosure may have a strong influence on the DC noise of the digital ground DGND.

Fig. 15 is a graph showing gain and phase at the bandgap reference circuit 100 with AC noise introduced. Referring to fig. 10 and 15, in the bandgap reference circuit 100 of fig. 10, which introduces AC noise of digital ground DGND, a bandgap reference circuit showing the measured reference voltage V is shown_REFGraph ACG1 showing gain to digital ground DGND and showing measured reference voltage V_REFGraph ACG2 of phase to digital ground DGND.

Referring to the graph ACG1, the horizontal axis represents frequency on a logarithmic scale and the vertical axis represents gain. In an example embodiment, the measured reference voltage V_REFThe gain to digital ground DGND may have a value within a particular range at the operating frequency. The operating frequency may be a frequency within the range in which the bandgap reference circuit 100 operates. For example, the measured reference voltage V at the operating frequency of the bandgap reference circuit 100_REFThe gain to digital ground DGND may be about-77.6 dB. Thus, even if AC noise of digital ground DGND is introduced into the bandgap reference circuit 100, the bandgap reference circuit 100 can generate a reference voltage V of uniform amplitude_REF。

Referring to the graph ACG2, the horizontal axis represents frequency on a logarithmic scale and the vertical axis represents phase. In an example embodiment, the measured reference voltage V_REFThe phase to digital ground DGND may have a value within a particular range at the operating frequency. Thus, the bandgap reference circuit 100 does not have an abnormal operation such as oscillation.

Fig. 16A and 16B are diagrams showing a reference voltage V at the bandgap reference circuit 100 to which AC noise is introduced_REFA graph of the waveform of (a). Referring to fig. 10 and 16A, in an example embodiment in which the AC noise of the digital ground DGND has a frequency of 100kHz, a graph showing a waveform of the digital ground DGND and a graph showing a measured reference voltage V are shown_REFA graph of the waveform of (a). The horizontal axis represents time and the vertical axis represents voltage.

In an example embodiment, the reference voltage V measured at the bandgap reference circuit 100 where the AC noise of the digital ground DGND having a frequency of 100kHz has a first peak-to-peak voltage Vpp1_REFThere may be a second peak-to-peak voltage Vpp 2. The second peak-to-peak voltage Vpp2 may be less than the first peak-to-peak voltage Vpp 1. That is, the bandgap reference circuit 100 can operate normally even if AC noise with a digital ground DGND of 100kHz frequency is introduced.

Referring to fig. 10 and 16B, in an example embodiment in which the AC noise of the digital ground DGND has a frequency of 1MHz, a graph showing a waveform of the digital ground DGND and a graph showing a measured reference voltage V are shown_REFA graph of the waveform of (a). The horizontal axis represents time and the vertical axis represents voltage.

In an example embodiment, the reference voltage V measured at the bandgap reference circuit 100 where the AC noise of the digital ground DGND having a frequency of 1MHz has a third peak-to-peak voltage Vpp3_REFThere may be a fourth peak-to-peak voltage Vpp 4. The fourth peak-to-peak voltage Vpp4 may be less than the third peak-to-peak voltage Vpp 3. That is, the bandgap reference circuit 100 can operate normally even if AC noise with a digital ground DGND of 1MHz frequency is introduced.

As described above, digital ground DGND may be a common noise or noise generation compared to analog ground AGNDA power supply that generates a large amount of noise. However, as described with reference to fig. 15, 16A, and 16B, even if AC noise of the digital ground DGND is introduced to the transistors Q1, Q2, and Q3 of the bandgap reference circuit 100 operating based on a heterogeneous power supply, the bandgap reference circuit 100 can generate the reference voltage V of uniform amplitude_REF. In addition, abnormal operations such as oscillation can be reduced at the bandgap reference circuit 100. That is, the bandgap reference circuit 100 according to the example embodiment of the present disclosure may have a strong influence on the AC noise of the digital ground DGND.

Fig. 17 is a block diagram illustrating an image sensor device ISD according to an example embodiment of the present disclosure. Fig. 17 illustrates an image sensor device ISD according to an example embodiment of the present disclosure. The image sensor device ISD may be an implementation example of the electronic device ED of fig. 9. The image sensor device ISD may be a semiconductor chip included in a digital camera, a smart phone, a tablet computer, a laptop computer, or the like. The image sensor device ISD is operable in the analog domain, the digital domain, and the analog and digital domains.

For example, an analog signal such as analog ground AGND may be used in the analog domain. Digital signals such as digital ground DGND may be used in the digital domain. Both analog signals, such as analog ground AGND, and digital signals, such as digital ground DGND, may be used in the analog and digital domains.

The connecting lines are omitted to prevent the drawing from being complicated. However, the analog ground AGND received from the first pin may be provided to at least one circuit included in the analog domain, and may be provided to at least one circuit included in the analog and digital domains. Additionally, digital ground DGND received from the second pin may be provided to at least one circuit included in the digital domain, and may be provided to at least one circuit included in the analog and digital domains.

The image sensor device ISD may comprise circuits in the analog domain, circuits in the digital domain and circuits in the analog and digital domains. For example, the image sensor device ISD may include a pixel array 210, a capacitor and switch network, and a comparator for use in the analog domain. The image sensor device ISD may comprise a counter for use in the digital domain, a memory unit, a second decoder 310 and a sense amplifier. The image sensor device ISD may include a bandgap reference circuit 100, a device interface circuit 410, a ramp generator 420, a pixel voltage generator 430, and/or a first driver and first decoder 440 used in the analog and digital domains.

The device interface circuit 410 may include a first pad and a second pad. The analog ground AGND may be formed at the first pad based on the power received from the first pin. The digital ground DGND may be formed at the second pad based on power received from the second pin. The device interface circuit 410 may receive a power supply voltage V from a separate power module (not shown)_SS. Device interface circuitry 410 may couple power supplies (e.g., AGND, DGND, and V) via separate transmission paths_SS) To the bandgap reference circuit 100.

The bandgap reference circuit 100 may be based on power supplies (e.g., AGND, DGND, and V) received from the device interface circuit 410_SS) Generating a reference voltage V_REF. In an example embodiment, the bandgap reference circuit 100 may further include a current source configured to be based on the reference voltage V_REFAnd outputting the reference current.

For example, the bandgap reference circuit 100 may further include a first current source CS1 configured to be based on the reference voltage V1_REFOutputting a first reference current I_REF1. First reference current I_REF1May have a current that is not sensitive to PVT. For example, the bandgap reference circuit 100 may further include a second current source CS2 configured to be based on the reference voltage V2_REFOutputting a second reference current I_REF2. Second reference current I_REF2May have a current that is not sensitive to PVT. Second reference current I_REF2May be in the presence of a first reference current I_REF1The circuit of (3) is a current used in a different circuit.

In an example embodiment, the bandgap reference circuit 100 may reference a voltage V_REFAnd a first reference current I_REF1And outputs to the pixel voltage generator 430. The bandgap reference circuit 100 can convert the second reference current I_REF2Output to the ramp generator 420.

The ramp generator 420 may be based on the second reference current I_REF2A ramp power supply is generated. Ramp generator 420 may output a ramp power supply to a comparator in the analog domain. The ramp power supply may be a power supply signal used in a comparison operation of the comparator.

The pixel voltage generator 430 may be based on a reference voltage V_REFAnd a first reference current I_REF1A pixel voltage is generated. The pixel voltage generator 430 may output the pixel voltage to the first driver and the first decoder 440. The pixel voltage may be a power supply signal for the first driver and the first decoder 440 to control the pixels of the pixel array 210. The first driver and first decoder 440 may control the pixels of the pixel array 210 based on the pixel voltages received from the pixel voltage generator 430.

The pixel array 210 may include a plurality of pixels arranged in a first direction and a second direction. Each of the pixels may generate an image signal under the control of the first driver and the first decoder 440. Each of the pixels may output an image signal to a corresponding capacitor and switch network. That is, the pixel array 210 may be a circuit driven based on the pixel voltage of the pixel voltage generator 430, and configured to output a plurality of image signals.

The capacitors and the switching network may be connected with corresponding comparators. The capacitor and switch network may output image signals received from corresponding pixels of the pixel array 210 to the comparator.

The comparator may perform a comparison operation based on the image signal received from the capacitor and switch network and the ramp voltage received from the ramp generator 420. The comparator may output a comparison signal to the counter as a result of performing the comparison operation. For example, when the amplitude of the image signal is greater than the amplitude of the ramp voltage, the comparator may output the comparison signal of the first voltage level. The comparator may output the comparison signal of the second voltage level when the amplitude of the image signal is less than the amplitude of the ramp voltage.

The counters may receive comparison signals from corresponding comparators. The counter may determine a count value based on the received comparison signal. For example, the counter may count a comparison signal having a first voltage level among comparison signals received from the comparator for a certain time. The counter may output a signal indicating the determined count value to the corresponding storage unit.

The storage unit may store data based on a signal received from the counter. The memory cell may be connected to a sense amplifier 320. The second decoder 310 may control a plurality of memory cells. For example, the second decoder 310 may control a memory cell such that a data signal is output to the sense amplifier 320 corresponding to the memory cell.

As described above, the bandgap reference circuit 100 according to the example embodiment of the present disclosure may be a circuit included in the image sensor device ISD. Moreover, the bandgap reference circuit 100 may be based on a reference voltage V_REFGenerating a PVT insensitive Current (e.g., first reference Current I)_REF1Or a second reference current I_REF2)。

Fig. 18 is a block diagram illustrating in detail an electronic system ES according to an example embodiment of the present disclosure. Referring to fig. 18, an electronic system ES including a semiconductor chip implemented on a Printed Circuit Board (PCB) is shown. The electronic system ES may comprise an interface module IM, an electronic device ED, an analog chip and/or a digital chip. The electronic device ED may include a bandgap reference circuit 100, an analog circuit 200, a digital circuit 300, and/or an analog and digital circuit 400.

The analog chip may be a semiconductor chip that operates based on an analog signal such as analog ground AGND. The digital chip may be a semiconductor chip that operates based on a digital signal, such as digital ground DGND. Unlike the analog circuit 200 and the digital circuit 300 formed on the semiconductor substrate of the electronic device ED, the analog chip and the digital chip may be semiconductor chips that are manufactured or used independently of the electronic device ED.

In an example embodiment, the electronic system ES may include an interface module IM, an electronic device ED, an analog chip, and/or a digital chip implemented at the PCB. For example, the analog chip may be deposited on an analog plane of the PCB. The digital chip may be deposited at the digital plane of the PCB. The electronic device ED may be deposited at the analog and digital planes of the PCB.

The interface module IM may comprise a first pin and a second pin. The first pin may receive the common ground CGND from the setup module SM through a first pin connection. The second pin may receive the common ground CGND from the setup module SM through a second pin connection. The first pin may be connected with the electronic device ED and the analog chip. The common ground CGND input to the first pin may be used as an analog ground AGND of the electronic device ED and the analog chip. The second pin may be connected to the electronic device ED and the digital chip. The common ground CGND input to the second pin may be used as a digital ground DGND at the electronic device ED and the digital chip.

In example embodiments, the pad bonding may be realized by a wire connecting a pad of a semiconductor device such as the electronic device ED and a pad of the PCB. For example, with reference to a pad bond providing an analog ground AGND of the electronic device ED, the electronic device ED may comprise a first pad. The first pad may be an on-chip pad. The analog plane of the PCB may include a third pad. The third pad may be a PCB pad. The first pad and the third pad may be connected by a wire. The conductive lines may be formed of a conductive material. The third pad may be connected with the first pin of the interface module IM. For example, the first pad, the corresponding wire, and the third pad may be referred to as a "first pad bond".

For example, the electronic device ED may comprise a second pad being an on-chip pad. The digital plane of the PCB may include a fourth pad that is a PCB pad. The second pad and the fourth pad may be connected by a wire. The fourth pad may be connected to a second pin of the interface module IM. For example, the second pad, corresponding wire, and fourth pad may be referred to as a "second pad bond.

However, the present disclosure is not limited thereto. Unlike the example illustrated in fig. 18, the electronic system ES may include semiconductor chips connected by using through-silicon vias (TSVs). For example, a pad bond may indicate a through silicon via to which a semiconductor chip is connected.

Any of the elements disclosed above may include or be implemented in processing circuitry, such as hardware including logic circuitry; a hardware/software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to: a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like.

According to the present disclosure, there are provided a bandgap reference circuit in which reliability of a reference voltage is improved by using a heterogeneous power supply, and an electronic apparatus including the bandgap reference circuit.

In addition, a bandgap reference circuit and an electronic device including the bandgap reference circuit are provided, which reduce an influence due to noise introduced from any other circuit and which are less sensitive to PVT.

While the present disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made therein without departing from the spirit and scope of the present disclosure as set forth in the following claims.