阅读说明：本技术 Nvm栅端电压控制电路 (NVM grid end voltage control circuit ) 是由 刘芳芳 于 2021-08-12 设计创作，主要内容包括：本申请涉及半导体集成电路制造技术领域,具体涉及一种NVM栅端电压控制电路。NVM栅端电压控制电路包括：电荷泵,电荷泵用于产生初始负高压信号；基准电路,基准电路用于产生基准电压信号；分压电路,分压电路的一输入端被配置为接收负高压信号,另一输入端被配置为接收基准电压信号；分压电路包括反馈端和多个分压输出端,反馈端用于产生反馈电压信号,多个分压输出端用于根据初始负高压信号和基准电压信号产生不同等级的抬升负高压信号；反馈电路,反馈电路的一输入端连接所分压电路的反馈端,用于产生电荷泵状态信号；控制输出电路,控制输出电路的输入端连接多个分压输出端,用于控制输出与电压输出信号的等级对应的NVM器件栅端电压信号。(The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an NVM gate voltage control circuit. The NVM gate voltage control circuit includes: the charge pump is used for generating an initial negative high-voltage signal; a reference circuit for generating a reference voltage signal; a voltage division circuit, one input end of the voltage division circuit is configured to receive a negative high voltage signal, and the other input end of the voltage division circuit is configured to receive a reference voltage signal; the voltage division circuit comprises a feedback end and a plurality of voltage division output ends, wherein the feedback end is used for generating a feedback voltage signal, and the plurality of voltage division output ends are used for generating lifting negative high voltage signals of different grades according to the initial negative high voltage signal and the reference voltage signal; one input end of the feedback circuit is connected with the feedback end of the voltage division circuit and is used for generating a charge pump state signal; and the input end of the control output circuit is connected with the plurality of voltage division output ends and is used for controlling and outputting the grid end voltage signal of the NVM device corresponding to the grade of the voltage output signal.)

1. An NVM gate-side voltage control circuit, comprising:

a charge pump for generating an initial negative high voltage signal;

a reference circuit for generating a reference voltage signal;

a voltage divider circuit having one input configured to receive the negative high voltage signal and another input configured to receive the reference voltage signal; the voltage division circuit comprises a feedback end and a plurality of voltage division output ends, the feedback end is used for generating a feedback voltage signal, and the voltage division output ends are used for generating lifting negative high-voltage signals of different grades according to the initial negative high-voltage signal and the reference voltage signal;

one input end of the feedback circuit is connected with the feedback end of the voltage division circuit and is used for generating a charge pump state signal;

and the input end of the control output circuit is connected with the plurality of voltage division output ends and is used for controlling and outputting the grid end voltage signal of the NVM device corresponding to the grade of the voltage output signal.

2. The NVM gate terminal voltage control circuit of claim 1 wherein said voltage divider circuit comprises a plurality of serially connected resistors disposed between an output of said charge pump and an output of said reference circuit;

the resistor is connected with the output end of the reference circuit, and the other end of the resistor is a feedback end of the voltage division circuit;

and a voltage division output end is formed between any two adjacent resistors except the resistor connected with the output end of the reference circuit.

3. The NVM gate terminal voltage control circuit of claim 1 or 2 wherein each of said voltage dividing output terminals has a control switch associated therewith for controlling whether the corresponding voltage dividing output terminal is connected to the input terminal of said control output circuit.

4. The NVM gate terminal voltage control circuit of claim 1, wherein the feedback circuit comprises an operational amplifier comprising a non-inverting input terminal and an inverting input terminal;

the positive phase input end of the operational amplifier is connected with the feedback end of the voltage division circuit and is used for receiving the feedback voltage signal; the inverting input end of the operational amplifier is grounded;

the feedback voltage signal is amplified by the operational amplifier to form a charge pump state signal.

5. The NVM gate terminal voltage control circuit of claim 4, wherein when the path between the charge pump, the voltage divider circuit, and the reference circuit is established and the charge pump and the reference circuit are operational, the charge pump status signal is in a high state, otherwise the charge pump status signal is in a low state.

6. The NVM gate terminal voltage control circuit of claim 1, wherein the control output circuit comprises:

the grid electrode of the output MOS tube is the input end of the control output circuit and is configured to receive the lifting negative high-voltage signals of different grades, and the source electrode of the output MOS tube is configured to output the grid end voltage signal of the NVM device;

the source electrode of the PMOS transmission tube is grounded, the drain electrode of the PMOS transmission tube is connected with the drain electrode of the output MOS tube, and the grid electrode of the PMOS transmission tube is configured to receive a first control signal for controlling whether the PMOS transmission tube is conducted;

the source electrode of the NMOS pass tube is configured to receive an initial negative high-voltage signal generated by the charge pump, the drain electrode of the NMOS pass tube is connected with the source electrode of the output MOS tube, and the grid electrode of the NMOS pass tube is configured to receive a second control signal for controlling whether the NMOS pass tube is conducted or not;

the second control signal is generated by delaying the first control signal, and the PMOS pass transistor and the NMOS pass transistor are not conducted at the same time.

7. The NVM gate terminal voltage control circuit of claim 6, further comprising: a control signal generation circuit, the control signal generation circuit comprising:

a NAND gate, the NAND gate comprising two inputs, wherein one input is configured to receive a charge pump status signal, the other input is configured to receive a programming operation signal, and an output of the NAND gate is used for outputting the first control signal;

and the input end of the delay circuit is connected with the output end of the NAND gate and is used for delaying and outputting the first control signal to obtain the second control signal.

8. The NVM gate terminal voltage control circuit of claim 7, wherein said delay circuit comprises a first CMOS inverter and a second CMOS inverter;

the COMS phase inverter comprises a first PMOS tube and a first NOMS tube, and the grid electrode of the first PMOS tube is connected with the grid electrode of the first NOMS tube and is connected with the output end of the NAND gate; a resistor is connected in series between the source electrode of the first PMOS tube and the drain electrode of the first NOMS tube; the drain electrode of the first PMOS tube is connected with a power supply, and the source electrode of the first NOMS tube is connected with an initial negative high-voltage signal;

the second COMS inverter comprises a second PMOS tube and a second NMOS tube, and the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube and is connected to the output end of the first COMS inverter; the source electrode of the second PMOS tube is connected with the drain electrode of the second NOMS tube to serve as the output end of the delay circuit and used for outputting a second control signal; the drain electrode of the second PMOS tube is connected with the power supply, and the source electrode of the second NOMS tube is connected with an initial negative high-voltage signal.

Technical Field

The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an NVM gate voltage control circuit.

Background

Non-Volatile Memory NVM (Non-Volatile Memory) is characterized by not losing content when power is turned off. Flash memories (Flash memories), for example, are a type of non-volatile Memory that retains on-chip information even after power is turned off

However, when a high voltage program operation is performed on a non-volatile memory including a flash memory, an erase type disturb is generated on a non-operating row (BD cell), and this disturb adversely affects the reliability of the NVM.

Disclosure of Invention

The application provides a NVM grid end voltage control circuit, which can reduce the problem that the related technology generates erasing type interference to the non-operation row when high-voltage programming operation is carried out, and improve the reliability of devices.

In order to solve the technical problem described in the background, the present application provides an NVM gate voltage control circuit, including:

a charge pump for generating an initial negative high voltage signal;

a reference circuit for generating a reference voltage signal;

a voltage divider circuit having one input configured to receive the negative high voltage signal and another input configured to receive the reference voltage signal; the voltage division circuit comprises a feedback end and a plurality of voltage division output ends, the feedback end is used for generating a feedback voltage signal, and the voltage division output ends are used for generating lifting negative high-voltage signals of different grades according to the initial negative high-voltage signal and the reference voltage signal;

one input end of the feedback circuit is connected with the feedback end of the voltage division circuit and is used for generating a charge pump state signal;

and the input end of the control output circuit is connected with the plurality of voltage division output ends and is used for controlling and outputting the grid end voltage signal of the NVM device corresponding to the grade of the voltage output signal.

Optionally, the voltage divider circuit includes a plurality of resistors connected in series in sequence and arranged between the output end of the charge pump and the output end of the reference circuit;

the resistor is connected with the output end of the reference circuit, and the other end of the resistor is a feedback end of the voltage division circuit;

and a voltage division output end is formed between any two adjacent resistors except the resistor connected with the output end of the reference circuit.

Optionally, each of the voltage-dividing output ends is correspondingly connected with a control switch, and the control switch is used for controlling whether the corresponding voltage-dividing output end is communicated with the input end of the control output circuit.

Optionally, the feedback circuit comprises an operational amplifier comprising a non-inverting input and an inverting input;

the positive phase input end of the operational amplifier is connected with the feedback end of the voltage division circuit and is used for receiving the feedback voltage signal; the inverting input end of the operational amplifier is grounded;

the feedback voltage signal is amplified by the operational amplifier to form a charge pump state signal.

Optionally, when a path between the charge pump, the voltage divider circuit, and the reference circuit is established and the charge pump and the reference circuit operate, the charge pump status signal is in a high level state, otherwise, the charge pump status signal is in a low level state.

Optionally, the control output circuit comprises:

the grid electrode of the output MOS tube is the input end of the control output circuit and is configured to receive the lifting negative high-voltage signals of different grades, and the source electrode of the output MOS tube is configured to output the grid end voltage signal of the NVM device;

the source electrode of the PMOS transmission tube is grounded, the drain electrode of the PMOS transmission tube is connected with the drain electrode of the output MOS tube, and the grid electrode of the PMOS transmission tube is configured to receive a first control signal for controlling whether the PMOS transmission tube is conducted;

the source electrode of the NMOS pass tube is configured to receive an initial negative high-voltage signal generated by the charge pump, the drain electrode of the NMOS pass tube is connected with the source electrode of the output MOS tube, and the grid electrode of the NMOS pass tube is configured to receive a second control signal for controlling whether the NMOS pass tube is conducted or not;

the second control signal is generated by delaying the first control signal, and the PMOS pass transistor and the NMOS pass transistor are not conducted at the same time.

Optionally, the NVM gate voltage control circuit further comprises: a control signal generation circuit, the control signal generation circuit comprising:

a NAND gate, the NAND gate comprising two inputs, wherein one input is configured to receive a charge pump status signal, the other input is configured to receive a programming operation signal, and an output of the NAND gate is used for outputting the first control signal;

and the input end of the delay circuit is connected with the output end of the NAND gate and is used for delaying and outputting the first control signal to obtain the second control signal.

Optionally, the delay circuit comprises a first CMOS inverter and a second CMOS inverter;

the COMS phase inverter comprises a first PMOS tube and a first NOMS tube, and the grid electrode of the first PMOS tube is connected with the grid electrode of the first NOMS tube and is connected with the output end of the NAND gate; a resistor is connected in series between the source electrode of the first PMOS tube and the drain electrode of the first NOMS tube; the drain electrode of the first PMOS tube is connected with a power supply, and the source electrode of the first NOMS tube is connected with an initial negative high-voltage signal;

the second COMS inverter comprises a second PMOS tube and a second NMOS tube, and the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube and is connected to the output end of the first COMS inverter; the source electrode of the second PMOS tube is connected with the drain electrode of the second NOMS tube to serve as the output end of the delay circuit and used for outputting a second control signal; the drain electrode of the second PMOS tube is connected with the power supply, and the source electrode of the second NOMS tube is connected with an initial negative high-voltage signal.

The technical scheme at least comprises the following advantages: the voltage of the grid end of the word line of the non-selected row can be raised during high-voltage programming operation, so that the voltage difference between the grid end and the drain end of the non-selected memory unit is reduced, the problem of erasing type interference generated on the non-operated row during high-voltage programming operation is reduced, and the reliability of the device is improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a block diagram of an NVM gate voltage control circuit according to an embodiment of the present application;

FIG. 2 is a circuit diagram of an NVM gate voltage control circuit according to an embodiment of the present application;

fig. 3 shows a circuit schematic of a control signal generating circuit.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Fig. 1 shows a block diagram of an NVM gate-side voltage control circuit according to an embodiment of the present application, and as can be seen from fig. 1, the NVM gate-side voltage control circuit includes:

a charge pump 110, the charge pump 110 for generating an initial negative high voltage signal VNEG.

A reference circuit 120, the reference circuit 120 for generating a reference voltage signal VREF.

A voltage divider circuit 130, one input of the voltage divider circuit 130 being configured to receive the initial negative high voltage signal VNEG, and the other input being configured to receive the reference voltage signal VREF; the voltage dividing circuit 130 includes a feedback terminal and a plurality of voltage dividing output terminals, the plurality of voltage dividing output terminals are configured to generate the lifting negative high voltage signal VNEG-PP with different levels according to the initial negative high voltage signal and the reference voltage signal, and the feedback terminal is configured to generate the feedback voltage signal DIV.

And an input end of the feedback circuit 140 is connected to the feedback end of the voltage dividing circuit 130, and is used for generating a charge pump state signal.

And the input end of the control output circuit 150 is connected with the plurality of voltage division output ends, and is used for generating an NVM device gate voltage signal VNEG-P according to the negative-lift high-voltage signal VNEG-PP.

According to the embodiment, when the high-voltage programming operation is performed, the voltage of the grid end of the word line of the unselected row is raised, so that the voltage difference between the grid end and the drain end of the unselected memory unit is reduced, the operation interference is reduced, and the reliability of the device is improved.

Fig. 2 shows a circuit diagram of an NVM gate terminal voltage control circuit according to an embodiment of the present application, and as can be seen from fig. 2, the voltage dividing circuit 130 includes: and a plurality of resistors R0, R1 … R (k), R (k +1) and R (n) connected in series in sequence are arranged between the output end of the charge pump 110 and the output end of the reference circuit 120, wherein k is a positive integer larger than 1. One end of the resistor R (n) is connected to the output end of the reference circuit 120, and the other end is connected to the resistor R (k +1), and the connection end of the resistor R (n) and the resistor R (k +1) is used as the feedback end of the voltage dividing circuit 130, and is used for generating a feedback voltage signal to the feedback circuit 140. A plurality of voltage division output ends of the voltage division circuit 130 are formed between the other two adjacent resistors, and are used for generating lifting negative high voltage signals of different levels according to the initial negative high voltage signal and the reference voltage signal. Each voltage division output end is correspondingly connected with a control switch S0, S1 … Sk, and the control switches S0, S1 … Sk are used for controlling whether the corresponding voltage division output end is communicated with the input end of the control output circuit 150. For example, the control switch Sk is used to connect the voltage division output end led out from the connection end of the resistor R (k) and the resistor R (k +1) to the input end of the control output circuit 150.

With continued reference to fig. 2, the feedback circuit 140 includes an operational amplifier a that includes a non-inverting input and an inverting input. The non-inverting input terminal of the operational amplifier a is connected to the feedback terminal of the voltage divider circuit 130, and is configured to receive the feedback voltage signal DIV, and the inverting input terminal of the operational amplifier a is grounded. The feedback voltage signal DIV is amplified by the operational amplifier A to form a charge pump status signal PUMPGOOD. When the paths between the charge pump 110, the voltage divider circuit 130 and the reference circuit 120 are established and the charge pump 110 and the reference circuit 120 are operating, the charge pump status signal PUMPGOOD is in a high state (i.e., PUMPGOOD is "1"), otherwise the charge pump status signal PUMPGOOD is in a low state (i.e., PUMPGOOD is "0").

With continued reference to fig. 2, the control output circuit 150 includes an output MOS transistor N0, a PMOS pass transistor P0, and an NMOS pass transistor N0.

The gate of the output MOS transistor N0 is an input terminal of the control output circuit 150, and is configured to receive the negative high-voltage signal VENG-PP of different levels, and the source of the output MOS transistor is configured to output the gate voltage signal VENG-P of the NVM device.

The source of the PMOS pass transistor P0 is grounded, the drain is connected to the drain of the output MOS transistor N0, and the gate is configured to receive a first control signal CTRL for controlling whether the PMOS pass transistor P0 is turned on.

The source of the NMOS pass transistor N1 is configured to receive the initial negative high voltage signal VNEG generated by the charge 110 pump, the drain is connected to the source of the output MOS transistor, and the gate is configured to receive the second control signal CTRLD for controlling whether the NMOS pass transistor N1 is turned on.

The second control signal CTRLD is generated by delaying the first control signal CTRL, and the PMOS pass transistor P0 and the NMOS pass transistor N1 are not turned on at the same time under the control of the first control signal CTRL and the second control signal CTRLD.

When the first control signal CTRL and the second control signal CTRLD are at a high level, i.e., CTRL ═ 1 "CTRLD ═ 1", the PMOS pass transistor P0 is turned off and the NMOS pass transistor N1 is turned on, so that the NVM device gate voltage signal VENG-P is equal to the initial negative high voltage signal VNEG.

When the first control signal CTRL and the second control signal CTRLD are at a low level, that is, CTRL is at "0" and CTRLD is at "0", the PMOS pass transistor P0 is turned on, and the NMOS pass transistor N1 is turned off, so that the NVM device gate voltage signal VENG-P is equal to the boosted negative high voltage signal VENG-PP of the corresponding level minus the turn-on voltage Vth of the output MOS transistor N0.

Referring to fig. 3, a circuit schematic of a control signal generation circuit for generating the control signal CTRL is illustrated. Referring to fig. 3, the control signal generating circuit includes: a nand gate 310 and a delay circuit 320.

The nand gate 310 includes two inputs, one input configured to receive the charge pump status signal PUMPGOOD, the other input configured to receive the PROGRAM operation signal PROGRAM, and an output of the nand gate 310 for outputting the first control signal CTRL.

The input terminal of the delay circuit 320 is connected to the output terminal of the nand gate 310, and is used for delaying the first control signal CTRL to obtain the second control signal CTRLD.

The delay circuit 320 may be a CMOS two-stage delay circuit made of PMOS and NMOS, wherein the delay circuit 320 includes a first CMOS inverter 321 and a second CMOS inverter 322.

The first cmos inverter 321 includes a first PMOS transistor and a first nmos transistor, a gate of the first PMOS transistor is connected to a gate of the first nmos transistor and connected to an output terminal of the nand gate, a resistor is connected in series between a source of the first PMOS transistor and a drain of the first nmos transistor, the drain of the first PMOS transistor is connected to a power supply Vpwr, and the source of the first nmos transistor is connected to an initial negative high voltage signal VNEG.

The second cmos inverter 322 includes a second PMOS transistor and a second NMOS transistor, a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor and is connected to an output terminal of the first cmos inverter (i.e., a source of the first PMOS transistor), a source of the second PMOS transistor is connected to a drain of the second NMOS transistor as an output terminal of the delay circuit 320, and is configured to output a second control signal CTRLD, the drain of the second PMOS transistor is connected to the power supply Vpwr, and the source of the second NMOS transistor is connected to the initial negative high voltage signal VNEG.

In this embodiment, the second control signal is obtained by delaying the first control signal through the delay circuit, so that when the first control signal is at a high level, the second control signal at the high level can be delayed, and thus the NMOS pass transistor N1 is delayed to be turned on, thereby avoiding that the initial negative high-voltage signal VNEG is pulled up instantaneously due to the coupling effect generated by the NMOS pass transistor N1 being turned on instantaneously, and reducing the instantaneous coupling degree of the initial negative high-voltage signal VNEG.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.