Field effect transistor, preparation method and logic gate operation implementation method
阅读说明：本技术 场效应晶体管及制备方法、逻辑门操作实现方法 (Field effect transistor, preparation method and logic gate operation implementation method ) 是由 王振兴 王俊俊 王峰 何军 于 2021-06-18 设计创作，主要内容包括：本发明提供一种场效应晶体管及制备方法、逻辑门操作实现方法,通过使用α-In-(2)Se-(3)纳米片形成沟道区,利用α-In-(2)Se-(3)受电压控制可以改变面内和面外的铁电极化特性,控制栅极和漏极至少一端的输入电压,可以改变沟道区的阻态来调节源极的输出电流,以根据该输出电流实现逻辑门操作。因此,使用本发明提供的单一的场效应晶体管,就能够实现多种逻辑门操作,这与利用传统的场效应晶体管实现逻辑门操作相比,本发明提供的场效应晶体管器件结构简单,尺寸更小。(The invention provides a field effect transistor, a preparation method and a logic gate operation realization method, and alpha-In is used 2 Se 3 The nanosheets form channel regions utilizing alpha-In 2 Se 3 The ferroelectric polarization characteristic in plane and out of plane can be changed by voltage control, the input voltage at least one end of the grid and the drain is controlled, the resistance state of the channel region can be changed to adjust the output current of the source, and the logic gate operation can be realized according to the output current. Therefore, multiple logic gate operations can be achieved using a single FET provided by the present invention, which is in contrast to logic gate operations achieved using conventional FETsThe structure is simple, and the size is smaller.)
1. A field effect transistor, comprising:
a gate electrode;
a dielectric layer covering the gate;
utilizing alpha-In on the dielectric layer2Se3A channel region formed by the nanosheets;
a source and a drain distributed at both ends with respect to the channel region.
2. The field effect transistor of claim 1, wherein the gate is formed from a substrate.
3. The field effect transistor of claim 1, further comprising:
and the passivation layer covers the channel region, the source electrode and the drain electrode.
4. The FET of claim 3, wherein the passivation layer is made of a light transmissive material.
5. A method of fabricating a field effect transistor, comprising:
forming a gate and a dielectric layer covering the gate;
a-In obtained by peeling off a micromachine2Se3Nanoplatelets are transferred onto the dielectric layer to form trenchesA street region;
source and drain electrodes are formed that are distributed at both ends with respect to the channel region.
6. The method of manufacturing a field effect transistor according to claim 5, wherein α -In obtained by micro-mechanical peeling is used2Se3The nanoplatelets are transferred onto the dielectric layer to form a channel region, comprising:
alpha-In obtained In micro-mechanical stripping2Se3Spin-coating PPC solution on the nano-chip;
baking the PPC solution to form a PPC film;
peel adhesion of the alpha-In using deionized water2Se3A nanosheet PPC film;
will adhere to the alpha-In2Se3The PPC film of nanoplates is transferred onto the dielectric layer such that the alpha-In2Se3A nanosheet overlying the dielectric layer;
dissolving the PPC film to leave the alpha-In2Se3The nanosheets form the channel regions.
7. The method of manufacturing a field effect transistor according to claim 5, wherein forming a source and a drain distributed at both ends with respect to the channel region comprises:
forming a metal material layer on the channel region using a metal deposition process;
and carrying out patterning treatment on the metal material layer to obtain the source electrode and the drain electrode.
8. The method for manufacturing a field effect transistor according to claim 5, further comprising:
forming a passivation layer on the channel region, the source electrode and the drain electrode using an atomic layer deposition method.
9. A method for implementing logic gate operation is characterized by comprising the following steps:
providing a field effect transistor according to any one of claims 1 to 4;
and controlling the input voltage of at least one end of the grid electrode and the drain electrode to adjust the output current of the source electrode so as to realize the logic gate operation according to the output current.
10. The method for implementing logic gate operation of claim 9, further comprising:
illuminating alpha-In the channel region with an optical signal2Se3Nanosheets to modulate the alpha-In2Se3The ferroelectric polarization state of the nano-sheet is adjusted, and the resistance state of the nano-sheet is further adjusted.
Technical Field
The invention relates to the technical field of semiconductors, in particular to a field effect transistor, a preparation method and a logic gate operation implementation method.
Background
The continuous scaling of Complementary metal-oxide-semiconductor (CMOS) field Effect transistor (fet) (field Effect transistor) sizes has been the cornerstone for the rapid increase in microprocessor computing performance. Although new technologies such as strained silicon gates, high-k dielectrics, Fin-FETs (Field-Effect transistors), fully-wrapped-gate structures, etc. have been driving the scaling of device dimensions, conventional CMOS will inevitably reach the scaling limit.
In order to enable the device performance to continue to improve, some solutions have been proposed that are easy to implement. For example, a reconfigurable field effect transistor with programmable conductivity polarity on a single device can increase the functionality of the device, thereby improving material area utilization without destroying accepted ways of designing and constructing modern electronic circuits. However, the above solution has a serious drawback in that additional electrode tips are required to be added or removed, which in turn greatly increases the complexity of the system. Therefore, a device design having a simpler structure and capable of realizing multi-functional logic operation is highly desirable.
Disclosure of Invention
The invention provides a field effect transistor, a preparation method and a logic gate operation implementation method, which are used for solving the problem that a semiconductor device for implementing logic gate operation in the prior art is complex in structure.
The present invention provides a field effect transistor, including:
a gate electrode;
a dielectric layer covering the gate;
utilizing alpha-In on the dielectric layer2Se3A channel region formed by the nanosheets;
a source and a drain distributed at both ends with respect to the channel region.
According to the field effect transistor provided by the invention, the gate is formed by the substrate.
According to the present invention, there is provided a field effect transistor further comprising:
and the passivation layer covers the channel region, the source electrode and the drain electrode.
According to the field effect transistor provided by the invention, the passivation layer is made of a light-transmitting material.
The invention also provides a preparation method of the field effect transistor, which comprises the following steps:
forming a gate and a dielectric layer covering the gate;
a-In obtained by peeling off a micromachine2Se3Transferring the nanosheets onto the dielectric layer to form a channel region;
source and drain electrodes are formed that are distributed at both ends with respect to the channel region.
According to the preparation method of the field effect transistor provided by the invention, the alpha-In obtained by micro-mechanical stripping2Se3The nanoplatelets are transferred onto the dielectric layer to form a channel region, comprising:
alpha-In obtained In micro-mechanical stripping2Se3Spin-coating PPC solution on the nano-chip;
baking the PPC solution to form a PPC film;
peel adhesion of the alpha-In using deionized water2Se3A nanosheet PPC film;
transferring the PPC film onto the dielectric layer and allowing the PPC film to cover the dielectric layer to support the alpha-In2Se3Nanosheets;
will adhere to the alpha-In2Se3The PPC film of nanoplates is transferred onto the dielectric layer such that the alpha-In2Se3A nanosheet overlying the dielectric layer;
dissolving the PPC film to leave the alpha-In2Se3The nanosheets form the channel regions.
According to the method for manufacturing the field effect transistor, the source and the drain distributed at two ends of the channel region are formed, and the method comprises the following steps:
forming a metal material layer on the channel region using a metal deposition process;
and carrying out patterning treatment on the metal material layer to obtain the source electrode and the drain electrode.
The preparation method of the field effect transistor provided by the invention further comprises the following steps:
forming a passivation layer on the channel region, the source electrode and the drain electrode using an atomic layer deposition method.
The invention also provides a logic gate operation implementation method, which comprises the following steps:
providing a field effect transistor as described in any of the above;
and controlling the input voltage of at least one end of the grid electrode and the drain electrode to adjust the output current of the source electrode so as to realize the logic gate operation according to the output current.
The logic gate operation implementation method provided by the embodiment of the invention further comprises the following steps:
illuminating alpha-In the channel region with an optical signal2Se3Nanosheets to modulate the alpha-In2Se3The ferroelectric polarization state of the nano-sheet is adjusted, and the resistance state of the nano-sheet is further adjusted.
The invention provides a field effect transistor, a preparation method and a logic gate operation realization method, wherein alpha-In is used2Se3The nanosheets form channel regions utilizing alpha-In2Se3The ferroelectric polarization characteristic in plane and out of plane can be changed by voltage control, the input voltage at least one end of the grid and the drain is controlled, the resistance state of the channel region can be changed to adjust the output current of the source, and the logic gate operation can be realized according to the output current. Therefore, a plurality of logic gate operations can be realized by using a single field effect transistor provided by the embodiment of the invention, and compared with the logic gate operation realized by using the traditional field effect transistor, the field effect transistor provided by the invention has the advantages of simple structure and smaller size.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic perspective view of a field effect transistor according to an embodiment of the present invention;
2-14 are schematic diagrams of testing processes for implementing the operation of a logic gate using the FET shown in FIG. 1 according to embodiments of the present invention;
fig. 15 is a schematic flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present invention;
fig. 16 to fig. 20 are schematic cross-sectional structural diagrams of various stages of a manufacturing method of a field effect transistor according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The performance of modern CMOS systems has now entered a plateau for many years. The main reason for this is that the physical separation between the processing and memory units of the von neumann architecture causes energy and time consumption when data is shuttled between the two. However, as society enters a big data era, a lot of scenes such as the internet of things, machine learning, artificial neural networks, bionic intelligence and the like need to be applied to a large amount of data, so that huge energy consumption and a large amount of time are wasted, and therefore the von neumann architecture is broken.
To build efficient, high-speed data-centric electronic circuits, a promising solution, a body of computation, has been proposed. To date, schemes based on non-volatile storage, including resistive memory, phase change memory, and floating gate memory, have been reported to demonstrate a cost-effective functionality. However, there are still many obstacles to the practical production life of these solutions, such as switching electrode variability, high operating voltage, complex processes (extra gate or logic input), etc.
Research shows that the ferroelectric material has the characteristic that the ferroelectric polarization state can be reversed by an external electric field, and has proved to have the capability of constructing functional devices, such as a ferroelectric random Access memory (ram) for nonvolatile storage, a negative capacitance field effect transistor for high-efficiency switching, and the like, and particularly for integrated ferroelectric field effect transistor devices. Scaling of devices with good endurance/reliability, large memory windows, and fast write/erase speeds, however, has been a major challenge. Furthermore, conventional ferroelectric materials are either insulators or wide band gap semiconductors, which severely limits the functionality of ferroelectric based devices.
The invention turns to another Van der Waals ferroelectric semiconductor material alpha-In2Se3. In one aspect, α -In2Se3The layered structure of (a) has inherent immunity to the problems caused by device scaling described above. Therefore, the above advantages make α -In2Se3Are considered promising candidates for building unexplored functional devices, where the concept of integrating logic and computational functions into a simple structured device has not been proposed and implemented.
A field effect transistor provided by an embodiment of the present invention is described below with reference to fig. 1.
Referring to fig. 1, a field effect transistor according to an embodiment of the present invention includes:
a gate electrode 11;
a dielectric layer 12 covering the gate electrode 11;
utilizing alpha-In on the dielectric layer 122Se3A channel region 13 formed of a nanosheet;
a source 14 and a drain 25 distributed at both ends with respect to said channel 13 region.
The channel region 13 of the embodiment of the present invention is made of α -In2Se3Logic gate operation can be realized by using the field effect transistor of the embodiment of the invention. Specifically, the input voltage at least one end of the gate 11 and the drain 15 is controlled to change the resistance state of the channel region 13 to adjust the output current of the source 14, so as to realize the logic gate operation according to the output current.
Therefore, a plurality of logic gate operations can be realized by using a single field effect transistor provided by the embodiment of the invention, and compared with the logic gate operation realized by using the traditional field effect transistor, the field effect transistor provided by the invention has the advantages of simple structure and smaller size.
The scheme of implementing the logic gate by the field effect transistor according to the embodiment of the present invention is described in detail below with reference to specific test data.
The field effect transistor is first set to a certain initial ferroelectric polarization state (high resistance state or low resistance state) using a pulse programming signal of a large amplitude, and then a gate voltage is input to the gate 11 and/or an input voltage pulse signal such as a bias signal is input to the drain 15 to perform logic calculation. After the input voltage is over, the nonvolatile memory integrated function can be realized.
Referring to fig. 2, if the field effect transistor is set to a High Resistance State (HRS) after the voltage input, the output current of the field effect transistor implements an and gate logic operation. Where 0 denotes an input low-level pulse signal, 1 denotes an input high-level pulse signal, and thus, gate voltage-bias voltage ═ 11 'denotes that the input voltage includes both gate voltage and bias voltage as high-level pulse signals, gate voltage-bias voltage ═ 00' denotes that the input voltage includes both gate voltage and bias voltage as low-level pulse signals, gate voltage-bias voltage ═ 01 'denotes that the input voltage medium gate voltage is a low-level pulse signal, bias voltage is a high-level pulse signal, and gate voltage-bias voltage ═ 10' denotes that the input voltage medium gate voltage is a high-level pulse signal, bias low-level pulse signal.
Specifically, only when a high-level pulse signal is simultaneously input to the gate voltage and the bias voltage, the output current is a high current. When one of the input grid voltage or the bias voltage is a low-level pulse signal, the output current is low current. Thus, the AND gate logic operation can be realized according to the output current.
After being cycled for many times, referring to fig. 3, the field effect transistor has good robustness in realizing and gate logic operation.
Referring to fig. 4, if the field effect transistor is set to a High Resistance State (HRS), after the voltage pulse signal input is ended, the storage current of the field effect transistor implements a nonvolatile nor gate logic operation, and the storage current is the output current of the field effect transistor after the voltage pulse signal input is ended.
Specifically, when a low-level pulse signal is input simultaneously with the input of the gate voltage and the bias voltage, the storage current maintains a high current, whereas when only one of the input of the voltage signal is a high-level pulse signal in the input of the gate voltage and the bias voltage, the storage current is low after the input of the voltage signal is ended. Thus, a non-volatile nor gate logic operation may be achieved based on the memory current.
Referring to fig. 5, the field effect transistor achieves a non-volatile nor gate logic operation that is very robust after being set to a High Resistance State (HRS).
Referring to fig. 6, after the field effect transistor is set to a High Resistance State (HRS), an ultra fast operation speed, which may be up to about 10 μ s, is achieved for the non-volatile nor gate logic operation.
Referring to fig. 7, after the field effect transistor is set to a Low Resistance State (LRS), an output current of the field effect transistor implements an or gate logic operation during a voltage input.
Specifically, the output current is a low current only when a low-level pulse signal is simultaneously input to the gate voltage and the bias voltage, and the output current is a high current when one of the gate voltage and the bias voltage is input to a high-level pulse signal. Therefore, an or gate logic operation can be realized according to the output current.
Referring to fig. 8, after the field effect transistor is set to a Low Resistance State (LRS), the implemented or gate logic operation is very robust.
Referring to fig. 9, after the field effect transistor is set to a Low Resistance State (LRS), the storage current of the device implements a non-volatile nand gate logic operation after the voltage input is terminated.
Specifically, the storage current maintains a low current after the gate voltage and the bias voltage are simultaneously inputted with the high level pulse signal and maintains a high current after the input signal is ended when only one of the voltage signals is inputted with the low level pulse signal. Therefore, a nonvolatile nand gate logic operation can be realized according to the memory current.
Referring to fig. 10, after the field effect transistor is set to a Low Resistance State (LRS), the implemented non-volatile nand gate logic operation is very robust.
Referring to fig. 11, after the field effect transistor is set to the high resistance state (LRS), the nand logic operation is realized with an ultra-fast operation speed, which may reach about 10 μ s.
In alternative embodiments of the present invention, α -In may also be utilized2Se3The strong photoresponse characteristic of (2) changes the resistance state of the channel region. Specifically, alpha-In the channel region is irradiated with an optical signal2Se3Nanosheets to modulate the alpha-In2Se3The ferroelectric polarization state of the nano-sheet is adjusted, and the resistance state of the nano-sheet is further adjusted.
Referring to fig. 12, a laser signal in the visible light band is used as another input terminal, and the above-mentioned drain bias signal is combined to realize a logic operation and nonvolatile memory integrated function of photoelectric synergy, wherein ON indicates that an optical signal is input, OFF indicates that no optical signal is input, and the visible light band includes 473 nm, 532 nm and 639 nm.
When the bias signal is input alone, the output current reaches a high current. When the bias signal is ended, the memory current becomes a low current, so that the nonvolatile not gate logic can be realized. When the bias signal and the laser signal are used as two input signals, the output current is kept to be low current only when the two input signals are low-level pulse signals; when the bias voltage and the laser signal are finished, the storage current keeps a low-current state only when the bias voltage signal is a high-level pulse signal and the laser signal is in an off state, so that the field effect transistor realizes the OR gate logic and the nonvolatile implication logic of photoelectric synergistic effect.
Referring to fig. 13, a laser signal in the visible light band is used as another input terminal, and the logic operation and nonvolatile storage operation integrated function of the photoelectric synergistic effect is realized by combining the gate voltage signal.
When the gate voltage signal is input alone, the output current reaches a high current. When the gate voltage signal is ended, the memory current becomes a low current, so that the non-volatile not gate logic can be realized. When the grid voltage signal and the laser signal are used as two input signals, the output current is kept to be low current only when the grid voltage signal is a low-level pulse signal and the laser signal is in an off state; when the grid voltage and the laser signal are finished, the storage current keeps a low-current state only when the grid voltage signal is a high-level pulse signal and the laser signal is in an off state, so that the field effect transistor realizes the OR gate logic and the nonvolatile inclusion logic of the photoelectric synergistic effect.
Referring to fig. 14, three terminals of a laser signal, a gate voltage signal and a bias signal are used as input terminals. The light columns are used to indicate the level of the output current, the darker the color, the higher the output current, and conversely, the lighter the color, the lower the output current.
When the input is the photo-grid voltage-bias voltage ═ 000 ', the output current is a low current, and in other states, such as the photo-grid voltage-bias voltage ═ 001', the photo-grid voltage-bias voltage ═ 010 ', the photo-grid voltage-bias voltage ═ 011', the photo-grid voltage-bias voltage ═ 100 ', the photo-grid voltage-bias voltage ═ 101', the photo-grid voltage-bias voltage ═ 110 ', the photo-grid voltage-bias voltage ═ 111', the output currents are all high currents, so that it is possible to implement a three-input or gate logical operation.
When the photo-gate voltage-bias voltage is equal to '000' and the photo-gate voltage-bias voltage is equal to '100', that is, when the input gate voltage and the bias voltage are both low-level pulse signals regardless of whether the laser signal is input, the storage current of the field effect transistor maintains a high current, and the storage current in other cases maintains a low current, the non-volatile nor logic operation is realized.
As can be seen from the above, the field effect transistor according to the embodiment of the present invention can implement the following functions:
s1, when only one grid voltage or bias voltage signal is used as an input signal, the non-volatile NOT gate logic operation can be realized;
s2, when the grid voltage and the bias pulse are used as input signals at the same time, the two-input AND gate and OR gate logic operation, and the nonvolatile NAND gate and NOR gate logic operation can be realized;
s3, when only one voltage signal (grid voltage or bias voltage) and laser signal are used as input signals, the logic operation of the two-input OR gate and the nonvolatile implication logic operation can be realized;
s4, when two voltage (gate voltage and bias voltage) pulses and a laser signal are used as input signals, three-input or gate and nor gate logic operations can be realized.
As can be seen from the above test results, the field effect transistor device provided by the embodiment of the present invention has a simple three-terminal structure, can implement various logic operations including or gate, and gate logic operation, and logic operations of non-volatile not gate, nand gate, nor gate, implication, etc. by setting different initial states and different input conditions, and exhibits excellent robustness and ultra-fast operation speed.
The structure of the field effect transistor according to the embodiment of the present invention is specifically described below with reference to fig. 1.
In the embodiment of the present invention, the gate electrode 11 is formed of a substrate. Specifically, a silicon wafer substrate is formed with heavy doping, and the substrate directly serves as the gate electrode 11.
In alternative embodiments of the present invention, the protruding gate may also be formed on the substrate or patterned to form the protruding gate, which is not limited herein.
In the embodiment of the present invention, the dielectric layer 12 may be aluminum oxide or other dielectric materials, which have an insulating and isolating function.
In an embodiment of the present invention, the field effect transistor may further include a passivation layer 16, and the passivation layer 16 covers the channel region 13, the source electrode 14, and the drain electrode 15. The passivation layer 16 functions to protect the channel region 13, the source electrode 14, and the drain electrode 15.
Wherein the passivation layer 16 covers the sidewalls of the source electrode 14 and the drain electrode 15, i.e. partially does not cover the source electrode 14 and the drain electrode 15. In an alternative embodiment, the passivation layer may also completely cover the source and drain electrodes.
The passivation layer 16 may be made of a light-transmissive material such as aluminum oxide or hafnium oxide, and the light-transmissive material may be used for transmitting a laser signal to implement a logic gate operation, which is not specifically limited herein.
The source electrode 14 and the drain electrode 15 may be metal electrodes, and may also be graphene electrodes.
A method for manufacturing a field effect transistor according to an embodiment of the present invention will be described below with reference to fig. 15 to 20.
Referring to fig. 15, a method for manufacturing a field effect transistor according to an embodiment of the present invention may include the following steps:
step 151: forming a gate and a dielectric layer covering the gate;
step 152: two-dimensional layered ferroelectric semiconductor alpha-In obtained by micro-mechanical stripping2Se3Transferring the nanosheets onto a dielectric layer to form a channel region;
step 153: source and drain electrodes are formed that are distributed at both ends with respect to the channel region.
Specifically, referring to fig. 16, a substrate 160 is provided, the substrate 160 forming a gate.
The substrate 160 may be a heavily doped silicon substrate and may directly serve as a gate. The type or ratio of ions doped in the substrate 160 is not particularly limited.
Referring to fig. 17, a dielectric layer 170 is deposited over substrate 160 using atomic deposition, and dielectric layer 170 covers substrate 160 and serves as an insulating barrier to substrate 160 and the device layers above it.
The material of the dielectric layer 170 is alumina or silicon dioxide or other materials capable of serving as an insulating barrier. The thickness of the aluminum trioxide dielectric layer 170 is 15 to 50nm, preferably 50nm, and the thickness of other materials can be selected according to the requirement, which is not limited herein.
Referring to FIG. 18, α -In2Se3The material exists In the form of nano-sheet, so that the alpha-In obtained by stripping can be separated2Se3Nanosheet transfer to dielectric layer 170, alpha-In2Se3The nanosheets are on top of the dielectric layer 170 to form channel regions 180.
Wherein, alpha-In2Se3The nano sheet can be prepared by mechanically stripping corresponding block materials by using transparent adhesive tapes, and the layered alpha-In is obtained by multiple stripping2Se3The bulk material adheres to the tape to effect the peel.
In the examples of the present invention, α -In is added2Se3The nanoplatelets are stripped directly onto the substrate 160 where the alumina dielectric layer 170 is evaporated.
In the examples of the present invention, the α -In obtained by the exfoliation2Se3The nanoplatelets are transferred onto the dielectric layer 170 to form a channel region 180, comprising the steps of:
alpha-In obtained In micro-mechanical stripping2Se3Spin-coating PPC solution on the nano-chip;
baking the PPC solution to form a PPC film;
peel adhesion of the alpha-In using deionized water2Se3A nanosheet PPC film;
will adhere to the alpha-In2Se3The PPC film of nanoplates is transferred onto the dielectric layer such that the alpha-In2Se3A nanosheet overlying the dielectric layer;
dissolving the PPC film to leave the alpha-In2Se3The nanosheets form the channel regions.
PPC is called poly (propylene carbonate) In English, and is prepared by uniformly spin-coating solution state PPC on alpha-In2Se3And curing the nano-chips by baking for about 10-30 seconds, wherein the baking time is not specifically limited.
In an alternative embodiment of the invention, heating may be applied to enhance alpha-In prior to dissolving the PPC film2Se3Adhesion between the nanoplatelets and the dielectric layer 170, such that the alpha-In2Se3The interface of the nano-sheet and the dielectric layer 170 is more tightly combined;
in addition, the PPC film may be dissolved using acetone.
Referring to fig. 19, a source electrode 191 and a drain electrode 192 are formed on the channel region 180, wherein the source electrode 191 and the drain electrode 192 are disposed at both ends.
In the present embodiment, the source 191 and the drain 192 are both located on the channel region 180.
In an embodiment of the present invention, forming a source and a drain distributed at both ends with respect to a channel region includes:
forming a metal material layer on the channel region using a metal deposition process;
and carrying out patterning treatment on the metal material layer to obtain the source electrode and the drain electrode.
In the embodiment of the invention, the metal deposition sequence can be 10-30 nm thick titanium and 50-60 nm thick gold; or gold 50-60 nm thick. Preferably, a titanium-gold composite layer is adopted, the lower layer is titanium, and the upper layer is gold; more preferably, the titanium layer of the electrode is 15nm thick and the gold layer is 60nm thick.
The patterning process may use a standard electron beam exposure process, and is not limited herein.
In an alternative embodiment of the invention, a patterned masking layer is formed over the channel region, the patterned masking layer defining the location of the source and drain, prior to forming a layer of metallic material over the channel region using a metal deposition process. In this way, a layer of metallic material formed over the channel region covers the patterned masking layer and the exposed channel region portions.
Further, the step of performing a patterning process on the metal material layer to obtain the source and the drain specifically includes removing a portion of the metal material layer on the patterned mask layer and the patterned mask layer,
in an alternative embodiment, the source and drain electrodes may also use graphene materials.
Referring to fig. 20, a passivation layer 200 is formed on the channel region 180, the source electrode 191 and the drain electrode 192 using an atomic layer deposition method. The passivation layer 200 covers the channel region 180 and also covers portions of the sidewalls of the source and drain electrodes 191 and 192.
The passivation layer 200 is made of aluminum trioxide or hafnium dioxide, the thickness of the passivation layer is 10-50 nm, aluminum trioxide is preferably used as the passivation layer, and the thickness of the passivation layer is more preferably 10 nm.
In an alternative embodiment of the present invention, the passivation layer may completely cover the source and drain electrodes.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
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