阅读说明：本技术 用于内容可寻址存储器单元的设备、系统及方法 (Apparatus, system, and method for content addressable memory cells ) 是由 J·施雷克 D·彭妮 于 2020-05-13 设计创作，主要内容包括：本公开的实施例涉及用于内容可寻址存储器(CAM)单元的设备及方法。每一CAM单元可包含存储信息位的比较器部分。每一CAM单元还可包含将外部位与所述经存储位进行比较的比较器部分。CAM单元群组可被组织成CAM寄存器,其中每一CAM单元共同耦合到信号线。如果所述外部位与所述经存储位不匹配,那么所述CAM单元中的任一者可改变所述信号线上的电压。(Embodiments of the present disclosure relate to apparatus and methods for Content Addressable Memory (CAM) cells. Each CAM cell may include a comparator portion that stores a bit of information. Each CAM cell may also include a comparator portion that compares an outer bit to the stored bits. The group of CAM cells may be organized as a CAM register, with each CAM cell coupled in common to a signal line. Any of the CAM cells may change the voltage on the signal line if the outer bit does not match the stored bit.)

1. An apparatus, comprising:

a latch circuit configured to store a first signal and a second signal, wherein the second bit is complementary to the first bit;

a comparator circuit configured to receive a third signal and a fourth signal, wherein the third signal is complementary to the fourth signal, the comparator circuit comprising:

a first portion configured to activate when the fourth signal is at a first logic level and configured to couple a signal line to a voltage when active when the first signal is at the first logic level; and

a second portion configured to activate when the third signal is at the first logic level and configured to couple the signal line to the voltage when active when the second signal is at the first logic level.

2. The apparatus of claim 1, wherein the latch circuit is configured to receive a fifth signal and a sixth signal complementary to the fifth bit, and to replace the first signal with the fifth signal and the second signal with the sixth signal when a write signal is active.

3. The apparatus of claim 2, wherein the latch circuit comprises a first write transistor coupled between the fifth signal and the first signal and a second write transistor coupled between the sixth signal and the second signal, wherein the first write transistor and the second write transistor have gates commonly coupled to the write signal.

4. The apparatus of claim 1, wherein a logic state of the first signal represents a logic state of a bit stored by the latch circuit.

5. The apparatus of claim 1, wherein the latch circuit comprises a first plurality of transistors all having a first size, and wherein the comparator circuit comprises a second plurality of transistors all having a second size different from the first size.

6. The apparatus of claim 1, wherein the latch circuit comprises:

a first transistor configured to couple a first voltage to the first signal when the second signal is at a second logic level;

a second transistor configured to couple the first voltage to the second signal when the first signal is at a second logic level;

a third transistor configured to couple a second voltage to the first signal when the second signal is at a first logic level; and

a fourth transistor configured to couple the second voltage to the second signal when the first signal is at the first logic level, wherein the first voltage is associated with the first logic level and the second voltage is associated with the second logic level.

7. The apparatus of claim 6, wherein the first portion of the comparator circuit comprises a fifth transistor and a sixth transistor coupled in series between the signal line and the first voltage, wherein the fifth transistor is activated by the first signal at a first logic level and the sixth transistor is activated by the fourth signal at the first logic level, and

wherein the second portion of the comparator circuit comprises a seventh transistor and an eighth transistor coupled in series between the signal line and the first voltage, wherein the seventh transistor is activated by the second signal at the first logic level and the eighth transistor is activated by the third signal at the first logic level.

8. An apparatus, comprising:

a plurality of Content Addressable Memory (CAM) registers, each of the CAM registers comprising a plurality of CAM cells configured to store a respective bit of stored information and further configured to compare the respective bit of stored information with a respective bit of external information; and

a plurality of signal lines, each of the plurality of signal lines coupled to one of the CAM registers, wherein each of the plurality of CAM cells of a given one of the plurality of CAM registers is configured to change a voltage of an associated one of the plurality of signal lines to a first voltage if the respective bit of stored information does not match the respective bit of external information.

9. The apparatus of claim 8, further comprising a driver circuit configured to set voltages of the plurality of signal lines to a second voltage different from the first voltage before any of the CAM cells compares the respective bit of stored information with the respective bit of external information.

10. The apparatus of claim 8, wherein a plurality of external bits are provided in common to each of the plurality of CAM registers.

11. The apparatus of claim 10, wherein there are a same number of the plurality of outer bits and the plurality of CAM cells in each of the plurality of CAM registers.

12. The apparatus of claim 8, wherein each of the plurality of CAM registers is configured to store a memory address associated with a group of memory cells of a memory device, and wherein each of the plurality of CAM cells of a given CAM register is configured to store a bit of the memory address.

13. The apparatus of claim 8, wherein each of the plurality of CAM cells is configured to store a first signal representative of the logic level of the stored bit and a second signal complementary to the first signal, to receive a third signal representative of the logic level of the bit of external information and a fourth signal complementary to the third signal, and to compare the first signal and the fourth signal and the second signal and the third signal.

14. The apparatus of claim 13, wherein each of the plurality of CAM cells is configured to change the voltage of the associated one of the plurality of signal lines to the first voltage if the first signal and the fourth signal match or if the second signal and the third signal match.

15. An apparatus, comprising:

a fuse array configured to provide a row address comprising a plurality of bits;

a fuse latch associated with a group of redundant memory cells, the fuse latch comprising a plurality of Content Addressable Memory (CAM) cells, each of the CAM cells comprising a latch portion configured to store a respective one of the plurality of bits of the row address and a comparator portion;

a row control configured to provide an access address comprising a plurality of bits, wherein the comparator portion is configured to compare a respective bit of the access address with the respective stored bit, and wherein each of the CAM cells is configured to change a state of a matching bit from high to low if the bit of the access address does not match the stored bit.

16. The apparatus of claim 15, further comprising fuse logic circuitry configured to provide the row address to a write signal, wherein each of the plurality of CAM cells in the fuse latch is configured to store the respective one of the plurality of bits of the row address in response to the row address and the write signal.

17. The apparatus of claim 15, wherein the row control is configured to perform an access operation on the group of redundant memory cells if the match bit remains at a high level after comparing the access address with the row address.

18. The apparatus of claim 15, further comprising an inverter circuit configured to invert a plurality of first signals, each first signal representing one of the plurality of bits of the row address to a complementary plurality of second signals, wherein the each of the CAM cells is configured to store a respective one of the plurality of first signals and a respective one of the plurality of second signals.

19. The apparatus of claim 18, further comprising an inverter circuit configured to invert a plurality of third signals, each third signal representing one of the bits of the access address to a complementary plurality of fourth signals, wherein each of the CAM cells of the fuse latch is configured to compare the respective first and fourth signals and the respective second signal to the third signal.

20. The apparatus of claim 19, wherein each of the CAM cells is configured to change the state of the match bit if the respective first signal matches the fourth signal or the respective second signal matches the third signal.

Background

The present disclosure relates generally to semiconductor devices, and more specifically to semiconductor components for storing bits. Semiconductor logic devices may typically operate with binary logic, where signals and information are stored as one or more bits, each of which may be at a high logic level or a low logic level. There may be several applications in which information is stored and it is useful to compare the stored information with external information. For example, a memory device may use a bit string as a row address to refer to a particular group of memory cells. One or more row addresses may be stored and may be compared to incoming row addresses to determine whether there is a match between any of the stored row addresses and the incoming row addresses.

Disclosure of Invention

In at least one aspect, the present disclosure is directed to an apparatus including a latch circuit and a comparator circuit. The latch circuit stores a first signal and a second signal, wherein the second bit is complementary to the first bit. The comparator circuit receives a third signal and a fourth signal, wherein the third signal is complementary to the fourth signal. The comparator circuit includes a first portion that activates when the fourth signal is at a first logic level and, when active, couples a signal line to a voltage when the first signal is at the first logic level. The comparator circuit includes a second portion that activates when the third signal is at the first logic level and, when active, couples the signal line to the voltage when the second signal is at the first logic level.

The latch circuit may receive a fifth signal and a sixth signal complementary to the fifth bit, and replace the first signal with the fifth signal and the second signal with the sixth signal when a write signal is active. The latch circuit may include a first write transistor coupled between the fifth signal and the first signal and a second write transistor coupled between the sixth signal and the second signal, where the first write transistor and the second write transistor may have gates commonly coupled to the write signal.

The logic state of the first signal may represent the logic state of a bit stored by the latch circuit. The latch circuit may include a first plurality of transistors all having a first size, and the comparator circuit may include a second plurality of transistors all having a second size different from the first size.

The latch circuit may include: a first transistor that can couple a first voltage to the first signal when the second signal is at a second logic level; a second transistor that can couple the first voltage to the second signal when the first signal is at a second logic level; a third transistor that can couple a second voltage to the first signal when the second signal is at a first logic level; and a fourth transistor that can couple the second voltage to the second signal when the first signal is at the first logic level, wherein the first voltage is associated with the first logic level and the second voltage is associated with the second logic level. The first portion of the comparator circuit may include a fifth transistor and a sixth transistor coupled in series between the signal line and the first voltage, wherein the fifth transistor may be activated by the first signal at a first logic level and the sixth transistor may be activated by the fourth signal at the first logic level. The second portion of the comparator circuit may include a seventh transistor and an eighth transistor coupled in series between the signal line and the first voltage, wherein the seventh transistor is activatable by the second signal at the first logic level and the eighth transistor is activatable by the third signal at the first logic level.

In at least one aspect, the present disclosure is directed to an apparatus including a plurality of Content Addressable Memory (CAM) registers and a plurality of signal lines. Each of the CAM registers may include a plurality of CAM cells that store a respective bit of stored information and further compare the respective bit of stored information to a respective bit of external information. Each of the plurality of signal lines is coupled to one of the CAM registers, wherein each of the plurality of CAM cells of a given one of the plurality of CAM registers changes a voltage of an associated one of the plurality of signal lines to a first voltage if the respective bit of stored information does not match the respective bit of external information.

The apparatus may also include a driver circuit that may set voltages of the plurality of signal lines to a second voltage different from the first voltage before any of the CAM cells compares the respective bit of stored information with the respective bit of external information. A plurality of external bits may be provided in common to each of the plurality of CAM registers. There may be the same number of the plurality of outer bits and the plurality of CAM cells in each of the plurality of CAM registers.

Each of the plurality of CAM registers may store a memory address associated with a group of memory cells of the memory device, and each of the plurality of CAM cells of a given CAM register may store bits of the memory address. Each of the plurality of CAM cells may store a first signal representative of the logic level of the stored bit and a second signal complementary to the first signal, may receive a third signal representative of the logic level of the bit of external information and a fourth signal complementary to the third signal, and may compare the first signal and the fourth signal and the second signal and the third signal. Each of the plurality of CAM cells may change the voltage of the associated one of the plurality of signal lines to the first voltage if the first and fourth signals match or if the second and third signals match.

In at least one aspect, the present disclosure relates to an apparatus comprising: a fuse array providing a row address comprising a plurality of bits; a fuse latch; and a row control member. The fuse latch is associated with a group of redundant memory cells. The fuse latch includes a plurality of Content Addressable Memory (CAM) cells, each of the CAM cells including a latch portion and a comparator portion that store a respective one of the plurality of bits of the row address. The row control provides an access address that includes a plurality of bits. The comparator portion compares respective bits of the access address with the respective stored bits, and if the bits of the access address do not match the stored bits, each of the CAM cells changes the state of the matching bits from high to low.

The apparatus may also include fuse logic circuitry that may provide the row address to a write signal, wherein each of the plurality of CAM cells in the fuse latch is configured to store the respective one of the plurality of bits of the row address in response to the row address and the write signal. The row control may perform an access operation on the group of redundant memory cells if the match bit remains at a high level after comparing the access address with the row address.

The apparatus may also include an inverter circuit that may invert a plurality of first signals, each first signal representing one of the plurality of bits of the row address to a complementary plurality of second signals, wherein the each of the CAM cells stores a respective one of the plurality of first signals and a respective one of the plurality of second signals. The apparatus may also include an inverter circuit that may invert a plurality of third signals, each third signal representing one of the bits of the access address to a complementary plurality of fourth signals, wherein each of the CAM cells of the fuse latch compares the respective first and fourth signals and the respective second signal to the third signal. Each of the CAM cells may change the state of the match bit if the respective first signal matches the fourth signal or if the respective second signal matches the third signal.

Drawings

Fig. 1 is a block diagram of a Content Addressable Memory (CAM) cell according to the present disclosure.

Fig. 2 is a schematic diagram of a CAM cell according to an embodiment of the disclosure.

Fig. 3 is a block diagram of a CAM cell register according to an embodiment of the disclosure.

FIG. 4 is a block diagram showing a register stack according to an embodiment of the present disclosure.

Fig. 5 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure.

FIG. 6 is a block diagram of a memory array according to an embodiment of the present disclosure.

FIG. 7 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

FIG. 8 is a block diagram of an address sampler in accordance with an embodiment of the disclosure.

Detailed Description

The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure or its application or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Furthermore, for the purpose of clarity, when certain features will be apparent to those skilled in the art, their detailed description will not be so discussed as to avoid obscuring the description of the embodiments of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

Information in a semiconductor device may generally be represented by one or more binary bits, with each bit at a high logic level (e.g., 1) or a low logic level (e.g., 0). Information may be stored in circuits included in semiconductor devices, such as latch circuits. The latch circuit may store a particular bit of information, which may be later retrieved and/or overwritten by a new bit of information to be stored. Groups of latch circuits may be organized together to form registers that store information (e.g., data) including a number of bits. Several registers may be organized into a stack to store multiple pieces of information (e.g., each register may have N latch circuits to store information including N bits, and there may be M registers in the stack). The number of registers in a stack may generally be referred to as the stack depth. There may be many applications where it is useful to be able to search for a register containing particular information in a given register stack, however such circuitry may be relatively space and power consuming.

The present disclosure relates to devices, systems, and methods for content addressable memory cells. In some embodiments of the present disclosure, a Content Addressable Memory (CAM) cell may store a bit of information and allow for addressing of the memory cell (e.g., within a group of CAM cells) based on the content stored in the CAM cell. The CAM cells of the present disclosure include layouts that may allow each CAM cell to occupy a relatively small space on a semiconductor device (e.g., by using fewer components and/or smaller components) and may also allow less power to be drawn when addressing the CAM cell.

A CAM cell according to some embodiments of the present disclosure includes a latch portion and a comparator portion. In such embodiments, the latch portion may store a bit of information, while the comparator portion may compare the stored bit to the supplied external bit. If the comparator section determines that there is no match, the state of the match signal may change from a high logic level to a low logic level. If there is a match, the comparator section may do nothing and the latch signal may remain at a high logic level. When multiple CAM cells are organized into registers, they may be coupled in common to a signal line and may share a latch signal.

Fig. 1 is a block diagram of a Content Addressable Memory (CAM) cell according to an embodiment of the disclosure. CAM cell 100 includes a latch portion 102 and a comparator portion 106.

The latch portion 102 stores bits and provides signals Q and QF indicative of the logic levels of the stored bits. The signals Q and QF may be binary signals at a high logic level (e.g., a first voltage) or a low logic level (e.g., a second voltage). The Q and QF signals are complementary to each other and have opposite logic values. For example, if signal Q is logic high, signal QF may be logic low, and vice versa. Signal Q may represent the logic level of the stored bit, while signal QF may be complementary to the logic level of the stored bit. The latch portion 102 may continue to provide the signals Q and QF as long as the latch portion 102 receives power. In some embodiments, latch portion 102 may receive power whenever a device containing CAM cell 100 is powered up.

CAM cell 100 may receive input signal D and complementary input signal DF. Input signals D and DF are complementary to each other and have opposite logic values. The input bit D may represent the logic value of an input bit provided to overwrite a stored bit currently in the CAM cell. When Write signal Write is at a high logic level, the values of signals D and DF may be written to CAM cell 100. This may cause the values of input signals D and DF to overwrite the current values of stored signals Q and QF, respectively. When the signal Write is at a low logic level, the values of the stored signals Q and QF may be maintained even though the input signals D and DF are provided.

The CAM cell 100 may also include a comparator portion 104. The comparator section 104 may be used when external signals X _ Compare and XF _ Compare are provided. During the comparison operation, the external signals X _ Compare and XF _ Compare are complementary to each other. The signal X _ Compare may represent the logic level of the external portion and the signal XF _ Compare may represent the complement of the logic level of the external portion. When no Compare operation is performed (e.g., when the signal X _ Compare does not represent an external bit), both X _ Compare and XF _ Compare may be at a low logic level. The comparator section 104 determines whether the external signal X _ match matches the stored signal Q and whether the complementary external signal XF _ match matches the complementary stored signal QF. If the external signal X _ Compare does not match the stored signal Q (and thus the complementary external signal XF _ Compare does not match the complementary stored signal QF), the comparator section 104 may provide a BitMatch signal having a low logic level. Conversely, if the external signal X _ Compare does match the stored signal Q (and thus the inverted external signal XF _ Compare matches the inverted stored signal QF), the comparator section 104 may provide a BitMatch signal having a high logic level.

In some embodiments of the present disclosure, the BitMatch signal may have a high logic level prior to performing the Compare operation (e.g., prior to providing X _ match and XF _ match). Thus, if there is no match between the external signal and the stored signal, CAM cell 100 may change the state of signal BitMatch to a low logic level. If the signals Q and X _ Compare (and QF and XF _ Compare) match, the signal BitMatch may remain at a high logic level.

In some embodiments, comparator portion 104 may include a first portion 101 and a second portion 103. Both first portion 101 and second portion 103 may be coupled to signal BitMatch and either first portion 101 or second portion 103 may be capable of changing the logic level of signal BitMatch. The first portion 101 may be activated when the signal XF _ match is at a high logic level, and may be otherwise inactive. The second portion 103 may be activated when the signal X _ Compare is at a high logic level. Since the signals X _ Compare and XF _ Compare are complementary to each other, only one of the first portion 101 or the second portion 103 may be active at a given time. When active, if signal Q is at a high level (e.g., if signals Q and XF _ match), first portion 101 may change signal BitMatch from a high logic level to a low logic level. Similarly, when active, if the signal QF is at a high logic level (e.g., if the signals QF and X _ match), the second portion 102 may change the signal BitMatch from a high logic level to a low logic level.

Fig. 2 is a schematic diagram of a CAM cell according to an embodiment of the disclosure. In some embodiments, CAM cell 200 may implement CAM cell 100 of fig. 1. CAM cell 200 includes a latch portion 202 and a comparator portion 204. CAM cell 200 may generally use voltages to represent the value of each bit. The CAM cell 200 may include a conductive element (e.g., node, conductive line) that carries a voltage representative of the logical value of that bit. For example, a high logic level may be represented by a first voltage (e.g., a system voltage such as VPERI), while a low logic level may be represented by a second voltage (e.g., a ground voltage such as VSS).

Latch portion 202 includes a first transistor 206, the first transistor 206 having a source coupled to a node providing a voltage VPERI, which may represent a high logic level. The first transistor 206 has a drain coupled to a node 217 having a voltage representative of the value of the signal Q and a gate coupled to a node 219 having a voltage representative of the value of the complementary signal QF. The signal Q represents the logic level of the bit stored in the latch portion 202. The first transistor 206 may be a p-type transistor. The latch portion 202 also includes a second transistor 207 having a source coupled to the node providing VPERI, a gate coupled to the node 217, and a drain coupled to the node 219. The second transistor 207 may be a p-type transistor.

The latch portion 202 includes a third transistor 208, the third transistor 208 having a drain coupled to a node 217, a gate coupled to a node 219, and a source coupled to a node providing a ground voltage VSS, which may represent a low logic level. The third transistor 208 may be an n-type transistor. The latch portion 202 includes a fourth transistor 209 having a drain coupled to a node 219, a gate coupled to a node 217, and a source coupled to a node providing a ground voltage VSS. The fourth transistor 209 may be an n-type transistor. Transistors 206 and 208 may form an inverter circuit and transistors 207 and 209 may form another inverter circuit, and the two inverter circuits are cross-coupled to each other.

In operation, the first, second, third and fourth transistors 206 and 209 may operate to store the values of the stored signals Q and QF. Transistor 206 and 209 may work together to couple node 217 carrying Q and node 219 carrying QF to a node providing a system voltage (e.g., VPERI or VSS) associated with the values of signals Q and QF. For example, if the stored signal Q is at a high logic level, the inverted signal QF is at a low logic level. The first transistor 206 may be active and VPERI may be coupled to the node 217. The second transistor 207 and the third transistor 208 may be inactive. The fourth transistor 209 may be active and may couple VSS to the node 219. This may hold node 217 at a voltage of VPERI, which represents a high logic level, and node 219 at a voltage of VSS, which represents a low logic level. In another example, the inverted signal QF may be at a high logic level if the stored signal Q is at a low logic level. The first transistor 206 and the fourth transistor 209 may both be inactive. The second transistor 207 may be active and may couple VPERI to node 219. The third transistor 208 may also be active and may couple VSS to the node 217. In this manner, the stored signals Q and QF may be coupled to respective system voltages corresponding to their current logic levels, which may maintain the current logic value of the stored bits.

The latch portion 202 also includes a fifth transistor 210 and a sixth transistor 211. Transistors 210 and 211 may act as switches that may couple a signal line carrying input data D and a signal line carrying inverted input data DF to nodes 217 and 219, respectively, carrying Q and QF when the Write signal Write is active. The fifth transistor 210 has a gate coupled to a line carrying the Write signal, a drain coupled to the signal D, and a source coupled to the node 219. Sixth transistor 211 has a gate coupled to the Write signal, a drain coupled to the signal DF, and a source coupled to node 219. Thus, when the Write signal is at a high level (e.g., at a voltage such as VPERI), transistors 210 and 211 may be active, and the voltages of signals D and DF may be coupled to nodes 217 and 219, respectively, which carry Q and QF.

In some embodiments, the first through sixth transistors 206 and 211 may all generally have the same size as each other. For example, the transistor 206 and 211 may have a gate width of about 300 nm. In other examples, other sizes of transistors 206 and 211 may be used. The CAM cell 200 also includes a comparator section 204. The comparator section 204 may Compare the signals Q and QF with the signals X _ Compare and XF _ Compare. The signal X _ Compare may represent a logic level provided to an external portion of the comparator section 204. If there is no match between signals Q and X _ Compare (and thus between QF and XF _ Compare), comparator portion 206 may change the state of the BitMatch signal from a first logic level (e.g., a high logic level) to a second logic level (e.g., a low logic level). For example, if the stored bit and the external bit do not match, the comparator section 204 may couple the ground voltage VSS to a signal line carrying the signal BitMatch. In some embodiments, if there is a match between the stored bit and the external bit, the comparator portion 206 may do nothing. In some embodiments, the signal BitMatch may be precharged to a voltage associated with a high logic level (e.g., VPERI) prior to the comparison operation. During the precharge operation, both X _ Compare and XF _ Compare may remain at a low logic level.

The comparator section includes a seventh transistor 212, an eighth transistor 213, a ninth transistor 214, and a tenth transistor 215. The seventh transistor 212 and the ninth transistor 214 may implement the first portion 101 of fig. 1. The eighth transistor 213 and the tenth transistor 215 may implement the second portion 103 of fig. 1. The seventh transistor 212 includes a drain coupled to the signal BitMatch, a gate coupled to the node 217 (e.g., signal Q), and a source coupled to the drain of the ninth transistor 214. The ninth transistor 214 also has a gate coupled to the signal XF _ match and a source coupled to a signal line that provides the ground voltage VSS.

The eighth transistor 213 has a drain coupled to the signal BitMatch, a gate coupled to the node 219 (e.g., the signal QF), and a source coupled to the drain of the tenth transistor 215. The tenth transistor has a gate coupled to the signal X _ match and a source coupled to the ground voltage VSS.

Since the signal Q is complementary to the signal QF, the comparator section 202 may operate by comparing the external signal X _ Compare with the signal QF to see if they match and comparing the inverted external signal XF _ Compare with the stored signal Q to see if they match. If they match, it may indicate that signal X _ Compare does not match signal Q and signal XF _ Compare does not match signal QF, and thus the external bit does not match the associated stored bit.

Comparator portion 204 may use relatively few components because it changes signal BitMatch from a known state (e.g., a precharged high logic level) to a low logic level. Therefore, it may not be necessary to include additional components (e.g., additional transistors) to change the logic level of the signal BitMatch from low to high, or from an unknown level to low or high. Comparator section 204 can take advantage of this to provide dynamic logic. For example, comparator portion 204 has two portions (e.g., transistor 212/214 and transistor 214/215), either of which may couple signal BitLine to voltage VSS, provided there is no match between the stored bit and the external bit. Since only one of the portions is active at a time, the active portion only needs to check the state of the signal Q or QF. Either of the two portions is also capable of changing the signal BitMatch to a low logic level.

In an example operation, if the stored signal Q is at a logic high level (and thus the signal QF is low) and the external signal X _ Compare is also high (and the signal XF _ Compare is low), the external signal may match the stored signal, and the transistors 212 and 215 may be active, while the transistors 214 and 213 are inactive. This may prevent the ground voltage VSS from being coupled to the signal BitMatch. If the signal X _ Compare is low (e.g., if there is no match), the external signal may not match the stored signal, and transistors 212 and 214 may be active while transistors 213 and 215 are inactive. Transistors 212 and 214 are active at the same time to couple ground voltage VSS to signal BitMatch.

In another example operation, if the stored signal Q is low (and thus the signal QF is high), the transistor 212 may be inactive while the transistor 213 is active. If the external signal X _ Compare is low (and XF _ Compare is high), the external signal can match the stored bit and transistor 214 is active while transistor 215 is inactive. If the signal X _ Compare is high (and the signal XF _ Compare is low), the external signal may not match the stored signal and transistor 214 may be inactive, while transistor 215 is active. Thus, signal BitMatch may be coupled to ground voltage VSS through active transistors 213 and 215.

In some embodiments, the transistors 212 and 215 of the comparator section 204 may all generally have the same size as each other. In some embodiments, the transistors 212 and 215 of the comparator portion 204 may have different sizes than the transistors 206 and 211 of the latch portion 202. For example, the transistor 212 and 215 may have a gate width of about 400nm and a gate length of about 45 nm. In other examples, other sizes of transistors 212 and 215 may be used.

Fig. 3 is a block diagram of a CAM cell register according to an embodiment of the disclosure. CAM cell register 300 includes a plurality of CAM cells 318(0) -318(n), each of which CAM cells 318(0) -318(n) may be CAM cell 100 of fig. 1 and/or 200 of fig. 2. CAM cell register 300 may store a plurality of bits of information (e.g., stored bits Q (0) through Q (n)). The CAM cells 318 of the CAM cell register 300 may be commonly coupled to a signal line that provides a signal register match having a voltage representing a match bit having a logic state based on a comparison between the information stored across the CAM cells 318 of the CAM cell register 300 and an external signal X _ match.

CAM cell register 300 includes a number of individual CAM cells 318, each of the number of individual CAM cells 318 may store a bit of information and provide signals Q and QF, where signal QF has a complementary logic level to signal Q. The signal Q may have a logic level that matches the logic level of the stored bit. CAM cell register 300 may include a number of CAM cells 318 to hold multi-bit information. For example, CAM cell register 300 may hold a row address that may be n bits long, and thus there may be n different CAM cells 318. The bits may be loaded into CAM register 300 using input terminals (e.g., which may receive input signals D and DF of FIGS. 1-2) and a Write signal not shown here (e.g., signal Write of FIGS. 1-2). A first information bit Q (0) may be loaded into a first CAM cell 318(0), a second information bit Q (2) may be loaded into a second CAM cell 318(1), and so on. In some embodiments, the input data D (0) - (n) may be provided along with the complementary input data DF (0) - (n). In some embodiments, only the input data D (0) - (n) may be provided, and one or more inverter circuits may be used to generate and provide the complementary data DF (0) - (n) to the respective CAM cells 318.

During the Compare operation, data X _ Compare may be provided to CAM cell register 300. Data X _ Compare may be the same type of information (e.g., row address) as that stored in CAM cell register 300. Data X _ Compare may be a multi-bit signal and may have n bits to match the number of CAM cells 318 of CAM cell register 300. When data X _ Compare is provided, it may be divided into different individual bits and provided to the associated CAM cell 318. Thus, the first outer bit X _ match (0) may be provided to CAM cell 318(0) containing stored bit Q (0), the second outer bit X _ match (1) may be provided to CAM cell 318(1) containing stored bit Q (1), and so on. In some embodiments, the external data X _ Compare may be provided along with the complementary data XF _ Compare. In some embodiments, only the data X _ match may be provided, and one or more inverter circuits may be used to generate and provide the complementary data XF _ match to the CAM cells 318 of the CAM cell register 318.

Each of the CAM cells 318 may be commonly coupled to a signal line that provides a signal register match. The signal register match may implement the signal BitMatch of fig. 1-2. The signal register match may be coupled to a register match driver 316. The register match driver 316 may precharge a voltage of the signal register match to a first voltage representing a high logic level. In some embodiments, the register match driver 316 may precharge the voltage of the register match to a first voltage every time the external signal X _ match is supplied. If the stored signal Q (i) in the memory cell 318 does not match the associated external signal X _ Compare (i), then any of the CAM cells 318 may couple the signal RegisterMatch to a second voltage (e.g., ground voltage) representing a low logic level. As previously described, the stored signal q (i) may be compared to the external signal X _ compare (i) and the complementary stored signal qf (i) may be compared to the complementary external signal XF _ compare (i). In some embodiments, the signal register match may be coupled to a second voltage if the stored signal q (i) matches the complementary external signal XF _ match (i) or the complementary stored signal qf (i) matches the external signal X _ match (i).

Thus, if each bit of the external signal X _ Compare matches each of the associated stored signals Q, the signal RegisterMatch will only remain at the first voltage (e.g., a high logic level). In other words, the register match may function as if each of the CAM cells 318 provides a match signal (e.g., the BitMatch of fig. 1-2) that is provided as an input to an AND gate that then provides the signal register match.

FIG. 4 is a block diagram showing a register stack according to an embodiment of the present disclosure. Register stack 400 includes a number of CAM cell registers 420, each of which number of CAM cell registers 420 may be CAM cell register 300 of fig. 3. There may be m different CAM cell registers 420 in the stack (e.g., the stack may be m deep). Each of the CAM cell registers 420 may be coupled to a respective signal line register Match (e.g., register Match (0-m)).

During a search operation, external information X _ Compare may be provided to each of the CAM cell registers 420. The external information X _ Compare may be commonly provided to the CAM cell register 420, and may serve as the external information X _ Compare of fig. 3. The information X _ Compare may be a multi-bit signal, and each of the CAM cell registers 420 may have the same number of individual CAM cells (e.g., 100 of fig. 1) as the number of bits in X _ Compare. Each of the CAM cell registers 420, register 0 through register m, is coupled to a respective signal line, register Match (0) through register Match (m). Each of the register match signal lines may provide a signal indicating whether the provided information X _ match exactly matches the data stored in the associated CAM cell register 420. The register match signal line may carry a voltage that may represent the logic level of the match bit, and the match bit may be at logic high (e.g., a first voltage) if the information X _ match matches the contents of the CAM cell register 420 associated with the respective register match signal line. If there is one or more bits of X _ Compare that do not match the data stored in the CAM cell register 420, then the respective signal line register match may be at a second voltage, which represents that the matching bits are at a low logic level.

After the Compare operation, the state of the register match (0-m) may be used to determine which of the CAM cell registers 420 contain a full match for X _ Compare. For example, if each of the CAM cell registers is associated with a physical location, that location may be accessed if the associated signal line RegisterMatch is at a first voltage (e.g., the match bit is at a high logic level).

An example environment in which the CAM cells, registers, and stacks of the present disclosure may be useful is in semiconductor memory devices. The memory device may be used to store one or more bits of information in an array of memory cells containing a plurality of memory cells, each of the plurality of memory cells including one or more bits of information. Memory cells can be organized at the intersections of rows (word lines) and columns (bit lines). During various operations, a memory device may access one or more memory cells along designated word lines or bit lines by providing row and/or column addresses that specify the word lines or bit lines. There may be memory operations in which the CAM cells, registers, and stacks of the present disclosure (e.g., as described in fig. 1-4) are useful for comparing row and/or column addresses with row and/or column addresses stored in a CAM cell stack.

One example application is a memory repair operation in a memory device. One or more of the memory cells of the memory device may become defective. Row and/or column addresses associated with defective memory cell(s) may be reassigned to redundant rows/columns of the memory array. This may be accomplished, for example, by changing the state(s) of one or more fuses (and/or antifuses) in the fuse array. The state of the fuses may represent the row/column address to be repaired, which may broadcast to the fuse latches associated with the redundant row/column. When the memory attempts to access a repaired row/column, if the incoming row/column address matches the row/column address stored in the fuse latch, the redundant row/column associated with that fuse latch is accessed instead of the defective row/column. A CAM cell register (e.g., 300 of fig. 3) may be used as a fuse latch and a match bit may be used to determine whether an incoming row/column address exactly matches a row/column address stored in the fuse latch.

Another example application of the CAM cells, registers, and stacks of the present disclosure is a refresh operation in a memory device. The information in the memory cells may decay over time and may need to be refreshed periodically (e.g., by rewriting the original values of the information to the memory cells). Repeated accesses to a particular row of memory (e.g., an aggressor row) may cause the decay rate of an adjacent row (e.g., a victim row) to increase due to, for example, electromagnetic coupling between the rows. This may be commonly referred to as a 'hammer' row or row hammer event. To prevent information from being lost due to row hammer, it may be necessary to identify the aggressor's row so that the corresponding victim row can be refreshed (' row hammer refresh ' or RHR). The row address of the accessed row may be stored and may be compared to the new row address to determine whether one or more rows require an RHR operation. A CAM cell stack (e.g., 400 of fig. 4) may be used to store an accessed address and a respective match bit may be used to determine whether an incoming row address matches any of the row addresses stored in the CAM cell stack. This may allow the accesses to a row to be counted in order to determine whether they are hammered.

Fig. 5 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device 500 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. Semiconductor device 500 may include one or more CAM cells (e.g., CAM cells 100 and/or 200 of fig. 1-2, CAM cell register 300 of fig. 3, and/or CAM cell stack 400 of fig. 4).

The semiconductor device 500 includes a memory array 542. In some embodiments, memory array 542 may include multiple memory banks. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL and/BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL and/BL. Selection of word line WL is performed by row control 534 and selection of bit lines BL and/BL is performed by column control 540. The bit lines BL and/BL are coupled to respective Sense Amplifiers (SAMP). Read data from bit line BL or/BL is amplified by sense amplifier SAMP 547 and transferred to read/write amplifier 550 through complementary local data line (LIOT/B), Transfer Gate (TG)548, and complementary main data line (MIO). Conversely, the write data output from the read/write amplifier 550 is transferred to the sense amplifier 547 through the complementary main data line MIO, the transfer gate 548 and the complementary local data line LIOT/B, and written in the memory cell MC coupled to the bit line BL or/BL.

The semiconductor device 500 may employ a plurality of external terminals including a command and address (C/a) terminal coupled to a command and address bus to receive commands and addresses, a clock terminal for receiving clocks CK and/CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

The clock terminal is supplied with the external clocks CK and/CK supplied to the clock input circuit 552. The external clocks may be complementary. The clock input circuit 552 generates the internal clock ICLK based on the CK and/CK clocks. The ICLK clock is provided to the command control 536 and the internal clock generator 554. The internal clock generator 554 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock may be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input/output circuitry 556 to time the operation of the circuitry included in the input/output circuitry 556, e.g., to a data receiver to time the receipt of write data.

The C/a terminal may be supplied with a memory address. The memory address supplied to the C/a terminal is transmitted to the address decoder 534 via the command/address input circuit 532. The address decoder 534 receives the address and supplies a decoded row address XADD to row controls 534 and a decoded column address YADD to column controls 540. The address decoder 534 may also supply a decoded bank address BADD, which may indicate a bank of the memory array 548 that contains a decoded row address XADD and a column address YADD. The C/a terminal may be supplied with a command. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, among other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell(s) to be accessed.

Commands may be provided to command control 536 as internal command signals via command/address input circuitry 532. Command control 536 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command control 536 may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

The device 500 may receive an access command as a row activate command ACT. When receiving a row activate command ACT, the row activate command ACT is supplied to the memory address BADD and the row address XADD in time.

The device 500 may receive an access command as a read command. When a read command is received, the read command is supplied to the bank address and the column address in time, reading read data from the memory cells in the memory array 542 corresponding to the row address and the column address. The read command is received by command control 536, which provides internal commands such that read data from memory array 542 is provided to read/write amplifier 550. The read data is output from the data terminal DQ to the outside via the input/output circuit 556.

The device 500 may receive an access command as a write command. When a write command is received, the write command is supplied to the bank command and the column address in time, and write data supplied to the data terminal DQ is written to memory cells in the memory array 542 corresponding to the row address and the column address. The write command is received by command control 536, which provides internal commands such that write data is received by a data receiver in input/output circuitry 556. The write clock may also be provided to an external clock terminal to time the receipt of write data by the data receiver of input/output circuit 556. Write data is supplied to the read/write amplifiers 550 via the input/output circuits 556 and through the read/write amplifiers 550 to the memory array 542 to be written into the memory cells MC.

One example application of the CAM cells described in this disclosure is as fuse latches 564 associated with redundant word lines (and/or redundant bit lines) of a memory array 542. While repair operations may generally be described with respect to redundant rows (and row latches), it should be understood that redundant columns (and column latches) may operate in a similar manner.

Fuse latch 564 may be used as part of a repair operation. During a repair operation, memory addresses previously associated with defective memory rows may be reassigned so that they are instead associated with one of the redundant word lines. The repair operation may be performed by 'blowing' one or more fuses (and/or antifuses) of the fuse array 560. The fuse array 560 may include a number of fuses, each of which may have a state representing a bit. The state of one or more fuses may be permanently changed (blown) for programming in a particular binary data segment. During a repair operation, an address to be repaired may be programmed into the fuse array 560 by blowing fuses.

Each redundant word line (and/or redundant bit line) may be associated with a fuse latch 564. The states of the fuses in the fuse array 560 may be provided along a fuse bus. The fuse logic circuit 562 may provide a select signal (e.g., a write signal) that causes a repaired address represented by a value of a fuse in the fuse array 560 to be stored in the fuse latch 564. When the memory performs an access operation, the row address XADD may be compared to the address in the fuse latch 564 and, if there is a match, the access operation may be performed on the redundant row associated with the fuse latch 564 instead of the original word line to which the address refers. In this manner, the repaired address may be redirected to the redundant row.

Each of fuse latches 564 may be a CAM cell register, such as CAM cell register 300 of FIG. 3. If any address has been repaired, the fuse array 560 may provide a row address along the fuse bus, and the fuse logic 562 may provide a select signal (which may serve as the signal Write of FIGS. 1-2) to allow the bits of the repaired address to be written as stored bits Q and QF (e.g., the bits of the repaired address may be the input bits D and DF) in the CAM cells of the fuse latch 564. In some embodiments, one or more inverter circuits may be used to generate the inverted input bit DF based on the input bit D provided along the fuse bus.

When the row address XADD is provided, it may serve as the external data X _ match (e.g., of fig. 3-4) and the fuse latch may change the value of the match bit if any of the external data bits does not match the corresponding stored bit. If the match bit remains high, it may indicate that the row address XADD matches the address stored in fuse latch 564, and an access operation may be performed on the associated redundant word line.

Another example application of the CAM cell described in the present application includes tracking aggressor addresses in order to refresh the victim word line associated with those aggressor addresses. The device 500 may also receive commands that cause it to perform refresh operations. The refresh signal AREF may be a pulse signal that is activated when the command control 536 receives a signal indicating a refresh mode. In some embodiments, the refresh command may be issued externally to the memory device 500. In some embodiments, the refresh command may be periodically generated by a component of the device. In some embodiments, the refresh signal AREF may also be activated when the external signal indicates a refresh entry command. The refresh signal AREF may be activated once immediately after the command input, and may be cyclically activated thereafter at a desired internal timing. Thus, the refresh operation may automatically continue. The self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to the IDLE state.

The refresh signal AREF is supplied to the refresh control circuit 546. The refresh control circuit 546 supplies a refresh row address RXADD to the row control members 534, which row control members 534 can refresh the word line WL indicated by the refresh row address RXADD. The refresh control circuit 546 may control the timing of refresh operations, and may generate and provide a refresh address RXADD. The refresh control circuit 546 can be controlled to change the details of the refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address), or can operate based on internal logic.

The memory device 500 may perform two types of refresh operations, an auto-refresh operation and a targeted refresh operation. The auto-refresh operation may involve sequentially refreshing different word lines of the memory array 542 such that each word line is refreshed at least once in a cycle based on an expected decay rate of information in the memory cells. The refresh control circuit 546 may provide a refresh address RXADD from a sequence of refresh addresses. In some embodiments, the refresh address RXADD associated with an auto-refresh operation may cause multiple word lines of the memory array 542 to be refreshed concurrently.

The victim word line of the identified aggressor word lines can be refreshed using the target refresh operation. In some embodiments, refresh operations that would normally be used for auto-refresh operations may be 'stolen' and instead used for targeted refresh operations. The victim word line may be physically close to the aggressor word line. For example, in some embodiments, the victim word line may include word lines (e.g., R +1 and R-1) that are physically adjacent to the aggressor word lines. In some embodiments, the victim word line can include word lines adjacent to adjacent word lines (e.g., R +2 and R-2).

To perform a targeted refresh operation, an aggressor word line must be identified based on the access pattern to that word line. Refresh control circuit 546 may store row address XADD in a CAM register stack (e.g., CAM register stack 400 of fig. 4). Each CAM cell register may store a row address XADD. The incoming row address may be compared to a previously stored row address to determine whether a particular row is accessed frequently. In some embodiments, each register in the stack may be associated with a count value that may be used to track the number of accesses to a row address stored in the associated register. Once an aggressor is identified, one or more victim addresses can be calculated based on the aggressor addresses and then provided as a refresh address RXADD.

The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 558. The internal voltage generator circuit 558 generates various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is primarily used in the row control 534, the internal potentials VOD and VARY are primarily used in the sense amplifier SAMP included in the memory array 542, and the internal potential VPERI is used in many peripheral circuit blocks.

The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 556. In the embodiments of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input/output circuit 556 so that power supply noise generated by the input/output circuit 556 is not propagated to other circuit blocks.

FIG. 6 is a block diagram of a memory array according to an embodiment of the present disclosure. FIG. 6 shows an example environment in which the CAM cells of the present disclosure may be used in order to implement fuse latches (e.g., fuse latches 564 of FIG. 5). FIG. 6 shows the transmission path of a fuse bus from a pair of fuse arrays 560a and 560b through the memory array 600. In some embodiments, memory array 600 may be an implementation of memory array 542 of FIG. 1. The memory array 200 includes 16 banks 668. The 16 banks 668 are organized into four bank groups (BG0-BG3) of four respective banks 668. Each of the banks 668 is associated with a fuse latch, such as a set of row latches 664 and column latches 666. The row latches 664 and the column latches 666 may implement the fuse latches 564 of FIG. 5. Each of the row latches 664 and/or the column latches 666 may include the CAM cell register 300 of FIG. 3.

Each row latch 664 and column latch 666 may be associated with a respective redundant row or column of memory. Each row latch 664 and column latch 666 may be a CAM cell register having a plurality of CAM cells. The row latches 664 may have a number of CAM cells equal to the number of bits in the row address, while the column latches 666 may have a number of CAM cells equal to the number of bits in the column address. Using the operation of row latch 664 as an example, the row latches may receive repaired row addresses along the fuse bus from fuse arrays 660 a-b. The row address may be accompanied by a select signal, which may serve as a write signal for the CAM cell of row latch 664. Each bit of the row address may be stored in a latch portion (e.g., latch portion 102 of fig. 1 or 202 of fig. 2) of a respective one of the CAM cells. Each bit of the row address may be accompanied by a portion of a select signal that serves as a write signal for the CAM cell that is to store that bit.

The row latches 664 may collectively receive an incoming row address XADD. In some embodiments, only some of the row latches 664 (e.g., the row latches 664 of a given bank) may collectively receive a row address XADD. The row latch 664 receiving the row address may compare the row address with the address stored in the row latch 664. For example, each row of latches 664 may be coupled to a signal line (e.g., the signal line register match of fig. 3) that may carry a voltage associated with the value of the match bit. Prior to comparing the row address, a driver circuit (e.g., 316 of fig. 3) may precharge the signal lines to a voltage associated with a high logic level. Each CAM cell of a given row latch 664 may compare a bit of a row address to a stored bit and may change the voltage of the signal line if there is no match. In this manner, the signal lines may only remain at the first voltage (e.g., a high logic level) if all bits of the address match all bits of the row address. When the signal line remains at a high logic level, only the row associated with the row latch 664 may be accessed.

A fuse bus may be used to provide addresses from the fuse array 660a-b to the row latches 664 and the column latches 666. In the particular embodiment of FIG. 6, there may be a pair of fuse arrays 660a and 660 b. Fuse array 660a may include a set of fuses and/or antifuses that may typically be used to store address information for a first portion of a row address. Fuse array 660b may include a set of fuses and/or antifuses that may typically be used to store address information for a second portion of the row address. In some embodiments, the row address may be divided between the first portion and the second portion based on a value assigned to the address.

Fuse arrays 660a-b may include groups of fuses that may be used to record memory addresses for repair. For example, when a defective row of memory is identified, an address associated with the defective row may be programmed into one of fuse arrays 660a-b by blowing one or more fuses. The blown fuse group may be associated with a particular row of redundant memory. During a broadcast operation, the fuse arrays 660a-b may broadcast row addresses stored in the fuse arrays 660a-b along the fuse bus. In some embodiments, fuse logic circuit 662 may receive addresses from both fuse arrays 660a-b, and may alternately provide addresses along the fuse bus from the first and second fuse arrays 660a and 660b to row latches 664 and column latches 666.

After exiting fuse logic 662, the fuse bus may pass data through one or more option circuits 663. The option circuits 663 may include various settings of the memory that may interact with addresses along the fuse bus. For example, the option circuit 663 may include fuse settings, such as test mode and power supply fuses. Data stored in fuse arrays 660a-b may be latched and/or read by option circuits 663, which option circuits 663 may then determine one or more properties of the memory based on the option data provided along the fuse bus.

After passing through the option circuits 663, the fuse bus may pass through the row latches 664 of all memory banks 668 before passing through the column latches 666 of all memory banks 668. In addition to providing data (including address data) along the fuse bus, fuse logic circuit 662 may also provide one or more select signals along the fuse bus. The select signal may be associated with a particular data packet along the fuse bus and may determine which circuit along the fuse bus the particular data packet is associated with. The select signal may serve as the write signal described in fig. 1-2 and may allow data to be written to the latch portion of either the row latch 664 or the column latch 666 associated with the select signal. For example, if the row latch select signal is in an active state, it may indicate that a data packet is to be stored in the row latch 664. In some embodiments, this may overwrite an address already stored in the row latch 664 with an address from the fuse bus. A further select signal may be used to specify a particular location (e.g., bank group select signal, bank select signal, etc.) of a particular row latch 664 that is intended to store a data packet.

FIG. 7 is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. FIG. 7 shows an example application of the CAM cell of the present disclosure as a way to track access to the word lines of a memory in order to detect a row hammer event. In some embodiments, the refresh control circuit 746 may implement the refresh control circuit 546 of FIG. 5. Dashed line 742 is shown to represent that in some embodiments, each of the components (e.g., refresh control circuitry 746 and row control 738) may correspond to a particular memory bank, and these components may be repeated for each of the memory banks. Thus, there may be multiple refresh control circuits 746 and row controls 738. For the sake of brevity, only the components of a single memory bank will be described.

The DRAM interface 733 may provide one or more signals to the address refresh control circuit 746 and the row control 738. Refresh control circuit 746 may include a sampling signal generator 768, an address sampler 767, a Row Hammer Refresh (RHR) state controller 765, and a refresh address generator 769. The DRAM interface 733 may represent one or more components of a memory device (e.g., device 500 of fig. 5) that provide one or more control signals, such as an auto-refresh signal AREF, and a row address XADD to a refresh control circuit 746 and/or a row control 738. The sampling signal generator 768 generates a sampling signal ArmSample at random timing.

The address sampler 767 may sample (e.g., latch) the current row address XADD in response to activation of ArmSample. The address sampler 767 may also provide one or more of the latched addresses as a matched address, HitXADD, to the refresh address generator 769. Address sampler 767 may include a CAM register stack (e.g., CAM register stack 400 of fig. 4) that may be used to count accesses to different row addresses XADD.

The RHR state controller 765 may provide a signal RHR to indicate that a row hammer refresh (e.g., a refresh of a victim row corresponding to an identified aggressor row) should occur. The RHR state controller 765 may also provide an internal refresh signal IREF to indicate that an auto-refresh should occur. In response to the activation of the RHR, the refresh address generator 769 may provide a refresh address RXADD, which may be an auto-refresh address or may be one or more victim addresses corresponding to victim rows of the aggressor row corresponding to the matching address HitXADD. The row control 738 may perform a refresh operation in response to the refresh address RXADD and the row hammer refresh signal RHR. The row control 738 may perform an auto-refresh operation based on the refresh address RXADD and the internal refresh signal IREF.

DRAM interface 733 may represent one or more components of a component that provides signals to a bank. For example, DRAM interface 733 may represent a component of, for example, command address input circuit 532, address decoder 534, and/or command decoder 536 of FIG. 5. The DRAM interface 733 may provide a row address XADD, an auto refresh signal AREF, an activation signal ACT, and a precharge signal Pre. The auto-refresh signal AREF may be a periodic signal that may indicate when an auto-refresh operation is to occur. An activation signal ACT may be provided to activate a given bank of the memory. A precharge signal Pre may be provided to precharge a given bank of the memory. The row address XADD may be a signal including multiple bits (which may be transmitted serially or in parallel) and may correspond to a particular row of an activated memory bank.

The sampling signal generator 768 provides a sampling signal ArmSample. The address sampler 767 may receive a row address XADD from the DRAM interface 733 and an ArmSample from the sample signal generator 768. The row address XADD may change as the DRAM interface 733 directs access operations (e.g., read and write operations) to different rows of a memory cell array (e.g., memory cell array 542 of fig. 9). Each time address sampler 767 receives an activation (e.g., a pulse) of ArmSample, address sampler 767 may sample and may save a current value of XADD in a CAM register of the CAM stack.

The address sampler 767 may determine whether one or more rows are aggressor rows based on the sampled row address XADD, and may provide the identified aggressor row as a matching address HitXADD. As part of this determination, address sampler 767 may record (e.g., by latching and/or storing in a register) the current value of XADD in response to activation of ArmSample. The current value of XADD may be compared to previously recorded addresses (e.g., addresses stored in latches/registers) in address sampler 767 to determine the access pattern of the sampled addresses over time. If address sampler 767 determines that the current row address XADD is repeatedly accessed (e.g., is an aggressor row), activation of ArmSample may also cause address sampler 767 to provide the address of the aggressor row as the matching address HitXADD. In some embodiments, the matching address (e.g., aggressor address) HitXADD may be stored in a latch circuit for later retrieval by the refresh address generator 769.

The address sampler 767 may store the values of the sampled addresses in a CAM cell register of a CAM stack (e.g., CAM register stack 420 of fig. 4), and may have a counter associated with each of the stored addresses. When ArmSample is activated, the value of the counter may be incremented if the current row address XADD matches one of the stored addresses. In response to the activation of ArmSample, address sampler 767 may provide the address associated with the highest value counter as the matching address, HitXADD. Other methods of identifying an aggressor address may be used in other examples.

The RHR state controller 765 may receive the auto-refresh signal AREF and provide a row hammer refresh signal RHR. The auto-refresh signal AREF may be generated periodically and may be used to control the timing of refresh operations. The memory device may perform a sequence of auto-refresh operations in order to periodically refresh the rows of the memory device. The RHR signal may be generated to indicate that the device should refresh a particular target row (e.g., a victim row) instead of an address from an auto-refresh address sequence. The RHR state controller 765 may use internal logic to provide the RHR signal. In some embodiments, the RHR state controller 765 may provide the RHR signal based on a particular number of activations of the AREF (e.g., every 4 activations of the AREF). The RHR state controller 765 may also provide an internal refresh signal IREF, which may indicate that an auto-refresh operation should occur. In some embodiments, signals RHR and IREF may be generated such that they are not active at the same time (e.g., both are not at a high logic level at the same time).

Refresh address generator 769 may receive row hammer refresh signal RHR and matching address HitXADD. The matching address HitXADD may represent an aggressor row. The refresh address generator 769 may determine the location of one or more victim rows based on the matching address HitXADD and provide them as the refresh address RXADD. In some embodiments, the victim row may include rows (e.g., HitXADD +1 and HitXADD-1) that are physically adjacent to the aggressor row. In some embodiments, the victim row may also include rows (e.g., HitXADD +2 and HitXADD-2) that are physically adjacent to physically adjacent rows of the aggressor row. In other examples, other relationships between the victim row and the identified aggressor row may be used.

The refresh address generator 769 may determine the value of the refresh address RXADD based on the row hammer refresh signal RHR. In some embodiments, the refresh address generator 769 may provide one of the auto-refresh address sequences when the signal RHR is not active. When signal RHR is active, refresh address generator 1092 may provide a target refresh address, such as a victim address, as refresh address RXADD.

Row control 738 may be configured to perform one or more operations on a memory array (not shown) based on the received signals and addresses. For example, in response to an activation signal ACT and a row address XADD (and IREF and RHR are at low logic levels), row control 738 may direct one or more access operations (e.g., read operations) to the designated row address XADD. In response to either (or both) of the RHR or IREF signals being active, row control 738 may refresh address RXADD.

FIG. 8 is a block diagram of an address sampler in accordance with an embodiment of the disclosure. In some embodiments, address sampler 800 may be used to implement address sampler 767 of FIG. 7. Address sampler 800 includes CAM register stack 870, which may be CAM register stack 400 of fig. 4. Address sampler 800 may include CAM register stacks 870, where each of the CAM register stacks 870 may have a corresponding counter 871. The counter 871 can be coupled to a comparator 872, which comparator 872 can be coupled to a pointer 874 through a counter scrambler 873. The register 870 may be coupled to an address latch 875, which address latch 875 may store and provide the identified row hammer address as the matching address HitXADD.

The address sampler 800 may sample the current row address XADD in response to a sampling signal ArmSample. The sample signal ArmSample may also cause the address sampler 800 to determine whether a sampled address (e.g., an address stored in one of the registers 870) is a row hammer address and store it on the address latch 875, where the sampled address may be provided to a refresh address generator (e.g., refresh address generator 769 of fig. 7) as the matching address HitXADD.

Each time a sampling signal ArmSample is provided, the current row address XADD may be compared to an address stored in CAM register stack 870. The current row address XADD may be provided as external data X _ match (e.g., as in fig. 3-4) to each of the CAM registers of CAM register stack 870. Each of the CAM registers of CAM register stack 870 may provide a match bit indicating whether the row address XADD exactly matches an address already stored in each of the CAM registers.

If the current address XADD is already stored in one of the registers (e.g., if at least one of the match bits is at a high logic level), the counter 871 associated with that register 870 may be incremented. If the current address XADD is not already stored in one of the CAM cell registers of stack 870 (e.g., if all of the match bits are at a low logic level), it may be added to one of the registers of CAM register stack 870. If an open CAM cell register (e.g., a register without a latched address) is present, the sampled address XADD may be stored in the open register. If there is no open register, the register associated with the counter 871 having the lowest value (as indicated by the pointer 874) may have its latched address replaced with the sampled address XADD. In either case, the row address XADD may be provided along with a Write signal at a high logic level (e.g., signal Write of fig. 1-2), which may cause bits of the row address XADD to overwrite data previously stored in the CAM cell register.

The ArmSample signal may also cause the comparator 872 to determine the counter 871 with the maximum and minimum values. These may be provided to a counter scrambler 873, which counter scrambler 873 may match the maximum and minimum counters 871 to their respective associated registers 870. The pointer 874 may point to the CAM cell register of the CAM stack 870 associated with the largest count value in the counter 871 and may point to the CAM register stack 870 associated with the smallest count value in the counter 871. When a new address XADD is sampled and there is no open register 870 to store it, the register 870 may be overwritten with a minimum pointer. The signal ArmSample may cause the address stored in the CAM register stack 870 indicated by the largest pointer to be stored in the address latch 875.

The address stored in address latch 875 may be provided as a matching address, HitXADD. When a target refresh operation is carried out based on the address HitXADD (e.g., when a victim address associated with the HitXADD is refreshed), the counter 871 associated with the refresh operation may be reset.

Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and/or processes, or separated and/or performed among separate devices or device portions, in accordance with the present systems, devices, and methods.

Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to example embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. The specification and drawings are accordingly to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.