阅读说明：本技术 存储装置及其操作方法 (Storage device and operation method thereof ) 是由 洪志满 于 2021-02-20 设计创作，主要内容包括：本技术涉及一种电子装置。更特别地,本技术涉及一种存储装置及其操作方法。根据实施例的存储器装置包括：存储器单元阵列,包括多个存储器单元；外围电路,被配置为执行编程操作；编程验证器,被配置为当完成编程操作时计算差值,差值中的每一个是编程状态中各自的编程状态的第一通过循环计数和第二通过循环计数之间的差值,并且根据是否差值中的至少一个超过参考值来输出通过状态或失败状态。(The present technology relates to an electronic device. More particularly, the present technology relates to a memory device and an operating method thereof. The memory device according to the embodiment includes: a memory cell array including a plurality of memory cells; peripheral circuitry configured to perform a programming operation; a program verifier configured to calculate difference values when a program operation is completed, each of the difference values being a difference value between a first pass cycle count and a second pass cycle count of a respective program state of the program states, and to output a pass state or a fail state according to whether at least one of the difference values exceeds a reference value.)

1. A memory device comprising:

a memory cell array including a plurality of memory cells;

a peripheral circuit performing a program operation that increases threshold voltages of the plurality of memory cells such that the threshold voltages of the plurality of memory cells are included in any one of a plurality of program states separated according to voltage magnitudes of the program states;

a cycle count storage device that stores a first pass cycle count and a second pass cycle count for the plurality of program states, respectively, the program states being determined while the program operation is performed; and

a program verifier to calculate difference values each of which is a difference value between a first pass cycle count and a second pass cycle count of a corresponding one of the program states when the program operation is completed, and to output a result of the program operation indicating a pass state or a fail state according to whether at least one of the difference values exceeds a reference value.

2. The memory device of claim 1, wherein the program operation comprises a plurality of program cycles, and

the first pass cycle count indicates a program cycle in which a memory cell that has passed a verify operation respectively corresponding to the plurality of program states is initially sensed.

3. The memory device of claim 2, wherein the second pass cycle count indicates a programming cycle in which verification of each of the plurality of program states is completed.

4. The memory device of claim 1, wherein the program operation comprises a plurality of program cycles, and

the first pass cycle count indicates a program cycle when memory cells that have passed verify operations respectively corresponding to the plurality of program states exceed a first reference number.

5. The memory device according to claim 4, wherein the second pass cycle count indicates a program cycle when memory cells that have passed verify operations respectively corresponding to the plurality of program states in verification for each target program state exceed a second reference number.

6. The memory device according to claim 1, wherein the program verifier outputs a result of the program operation in a failed state when at least one of the difference values exceeds the reference value.

7. The memory device of claim 1, further comprising:

a status register storing a result of performing the program operation.

8. A method of operating a memory device, the method comprising:

performing a program operation that increases threshold voltages of a plurality of memory cells such that the threshold voltages of the plurality of memory cells in a memory cell array are included in any one of a plurality of program states separated according to voltage magnitudes of the program states;

storing a first pass cycle count and a second pass cycle count for the plurality of program states, respectively, the program states being determined while the program operation is being performed;

calculating difference values when the programming operation is completed, each of the difference values being a difference between the first and second pass cycle counts of a respective one of the program states; and is

Determining whether the program operation passes or fails according to whether at least one of the difference values exceeds a reference value.

9. The method of claim 8, wherein determining whether the programming operation passed or failed comprises:

generating a result of the program operation indicating that the program operation failed in response to at least one of the difference values exceeding the reference value; and is

Storing the result of performing the programming operation in a status register.

10. The method of claim 8, wherein the programming operation includes a plurality of programming cycles, and

the first pass cycle count indicates a program cycle in which a memory cell that has passed a verify operation respectively corresponding to the plurality of program states is initially sensed.

11. The method of claim 10, wherein the second pass cycle count indicates a programming cycle in which verification of each of the plurality of program states is completed.

12. The method of claim 8, wherein the programming operation includes a plurality of programming cycles, and

the first pass cycle count indicates a program cycle when memory cells, which respectively correspond to the plurality of program states, have passed a verify operation, exceed a first reference number.

13. The method of claim 12, wherein the second pass cycle count indicates a program cycle when memory cells that have passed verify operations respectively corresponding to the plurality of program states in the verifying for each target program state exceed a second reference number.

14. A memory device comprising:

a plurality of memory cells;

a peripheral circuit performing a program operation that increases threshold voltages of the plurality of memory cells such that the threshold voltages of the plurality of memory cells are included in any one of a plurality of program states separated according to voltage magnitudes of the program states; and

control logic to determine whether the program operation passes according to whether a difference between a program cycle in which it is initially sensed that the memory cells respectively corresponding to the verification operations of the plurality of program states pass and a program cycle in which the verification of each of the plurality of program states is completed exceeds a reference value while the program operation is performed.

15. The memory device of claim 14, further comprising:

a status register to store a result of the programming operation.

Technical Field

The present disclosure relates to an electronic device, and more particularly, to a memory device and an operating method thereof.

Background

The storage device stores data under the control of the host device. The memory device may include a memory device to store data and a memory controller to control the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

Volatile memory devices store data only when power is received from a power source. When the power is turned off, data stored in the volatile memory device may be lost. Examples of volatile memory devices include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

In a nonvolatile memory device, stored data is not lost even in a state where power is not supplied. Examples of non-volatile memory devices include Read Only Memory (ROM), programmable memory (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, and the like.

Disclosure of Invention

Embodiments of the present disclosure provide a memory device capable of preventing a read failure and an operating method thereof.

A memory device according to an embodiment of the present disclosure may include: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation of increasing threshold voltages of a plurality of memory cells such that the threshold voltages of the plurality of memory cells are included in any one of a plurality of program states separated according to voltage magnitudes of the program states; a cycle count storage configured to store a first pass cycle count and a second pass cycle count for a plurality of program states, respectively, the program states being determined while a program operation is performed; and a program verifier configured to calculate difference values each of which is a difference value between the first pass cycle count and the second pass cycle count of a corresponding one of the program states when the program operation is completed, and output a result of the program operation indicating a pass state or a fail state according to whether at least one of the difference values exceeds a reference value.

A method of operating a memory device according to another embodiment of the present disclosure may include: performing a program operation of increasing threshold voltages of the plurality of memory cells such that the threshold voltages of the plurality of memory cells in the memory cell array are included in any one of a plurality of program states separated according to voltage magnitudes of the program states; storing a first pass cycle count and a second pass cycle count for a plurality of program states, respectively, the program states being determined while performing a program operation; when the program operation is completed, difference values are calculated, each of the difference values being a difference value between the first pass cycle count and the second pass cycle count of a corresponding one of the program states, and whether the program operation passes or fails is determined according to whether at least one of the difference values exceeds a reference value.

A memory device according to an embodiment of the present disclosure may include: a plurality of memory cells; a peripheral circuit configured to perform a program operation of increasing threshold voltages of a plurality of memory cells such that the threshold voltages of the plurality of memory cells are included in any one of a plurality of program states separated according to voltage magnitudes of the program states; and control logic configured to determine whether the program operation passes according to whether a difference between a program cycle in which memory cells having passed verification operations respectively corresponding to the plurality of program states are initially sensed and a program cycle in which verification for each of the plurality of program states is completed exceeds a reference value.

A memory device according to an embodiment of the present disclosure may include: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program operation on a plurality of memory cells to indicate any one of a plurality of program states, the program operation including a plurality of program cycles having different program voltages; and a programming operation controller. The program operation controller is configured to determine a first pass cycle count and a second pass cycle count for each of a plurality of program states, calculate a difference between the corresponding first pass cycle count and second pass cycle count, and determine whether a program operation passes or fails based on the difference of the plurality of program states. The first pass loop count indicates a program loop of the pass verify operation among the program loops. The second pass loop count indicates a program loop among the program loops that completes verification of the target program state.

According to the present technology, a memory device capable of preventing a read failure and an operating method thereof are provided.

Drawings

FIG. 1 is a diagram illustrating a storage system according to an embodiment of the present disclosure;

FIG. 2 is a diagram illustrating an embodiment of the memory device shown in FIG. 1;

FIG. 3 is a diagram illustrating an embodiment of a structure of the representative memory block shown in FIG. 2;

FIG. 4 is a diagram illustrating a program operation and a verify operation running in a program loop, according to an embodiment of the present disclosure;

FIG. 5 is a diagram illustrating program states according to an embodiment of the present disclosure;

FIG. 6 is a diagram illustrating a pass loop count according to an embodiment of the present disclosure;

FIG. 7 is a diagram illustrating an embodiment of a program operation controller shown in FIG. 2;

FIG. 8 is a diagram showing a first pass cycle count and a second pass cycle count stored in a cycle count storage device such as that shown in FIG. 7;

FIG. 9 is a flow diagram illustrating an embodiment of a method of operating a memory device such as that shown in FIG. 1;

FIG. 10 is a diagram illustrating an embodiment of a memory controller, such as that shown in FIG. 1;

fig. 11 is a block diagram showing a memory card system to which a storage device is applied according to an embodiment of the present disclosure;

FIG. 12 is a block diagram illustrating a Solid State Drive (SSD) system employing storage devices in accordance with an embodiment of the present disclosure;

fig. 13 is a block diagram illustrating a user system applying a storage device according to an embodiment of the present disclosure.

Detailed Description

Descriptions of specific structures and functions are provided herein for purposes of describing embodiments of the present disclosure. However, the invention may be embodied in various forms and embodiments. Thus, the invention is not limited to or by any of the disclosed embodiments, nor is it limited to any of the specific details provided herein. Throughout the specification, references to "an embodiment" or "another embodiment" are not necessarily to only one embodiment, and different references to any similar language are not necessarily to the same embodiment.

Fig. 1 is a diagram illustrating a storage system according to an embodiment of the present disclosure.

Referring to fig. 1, the storage system may be implemented as a Personal Computer (PC), a data center, an enterprise data storage system, a data processing system including a Direct Attached Storage (DAS), a data processing system including a Storage Area Network (SAN), a data processing system including a Network Attached Storage (NAS), or the like.

The storage system may include the storage apparatus 1000 and the host 400.

The storage device 1000 may store data under the control of a host 400 such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

The storage device 1000 may be manufactured or configured as any of various types of storage devices according to a host interface that defines a communication protocol with the host 400. For example, the storage device 1000 may be configured as any one of SSD, a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a Universal Serial Bus (USB) storage device, a universal flash memory (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) card type storage device, a PCI express (PCI-e or PCIe) card type storage device, a Compact Flash (CF) card, a smart media card, and a memory stick.

The memory device 1000 may be manufactured as any of various types of packages. For example, the memory device 1000 may be manufactured as any one of a Package On Package (POP), a System In Package (SIP), a System On Chip (SOC), a multi-chip package (MCP), a Chip On Board (COB), a wafer level manufacturing package (WFP), and a wafer level package on package (WSP).

The memory device 1000 may include a memory device 100 and a memory controller 200.

The memory device 100 may operate in response to control of the memory controller 200. Specifically, the memory device 100 may receive a command and an address from the memory controller 200 and access a memory cell selected by the address among the memory cell array (not shown). The memory device 100 may perform the operation indicated by the command on the memory cell selected by the address.

The command may be, for example, a program command, a read command, or an erase command, and the operation indicated by the command may be, for example, a program operation (or a write operation), a read operation, or an erase operation.

For example, the memory device 100 may receive a program command, an address, and data, and program the data in a memory cell selected by the address.

For example, the memory device 100 may receive a read command and an address, and read data from an area selected by the address in the memory cell array.

For example, the memory device 100 may receive an erase command and an address, and erase data stored in an area selected by the address.

For example, the memory device 100 may be implemented as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4(LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory devices, Resistive Random Access Memory (RRAM), phase change memory (PRAM), Magnetoresistive Random Access Memory (MRAM), ferroelectric random access memory, or spin transfer torque random access memory (STT-RAM), among others.

In this specification, the present invention is described in the case where the memory device 100 is a NAND flash memory as an example.

The memory device 100 may store data under the control of the memory controller 200 or provide the stored data to the memory controller 200.

The memory device 100 may include a memory cell array (not shown) including memory cells storing data.

The memory cell array (not shown) may include a plurality of memory blocks (not shown). The memory block may be a unit in which an erase operation for erasing data is performed.

The memory block may include a plurality of pages (not shown). The page may be a unit of performing a program operation of storing data or a read operation of sensing the stored data.

The memory device 100 may include a program operation controller 131.

The program operation controller 131 may control the memory device 100 to perform a program operation of storing data in the selected memory cells in response to a program command provided by the memory controller 200.

The program operation controller 131 may store the result of the program operation. Memory controller 200 may request the program operation results from memory device 100. Further, the memory controller 200 may determine whether the program operation is successfully performed based on the program operation result received from the memory device 100.

The program operation may include increasing a threshold voltage of the selected memory cell such that the threshold voltage of the selected memory cell is included in any one of a plurality of program states. The program state of the memory cell being programmed may be determined according to data to be stored in the corresponding memory cell. That is, the target program state may be determined according to data to be stored in the memory cell.

The program operation may be performed in units of pages. A page may be a plurality of memory cells connected to the same word line.

The number of program states may be determined according to the number of bits of data stored in the memory cell. For example, the memory cell may be configured as a Single Layer Cell (SLC) storing one bit of data, a multi-layer cell (MLC) storing two bits of data, a Triple Layer Cell (TLC) storing three bits of data, and a Quadruple Layer Cell (QLC) storing four bits of data.

In the SLC, the target program state may be the first program state or the second program state. In the MLC, the target program state may be any one of the first to fourth program states. In TLC, the target program state may be any one of the first to eighth program states. In the QLC, the target program state may be any one of the first to sixteenth program states.

The program operation may include a plurality of program loops. The program loop may include a program voltage applying operation and a verifying operation.

The program voltage applying operation may include applying a program voltage to a selected word line, which is a word line commonly connected to the selected memory cell.

The verifying operation may include determining whether a threshold voltage of the memory cell reaches a target threshold voltage corresponding to a target program state. In a verify operation, a verify voltage corresponding to a target program state may be applied to a selected word line. When the threshold voltage of the memory cell is greater than the verify voltage, it may be determined that the verify operation passes. When the threshold voltage of the memory cell is less than or equal to the verify voltage, it may be determined that the verify operation failed. When the verifying operation for a set number of memory cells among the memory cells having the same target program state passes, the verifying of the corresponding target program state may be completed.

When verification of all target program states is complete, the program operation may be completed. When the programming operation is complete, it may be determined that the programming operation passed.

When the program operation does not pass within the set reference time, it may be determined that the program operation fails. Alternatively, when the program operation is not passed even after the maximum allowable number of program loops indicated by the set maximum loop count are performed, it may be determined that the program operation failed.

According to an embodiment of the present disclosure, the program operation controller 131 may determine that the program operation fails even though the verification of all target program states is completed.

Specifically, while performing the program operation, the program operation controller 131 may store a first pass cycle count and a second pass cycle count corresponding to each of the plurality of program states.

When the program operation is completed, the program operation controller 131 may calculate a difference between the first pass cycle count and the second pass cycle count. Further, the program operation controller 131 may determine whether the program operation passes or fails according to whether any one of the difference values exceeds a set reference value.

The first pass cycle count may indicate that a program cycle of the memory cells that passed the verify operation respectively corresponding to each program state is first sensed.

The second pass loop count may indicate a programming loop in which verification of the target program state is completed.

The program operation controller 131 is described in detail below with reference to fig. 7.

The memory controller 200 may control the overall operation of the memory device 1000.

Memory controller 200 may run firmware when power is supplied to memory device 1000. When memory device 100 is a flash memory device, the firmware may include a host interface layer, a flash translation layer, and a flash interface layer.

The host interface layer may control operations between the host 400 and the memory controller 200.

The flash translation layer may translate logical addresses provided by the host 400 into physical addresses. To this end, the memory controller 200 may store mapping data indicating a relationship between logical addresses and physical addresses.

The flash interface layer may control communication between the memory controller 200 and the memory device 100.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, and an erase operation in response to a write request, a read request, and an erase request from the host 400, respectively.

During a programming operation, the memory controller 200 may provide a write command, a physical address, and data to the memory device 100.

During a read operation, memory controller 200 may provide a read command and a physical address to memory device 100.

During an erase operation, memory controller 200 may provide an erase command and a physical address to memory device 100.

Memory controller 200 may autonomously generate commands, addresses, and data without a request provided by host 400. The memory controller 200 may transmit autonomously generated commands, addresses and data to the memory device 100.

For example, memory controller 200 may generate commands, addresses, and data for performing background operations. In addition, the memory controller 200 may provide the command, address, and data to the memory device 100.

Background operations may be wear leveling, read reclamation, and/or garbage collection.

The memory controller 200 may control two or more memory devices 100. In this case, the memory controller 200 may control the memory device 100 according to the interleaving method to improve the operation performance.

The interleaving method may be a method of controlling to overlap operations on two or more memory devices 100.

The host 400 may communicate with the storage apparatus 1000 through an interface (not shown).

The interface may be implemented as a Serial Advanced Technology Attachment (SATA) interface, a SATA express interface, a serial small computer system interface (SAS) interface, a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, an Advanced Host Controller Interface (AHCI), or a multimedia card interface. However, the interface is not limited thereto.

The host 400 may communicate with the storage device 1000 to store data in the storage device 1000 or to obtain data stored in the storage device 1000.

In an embodiment, the host 400 may provide a write request to the storage device 1000 to request data to be stored in the storage device 1000. In addition, the host 400 may provide a write request, data, and a logical address that identifies the data to be written (stored) in the storage device 1000.

The storage device 1000 may store data provided by the host 400 in the memory device 100 in response to a write request provided by the host 400 and provide a response to the host 400 to complete the storage.

In an embodiment, the host 400 may provide a read request to the storage device 1000 to request that data stored in the storage device 1000 be sent to the host 400. In addition, the host 400 may provide a read request and a read address to the storage device 1000.

The memory device 1000 may read data corresponding to a read address provided by the host 400 from the memory device 100 in response to a read request from the host 400 and provide the read data to the host 400 in response to the read request.

FIG. 2 is a diagram used to describe an embodiment of the memory device 100 shown in FIG. 1.

Referring to fig. 1 and 2, the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130.

Memory cell array 110 may include a plurality of memory blocks MB1 through MBk (where k is a positive integer).

Each of the memory blocks MB1 through MBk may be connected to a local line LL and bit lines BL1 through BLn (where n is a positive integer).

The local line LL may be connected to each of the memory blocks MB1 through MBk.

Although not shown, the local line LL may include a first selection line, a second selection line, and a plurality of word lines disposed between the first selection line and the second selection line.

Although not shown, the local line LL may further include a dummy line disposed between the first selection line and the word line, a dummy line disposed between the second selection line and the word line, and a pipe line.

The bit lines BL1 to BLn may be commonly connected to the memory blocks MB1 to MBk.

The memory blocks MB1 through MBk may be implemented as two-dimensional or three-dimensional structures.

In the memory blocks MB1 to MBk of the two-dimensional structure, memory cells may be arranged in a direction parallel to the substrate.

In the memory blocks MB1 through MBk of the three-dimensional structure, memory cells may be stacked on a substrate in a vertical direction.

The peripheral circuits 120 may include a voltage generator 121, a row decoder 122, a group of page buffers 123, a column decoder 124, input/output (I/O) circuits 125, and sensing circuits 126.

The voltage generator 121 may generate various operation voltages Vop for a program operation, a read operation, and an erase operation in response to the operation signal OP _ CMD. In addition, the voltage generator 121 may selectively discharge the local line LL in response to the operation signal OP _ CMD. For example, the voltage generator 121 may generate a program voltage, a verify voltage, a pass voltage, a turn-on voltage, a read voltage, an erase voltage, a source line voltage, and the like under the control of the control logic 130.

In an embodiment, the voltage generator 121 may adjust an external power supply voltage to generate an internal power supply voltage. The internal power supply voltage generated by the voltage generator 121 is used as an operation voltage of the memory device 100.

In an embodiment, the voltage generator 121 may generate the plurality of operating voltages using an external power supply voltage or an internal power supply voltage. For example, the voltage generator 121 may include a plurality of pumping capacitors that receive the internal power supply voltage, and may generate the plurality of voltages by selectively enabling the plurality of pumping capacitors in response to control of the control logic 130. A plurality of the generated voltages may be supplied to the memory cell array 110 through the row decoder 122.

The row decoder 122 may transmit the operation voltage Vop to the local line LL in response to the row address RADD. The operating voltage Vop may be transferred to the selected memory block through the local line LL.

During a program operation, the row decoder 122 may apply a program voltage to a selected word line and apply a program pass voltage having a level less than that of the program voltage to unselected word lines. During a program verify operation, the row decoder 122 may apply a verify voltage to a selected word line and a verify pass voltage greater than the verify voltage to unselected word lines.

During a read operation, the row decoder 122 may apply a read voltage to a selected word line and apply a read pass voltage greater than the read voltage to unselected word lines.

During an erase operation, the row decoder 122 may select one of the memory blocks according to the decoded address. Further, the row decoder 122 may apply a ground voltage to word lines connected to the selected memory block.

The page buffer group 123 may include first to nth page buffers PB1 to PBn, and the first to nth page buffers PB1 to PBn may be connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn may operate in response to control of the control logic 130.

Specifically, the first to nth page buffers PB1 to PBn may operate in response to the page buffer control signals PBSIGNALS. For example, during a read operation or a verify operation, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense voltages or currents of the bit lines BL1 to BLn.

During a program operation, when a program voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn may transfer DATA received through the column decoder 124 and the input/output circuit 125 to a selected memory cell through the first to nth bit lines BL1 to BLn. The memory cells of the selected page are programmed according to the transferred DATA. A memory cell connected to a bit line to which a program enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cell connected to the bit line to which the program-inhibit voltage (e.g., power supply voltage) is applied may be maintained.

During the verify operation, the first to nth page buffers PB1 to PBn may sense data stored in memory cells selected from the selected memory cells through the first to nth bit lines BL1 to BLn.

During a read operation, the first to nth page buffers PB1 to PBn may sense DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read DATA to the input/output circuit 125 under the control of the column decoder 124.

During an erase operation, the first through nth page buffers PB1 through PBn may float the first through nth bit lines BL1 through BLn.

The column decoder 124 may transfer data between the input/output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may exchange data with the page buffers PB1 to PBn through the data lines DL, or may exchange data with the input/output circuit 125 through the column lines CL.

The input/output circuit 125 may transmit a command CMD and an address ADD received from the memory controller 200 to the control logic 130, or may exchange DATA with the column decoder 124.

During a read operation or a verify operation, the sense circuit 126 may generate a reference current in response to the enable BIT signal VRY _ BIT < # >. Further, the sensing circuit 126 may compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by a reference current to output a PASS signal PASS or a FAIL signal FAIL.

The control logic 130 may output an operation signal OP _ CMD, a row address RADD, a page buffer control signal PBSIGNALS, and an enable BIT VRY _ BIT < # > in response to the command CMD and the address ADD to control the peripheral circuit 120.

Control logic 130 may include a program operation controller 131.

Even if the verification of all target program states is completed, the program operation controller 131 may determine that the program operation fails.

Specifically, while performing the program operation, the program operation controller 131 may store a first pass cycle count and a second pass cycle count corresponding to each of the plurality of program states.

When the program operation is completed, the program operation controller 131 may calculate the difference between the first and second pass cycle counts, respectively. Further, the program operation controller 131 may determine whether the program operation passes or fails according to whether any one of the difference values exceeds a set reference value.

The first pass cycle count may indicate that a program cycle of the memory cells that passed the verify operation respectively corresponding to each program state is first sensed.

The second pass loop count may indicate a programming loop in which verification of the target program state is completed.

FIG. 3 is a diagram illustrating an embodiment of a structure of a representative memory block MBi of the plurality of memory blocks shown in FIG. 2.

Referring to fig. 2 and 3, the memory block MBi shown in fig. 3 may be any one of the memory blocks MB1 through MBk of fig. 2.

The memory block MBi may include a first select line, a second select line, a plurality of word lines WL1 to WL16, a source line SL, a plurality of bit lines BL1 to BLn, and a plurality of strings ST.

The first selection line may be, for example, a source selection line SSL. Hereinafter, it is assumed that the first selection line is the source selection line SSL.

The second selection line may be, for example, a drain selection line DSL. Hereinafter, it is assumed that the second selection line is the drain selection line DSL.

A plurality of word lines WL1 to WL16 may be arranged in parallel between the source select line SSL and the drain select line DSL.

The number of word lines WL1 to WL16 shown in fig. 3 is an example, and the number of word lines is not limited to 16. Hereinafter, as an example, it is assumed that the number of the plurality of word lines is 16.

The source lines SL may be commonly connected to the plurality of strings ST.

A plurality of bit lines BL1 through BLn may be respectively connected to the strings ST.

A plurality of strings ST may be connected to bit lines BL1 to BLn and source lines SL.

Since the strings ST may be configured to be identical to each other, the string ST connected to the first bit line BL1 is specifically described as an example.

The string ST may include a plurality of memory cells MC1 through MC16, at least one first selection transistor, and at least one second selection transistor.

The plurality of memory cells MC1 through MC16 may be connected in series between the source select transistor SST and the drain select transistor DST.

The gates of memory cells MC 1-MC 16 may be connected to a plurality of word lines WL 1-WL 16, respectively. Therefore, the number of memory cells MC1 to MC16 included in one string ST may be the same as the number of word lines WL1 to WL 16. Hereinafter, as an example, it is assumed that there are 16 memory cells as many as the number of word lines WL1 to WL 16.

Any one of the plurality of memory cells MC1 through MC16 may be configured as any one of SLC, MLC, TLC, and QLC.

A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PG. Accordingly, the memory block MBi may include physical pages PG corresponding to the number of word lines WL1 to WL 16. Hereinafter, it is assumed that the memory cell (e.g., MC3) included in the physical page PG is a selected memory cell.

The first selection transistor may be, for example, a source selection transistor SST. Hereinafter, it is assumed that the first selection transistor is the source selection transistor SST.

A first electrode of the source selection transistor SST may be connected to a source line SL. The second electrode of the source selection transistor SST may be connected to a first memory cell MC1 among the plurality of memory cells MC1 through MC 16. A gate electrode of the source selection transistor SST may be connected to a source selection line SSL.

The second selection transistor may for example be a drain selection transistor DST. Hereinafter, it is assumed that the second selection transistor is a drain selection transistor DST.

The first electrode of the drain select transistor DST may be connected to a sixteenth memory cell MC16 among the plurality of memory cells MC1 through MC 16. A second electrode of the drain select transistor DST may be connected to a first bit line BL 1. A gate electrode of the drain select transistor DST may be connected to the drain select line DSL.

Fig. 4 is a diagram illustrating a program operation and a verify operation that run in a program loop according to an embodiment of the present disclosure.

Referring to fig. 4, a program operation may include a plurality of program loops.

The value of each program loop may be its program loop count. For example, the value of the first program loop may be 1, the value of the second program loop may be 2, and the value of the third program loop may be 3.

Each program loop may include a program voltage applying operation and a verifying operation.

The program voltage applying operation may include applying a program voltage Vpgm to a selected word line.

For example, when the first program state is an erase state, the first program voltage applying operation in the first program loop may include applying the first program voltage Vpgm1 to memory cells programmed with the second program state as a target program state. For example, the second program voltage applying operation in the second program loop may include applying the second program voltage Vpgm2 to memory cells programmed with the third program state as a target program state. For example, the third program voltage applying operation in the third program loop may include applying the third program voltage Vpgm3 to memory cells programmed with the fourth program state as a target program state.

The verify operation may include determining whether a threshold voltage Vth of the memory cell reaches a target threshold voltage. In the verify operation, a verify voltage Vfy corresponding to a target program state may be applied to a selected word line.

For example, when the first program state is the erase state, the first verifying operation in each of the first to third program loops may be an operation of determining whether the threshold voltage Vth of the memory cell reaches a target threshold voltage corresponding to the second program state as a target program state. In addition, in the first verify operation, a first verify voltage Vfy1 corresponding to the second program state may be applied. The second verifying operation in each of the first to third program loops may be an operation of determining whether the threshold voltage Vth of the memory cell reaches a target threshold voltage corresponding to the third program state as a target program state. In addition, in the second verify operation, a second verify voltage Vfy2 corresponding to the third program state may be applied. However, the present disclosure is not limited thereto.

When the threshold voltage Vth of the memory cell is greater than the verify voltage Vfy, the verify operation passes. When the threshold voltage Vth of the memory cell is less than or equal to the verify voltage Vfy, the verify operation fails.

When the verifying operation for a set number of memory cells among the memory cells having the same target program state passes, the verifying of the corresponding target program state may be completed.

When verification of all target program states is complete, the program operation may be completed. When the programming operation is complete, it may be determined that the programming operation passed.

When the program operation does not pass within the set reference time, it may be determined that the program operation fails. Alternatively, when the program operation is not passed even after the program loop is executed the maximum number of times indicated by the set maximum loop count Max, it may be determined that the program operation failed.

The program voltage Vpgm may be provided according to an Incremental Step Pulse Programming (ISPP) method. The program voltage Vpgm may be increased by the set step voltage Δ V each time the program loop is repeated. That is, the program voltage Vpgm may be sequentially increased from the first program voltage Vpgm1 to the mth program voltage VpgmM.

After the program voltage Vpgm is applied, at least one verify voltage Vfy in one program loop may be applied. Specifically, in a program loop, after the program voltage Vpgm is applied, at least one verify voltage (e.g., Vfy1) among a plurality of verify voltages Vfy1 through Vfy7 may be applied.

The application of the program voltages Vpgm1 to VpgmM and the verify voltages Vfy1 to Vfy7 may be repeated until the maximum loop count Max is reached.

Fig. 5 is a diagram illustrating a program state according to an embodiment of the present disclosure.

Fig. 5 is described in the case of TLC storing 3-bit data.

Referring to fig. 5, the target program state may be any one of a plurality of program states, i.e., P1 through P8. The first programmed state P1 may be, for example, the erased state.

The memory cells may have threshold voltages belonging to a threshold voltage distribution corresponding to any one of the program states P1 through P8 through a program operation.

Before performing a programming operation, the memory cell may be in the first program state P1. In an embodiment, the first program state P1 may be the state of the memory cell after performing an erase operation.

Since the program voltage Vpgm is increased by the set step voltage Δ V each time the successive program loops are repeated, the threshold voltage Vth of the memory cell may be changed according to the program voltage Vpgm. The threshold voltage Vth of the memory cell may increase as the program voltage applying operation proceeds. In addition, the threshold voltage distribution corresponding to the state of the memory cell after performing the erase operation may be changed as the program voltage applying operation proceeds. Specifically, the threshold voltage distribution corresponding to the state of the memory cell after the erase operation is performed may change (or move) in the direction in which the threshold voltage Vth increases.

As the program voltage applying operation proceeds, the verifying operation may be sequentially performed from the second program state P2 to the eighth program state P8.

The verify operation corresponding to the second program state P2 may include: it is determined whether the threshold voltage of the memory cell reaches a target threshold voltage corresponding to the second program state P2 as a target program state. The verify voltage corresponding to the second program state P2 may be the first verify voltage Vfy 1. That is, the target threshold voltage corresponding to the second program state P2 may be the first verify voltage Vfy 1. During a verify operation using the first verify voltage Vfy1, memory cells having a threshold voltage Vth greater than the first verify voltage Vfy1 may be in an off state (or may be off cells). During a verify operation using the first verify voltage Vfy1, memory cells having a threshold voltage Vth less than or equal to the first verify voltage Vfy1 may be in a conductive state (or may be conductive cells).

The verifying operations corresponding to the third through eighth program states P3 through P8 may include: it is determined whether the threshold voltage of the memory cell reaches a target threshold voltage corresponding to a target program state (e.g., the third program state P3 through the eighth program state P8). In this case, the verify voltages corresponding to the third through eighth program states P3 through P8 may be the second through seventh verify voltages Vfy2 through Vfy 7.

Fig. 6 is a diagram illustrating a pass cycle count according to an embodiment of the present disclosure.

Referring to fig. 6, a threshold voltage distribution corresponding to any one program state (e.g., P3) among the second through eighth program states P2 through P8 will be described.

In fig. 6, as program loops are repeated, each of which includes a program voltage applying operation of applying a program voltage (e.g., Vpgm2) for a program state (e.g., P3) and a verifying operation of applying a verifying voltage (e.g., Vfy2) for a program state (e.g., P3), the threshold voltage distributions VTHD of the memory cells may be changed in order from the first threshold voltage distribution VTHD _1 to the k-th threshold voltage distribution VTHD _ k.

In an embodiment, the first pass cycle count may be a value in which a program cycle of a memory cell that passed a verify operation corresponding to each program state is initially sensed.

Referring to fig. 4 to 6, for example, according to a second program voltage applying operation in a second program loop, a second program voltage Vpgm2 may be applied to a selected memory cell.

The threshold voltage distribution VTHD of the memory cells to be programmed to the third program state P3 may be changed from a target voltage distribution corresponding to a state (e.g., P1) of the memory cells after performing the erase operation to the first threshold voltage distribution VTHD _ 1.

In a second verifying operation in a second program loop, a target threshold voltage Vth _ target corresponding to the third program state P3, i.e., a second verifying voltage Vfy2 for verifying the third program state P3, may be applied to the selected memory cells. At least one memory cell having a threshold voltage Vth greater than the second verify voltage Vfy2 among the threshold voltages Vth belonging to the first threshold voltage distribution VTHD _1 may be initially sensed. That is, the second verify operation in the second program loop may initially pass. In this case, the first pass loop count may be 2, which is the value of the second program loop.

In an embodiment, the first pass cycle count may be a value of a program cycle in which a verify operation for a first set reference number of memory cells among the memory cells having the same target program state passes.

For example, during a second verifying operation in a second program loop, a number of memory cells, which are less than the first reference number, to be programmed to a third program state pass the second verifying operation. During the second verifying operation in the third program loop, when the first reference number of memory cells among the memory cells to be programmed to the third program state pass the second verifying operation, the first pass loop count may be 3, which is a value of the third program loop.

In an embodiment, the second pass loop count may be a value of a program loop for which verification of the target program state is complete. When the verifying operation for the second reference number of memory cells among the memory cells having the same target program state passes, the verifying of the corresponding target program state may be completed.

Referring to fig. 4 to 6, for example, according to a third program voltage applying operation in a third program loop, a third program voltage Vpgm3 may be applied to a selected memory cell.

The threshold voltage distribution VTHD of the memory cells to be programmed to the third program state P3 may be changed from a target voltage distribution corresponding to a state (e.g., P1) of the memory cells after performing the erase operation to a kth threshold voltage distribution VTHD _ k.

In a second verify operation included in the third program loop, a second verify voltage Vfy2 may be applied to the selected memory cell. Among the threshold voltages Vth belonging to the kth threshold voltage distribution VTHD — k, a second reference number of memory cells having a threshold voltage Vth greater than the second verify voltage Vfy2 may be sensed. That is, the second verify operation in the third program loop may pass last. Therefore, since the verification for the third program state is completed, the second pass loop count may be 3, which is the value of the third program loop.

In an embodiment, the first reference number may be smaller than the second reference number.

Fig. 7 is a diagram illustrating an embodiment of the program operation controller 131 shown in fig. 2.

Referring to fig. 7, the program operation controller 131 may include a program verifier 131_1, a loop count storage 131_2, and a status register 131_ 3.

Program verifier 131_1 may receive PASS signal PASS or FAIL signal FAIL.

The program verifier 131_1 may detect the first through-cycle count PLC1 and the second through-cycle count PLC2 corresponding to one program state in response to the PASS signal PASS or the FAIL signal FAIL. In addition, the program verifier 131_1 may detect the first through-loop count PLC1 and the second through-loop count PLC2 corresponding to a plurality of program states.

Program verifier 131_1 may provide first and second pass loop count PLCs 1 and 2 to loop count storage 131_ 2.

The loop count storage 131_2 may store a first pass loop count PLC1 and a second pass loop count PLC2 corresponding to each of a plurality of program states determined while performing a program operation.

When the programming operation is completed, the program verifier 131_1 may receive the first through-loop count PLC1 and the second through-loop count PLC2 stored in the loop count storage 131_ 2.

When the program operation is completed, the program verifier 131_1 may calculate a difference between the first through-cycle count PLC1 and the second through-cycle count PLC2 corresponding to one program state. That is, the program verifier 131_1 may calculate a difference between a corresponding pair of the PLC1 and the PLC2 with respect to a plurality of program states.

The program verifier 131_1 may output a result of performing a program operation according to whether there is a difference value exceeding a set reference value among the difference values. The result of performing a programming operation may indicate either a pass state PS or a fail state FS.

The reference value may be stored in the program verifier 131_1, but the present invention is not limited thereto.

In an embodiment, the program verifier 131_1 may output a result of performing a program operation indicating a fail state FS in response to there being a difference value exceeding a reference value. That is, when there is at least one difference value exceeding the reference value, the program verifier 131_1 may output a result of performing a program operation indicating a fail state FS.

In an embodiment, program verifier 131_1 may output a result indicating that a program operation is performed through state PS in response to all differences being less than or equal to a reference value.

The program verifier 131_1 may provide the result indicating the execution of the program operation by the state PS or the fail state FS to the state register 131_ 3.

The status register 131_3 may store the result of performing a programming operation, which may indicate a pass status PS or a fail status FS.

Fig. 8 is a diagram illustrating the first pass cycle count and the second pass cycle count stored in the cycle count storage device shown in fig. 7.

In fig. 8, PV1 through PV7 may correspond to the second through eighth program states P2 through P8, respectively, described with reference to fig. 5.

In describing fig. 8, the selected memory cells are tri-level cells as described above with reference to fig. 5, and thus the present embodiment is described in the case where the number of the plurality of program states is eight.

Referring to fig. 7 and 8, the loop count storage 131_2 may store a first pass loop count PLC1 and a second pass loop count PLC2 for each of a plurality of program states P1 through P8. In addition, the first and second pass loop count PLCs 1, 2 have values for programming loops.

For example, the first pass-cycle count PLC1 of the second program state P2 or PV1 may be x1 and the second pass-cycle count PLC2 of the second program state P2 or PV1 may be y 1. For example, the first pass-cycle count PLC1 of the third program state P3 or PV2 may be x2 and the second pass-cycle count PLC2 of the third program state P3 or PV2 may be y 2. For example, the first pass cycle count PLC1 of the fourth program state P4 or PV3 may be x3 and the second pass cycle count PLC2 of the fourth program state P4 or PV3 may be y 3. For example, the first pass-cycle count PLC1 of the fifth program state P5 or PV4 may be x4 and the second pass-cycle count PLC2 of the fifth program state P5 or PV4 may be y 4. For example, the first pass cycle count PLC1 of the sixth program state P6 or PV5 may be x5 and the second pass cycle count PLC2 of the sixth program state P6 or PV5 may be y 5. For example, the first pass cycle count PLC1 of the seventh programmed state P7 or PV6 may be x6 and the second pass cycle count PLC2 of the seventh programmed state P7 or PV6 may be y 6. For example, the first pass cycle count PLC1 of the eighth program state P8 or PV7 may be x7 and the second pass cycle count PLC2 of the eighth program state P8 or PV7 may be y 7.

When the program operation is completed, the program verifier 131_1 may calculate a difference value (| PLC1-PLC2 |) between the corresponding first through-cycle count PLC1 and second through-cycle count PLC2 from the cycle count storage device 131_ 2. In an embodiment, the second pass count PLC2 may be greater than or equal to the first pass count PLC 1. Hereinafter, it is assumed that the second pass cycle count PLC2 is greater than or equal to the first pass cycle count PLC 1.

For example, the program verifier 131_1 may calculate a difference (y1-x1) between the first pass cycle count PLC1 and the second pass cycle count PLC2 for the second program state P2 or PV 1. For example, the program verifier 131_1 may calculate a difference (y2-x2) between the first pass cycle count PLC1 and the second pass cycle count PLC2 for the third program state P3 or PV 2. For example, the program verifier 131_1 may calculate a difference (y3-x3) between the first pass cycle count PLC1 and the second pass cycle count PLC2 for the fourth program state P4 or PV 3. For example, the program verifier 131_1 may calculate a difference value (y4-x4) between the first pass cycle count PLC1 and the second pass cycle count PLC2 for the fifth program state P5 or PV 4. For example, the program verifier 131_1 may calculate a difference value (y5-x5) between the first through-cycle count PLC1 and the second through-cycle count PLC2 for the sixth program state P6 or PV 5. For example, the program verifier 131_1 may calculate a difference value (y6-x6) between the first through-cycle count PLC1 and the second through-cycle count PLC2 for the seventh program state P7 or PV 6. For example, the program verifier 131_1 may calculate a difference value (y7-x7) between the first through-cycle count PLC1 and the second through-cycle count PLC2 for the eighth program state P8 or PV 7.

The program verifier 131_1 may store a result of performing a program operation in the state register 131_3 according to whether there is a difference value exceeding a set reference value among the difference values (y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x 7).

For example, the program verifier 131_1 may store a result of performing a program operation indicating the fail state FS in the state register 131_3 according to at least one difference value among the difference values (y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) exceeding a set reference value.

For example, the program verifier 131_1 may store a result indicating the execution of the program operation by the state PS in the state register 131_3 according to all the difference values (y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) being less than or equal to the reference value.

FIG. 9 is a flow chart illustrating an embodiment of a method of operating the memory device 100 shown in FIG. 1.

Referring to fig. 9, while the program operation is performed, as shown in fig. 8, the memory device 100 stores the first and second pass loop count PLCs 1 and 2 corresponding to each of the plurality of program states (S110).

When the program operation is completed, as shown in FIG. 8, the memory device 100 calculates the difference values (y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) between the first through-cycle count PLC1 and the second through-cycle count PLC2 (S120).

The memory device 100 determines whether at least one of the differences among the differences (y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) exceeds a set reference value (S130).

When at least one of the difference values exceeds the reference value (S130, yes), the memory device 100 stores a result of performing the program operation indicating the fail state FS (S140).

When no difference value exceeds the reference value, i.e., each of the difference values (y1-x1), (y2-x2), (y3-x3), (y4-x4), (y5-x5), (y6-x6), and (y7-x7) is less than or equal to the reference value (S130, no), the memory device 100 stores a result indicating that the program operation is performed by the state PS (S150).

FIG. 10 is a diagram depicting an embodiment of the memory controller 200 shown in FIG. 1.

Referring to fig. 1 and 10, the memory controller 200 may include a processor 210, a Random Access Memory (RAM)220, an error correction circuit (i.e., ECC circuit) 230, a Read Only Memory (ROM)260, a host interface 270, and a flash memory interface 280.

The processor 210 may control the overall operation of the memory controller 200. The RAM 220 may be used as a buffer memory, a cache memory, and an operation memory of the memory controller 200. In addition to the RAM 220, a Static Random Access Memory (SRAM) may be used as a buffer memory.

The ROM 260 may store various information for the memory controller 200 to operate via firmware.

The memory controller 200 may communicate with external devices (e.g., the host 400, application processors, etc.) through the host interface 270.

The memory controller 200 may communicate with the memory device 100 through a flash interface 280. The memory controller 200 may transmit a command CMD, an address ADDR, and a control signal CTRL to the memory device 100 through the flash interface 280 and receive DATA.

For example, flash interface 280 may include a NAND interface.

Fig. 11 is a block diagram illustrating a memory card system 2000 to which a storage device is applied according to an embodiment of the present disclosure.

Referring to fig. 1 and 11, a memory card system 2000 includes a memory device 2100, a memory controller 2200, and a connector 2300.

For example, memory device 2100 may be configured as any of a variety of non-volatile memory elements such as: electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), and spin torque magnetic RAM (STT-MRAM).

The memory controller 2200 is connected to the memory device 2100. The memory controller 2200 is configured to access the memory device 2100. For example, the memory controller 2200 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 2100. The memory controller 2200 is configured to provide an interface between the memory device 2100 and the host 400. The memory controller 2200 is configured to drive firmware for controlling the memory device 2100. The memory controller 2200 may be implemented the same as the memory controller 200 described with reference to fig. 1.

For example, the memory controller 2200 may include components such as a Random Access Memory (RAM), a processor, a host interface, a memory interface, and error correction circuitry.

The memory controller 2200 may communicate with an external device through the connector 2300. The memory controller 2200 may communicate with an external device (e.g., the host 400) according to a specific communication standard. For example, the memory controller 2200 is configured to communicate with an external device through at least one of various communication standards such as: universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-e or PCIe), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the various communication standards described above.

The memory device 2100 and the memory controller 2200 may be integrated into one semiconductor device to configure a memory card such as the following: PC card (personal computer memory card international association (PCMCIA)), compact flash Card (CF), smart media card (e.g., SM or SMC), memory stick, multimedia card (e.g., MMC, RS-MMC, micro MMC, or eMMC), Secure Digital (SD) card (e.g., SD, mini SD, micro SD, or SDHC), and/or universal flash memory (UFS).

Fig. 12 is a block diagram illustrating a Solid State Drive (SSD) system 3000 to which a storage device is applied according to an embodiment of the present disclosure.

Referring to fig. 12, the SSD system includes a host 400 and an SSD 3000.

SSD 3000 exchanges signals SIG with host 400 through signal connector 3001 and receives power PWR through power connector 3002. The SSD 3000 includes an SSD controller 3200, a plurality of flash memories 3100_1, 3100_2, and 3100_ n, an auxiliary power supply device 3300, and a buffer memory 3400.

According to an embodiment of the present disclosure, SSD controller 3200 may perform the functions of memory controller 200 described with reference to fig. 1.

The SSD controller 3200 may control the plurality of flash memories 3100_1, 3100_2, and 3100_ n in response to a signal SIG received from the host 400. For example, signal SIG may include a signal based on an interface between host 400 and SSD 3000. For example, the signal SIG may be defined by at least one of the interfaces such as: universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-e or PCIe), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and NVMe.

The auxiliary power supply device 3300 is connected to the host 400 through the power supply connector 3002. The auxiliary power supply device 3300 may receive power PWR from the host 400 and may charge the power. When the power supply from the host 400 is not smooth, the auxiliary power supply device 3300 may supply power to the SSD 3000. For example, the auxiliary power supply device 3300 may be provided in the SSD 3000 or outside. For example, the auxiliary power supply device 3300 may be provided on the main board and may supply auxiliary power to the SSD 3000.

The buffer memory 3400 may temporarily store data. For example, the buffer memory 3400 may temporarily store data received from the host 400 or data received from the plurality of flash memories 3100_1, 3100_2, and 3100_ n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3100_1, 3100_2, and 3100_ n. The buffer memory 3400 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 13 is a block diagram illustrating a user system 4000 to which a storage device is applied according to an embodiment of the present disclosure.

The user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components, an Operating System (OS), user programs, and the like included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphic engine, etc. that controls components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR2 SDRAM, DDR3SDRAM, LPDDR SDRAM LPDDR2 SDRAM, and LPDDR 3SDRAM, or non-volatile random access memory such as FRAM, ReRAM, MRAM, and PRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a Package On Package (POP) and provided as one semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communication such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), long term evolution, Wimax, WLAN, UWB, bluetooth, and Wi-Fi. For example, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transmit data stored in the memory module 4400 to the application processor 4100. For example, the memory module 4400 may be implemented as a nonvolatile semiconductor memory element such as: phase change ram (pram), magnetic ram (mram), resistive ram (rram), NAND flash memory, NOR flash memory, and three-dimensional NAND flash memory. For example, the memory module 4400 may be provided as a removable storage device (removable drive), such as a memory card and an external drive of the user system 4000.

For example, the memory module 4400 may operate in the same manner as the memory device 1000 described with reference to fig. 1. The memory module 4400 may include a plurality of nonvolatile memory devices, and each of the plurality of nonvolatile memory devices may operate in the same manner as the memory device 100 described with reference to fig. 1.

The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, user interface 4500 may include user input interfaces such as: a keyboard, a keypad, buttons, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and a piezoelectric element. User interface 4500 may include user output interfaces such as the following: liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) display devices, active matrix OLED (amoled) display devices, LEDs, speakers, and monitors.

While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes and/or modifications in form and detail may be made to any disclosed embodiment without departing from the spirit and scope of the invention.

For example, not all steps need necessarily be performed in the order recited, and in some cases, one or more steps or portions thereof may be omitted. Also, the specific terms used herein are intended to explain the embodiments of the disclosure rather than to limit the invention. Accordingly, the present invention is intended to embrace all such alterations and modifications that fall within the scope of the appended claims.