阅读说明：本技术 超导集成电路的布线优化方法和装置、存储介质和终端 (Method and apparatus for optimizing wiring of superconducting integrated circuit, storage medium, and terminal ) 是由 杨树澄 任洁 高小平 王镇 于 2021-09-17 设计创作，主要内容包括：本发明公开了一种超导集成电路的布线优化方法和装置、存储介质和终端,其中方法包括：基于待优化电路的版图信息和电路网表获取逻辑门坐标互连线,对所有坐标互连线进行布线运算,将布线成功的运算结果存储到预设数据库中,并将布线失败对应的坐标互连线添加到失败队列中；基于失败队列获取最优布线结果；再分别基于减少路径延时方式和/或增加路径延时方式对最优布线结果中的时钟互连线和信号互连线进行优化,得到待优化电路的优化布线结果。本发明实现了超导集成电路布局后的自动布线问题,降低设计成本,减少手动布线所带来的设计时间开销。(The invention discloses a wiring optimization method and device of a superconducting integrated circuit, a storage medium and a terminal, wherein the method comprises the following steps: acquiring a logic gate coordinate interconnection line based on layout information and a circuit netlist of a circuit to be optimized, performing wiring operation on all coordinate interconnection lines, storing an operation result of successful wiring into a preset database, and adding a coordinate interconnection line corresponding to wiring failure into a failure queue; obtaining an optimal wiring result based on the failure queue; and optimizing the clock interconnection line and the signal interconnection line in the optimal wiring result respectively based on the path delay reducing mode and/or the path delay increasing mode to obtain the optimal wiring result of the circuit to be optimized. The invention realizes the automatic wiring problem after the layout of the superconducting integrated circuit, reduces the design cost and reduces the design time overhead caused by manual wiring.)

1. A wiring optimization method for a superconducting integrated circuit, comprising:

acquiring coordinate positions of all logic gates in the circuit to be optimized based on layout information of the circuit to be optimized, acquiring interconnection relations among all logic gates in the circuit to be optimized based on a circuit netlist of the circuit to be optimized, matching the coordinate positions of all the logic gates with the interconnection relations among all the logic gates, and acquiring coordinate interconnection lines of all the logic gates;

sequentially carrying out wiring operation on all the coordinate interconnection lines based on preset wiring operation to obtain operation results, judging whether the coordinate interconnection lines are successfully wired or not based on the operation results, if so, storing the operation results into a preset database, otherwise, adding the corresponding coordinate interconnection lines into a failure queue;

judging whether the failure queue meets preset requirements or not, if so, searching an optimal wiring result from the preset database based on preset conditions, otherwise, improving the operation priority of the interconnection lines in the failure queue, and performing wiring operation on the coordinate interconnection lines based on preset wiring operation again to obtain an operation result;

optimizing the clock interconnection lines in the optimal wiring result by reducing a path delay mode and/or increasing a path delay mode so as to reduce the deviation values of the clock interconnection lines among different clock levels and obtain a primary optimization result;

and performing static time sequence analysis on the signal interconnection lines in the preliminary optimization result to obtain a time sequence violation signal queue and a normal time sequence signal queue, repairing the signal interconnection lines in the time sequence violation signal queue in a way of reducing path delay and/or increasing path delay, and optimizing the signal interconnection lines in the normal time sequence signal queue in a way of reducing path delay to obtain an optimized wiring result of the circuit to be optimized.

2. The method of claim 1, wherein the step of obtaining the coordinate interconnection line and the step of performing the routing operation further comprises:

and grouping all the coordinate interconnecting lines based on the coordinates of the starting points of the coordinate interconnecting lines, the coordinates of the end points of the coordinate interconnecting lines and a preset grouping tolerance to obtain a plurality of interconnecting line groups.

3. The method of claim 2, wherein between the step of obtaining the set of interconnect lines and the step of performing the routing operation further comprises:

sequencing each interconnection line group respectively to obtain a corresponding wiring queue;

wherein sorting the single group of interconnect lines to obtain a corresponding routing queue comprises:

sequencing the clock interconnection lines in the interconnection line group, sequencing the signal interconnection lines in the latest failure queue in the interconnection line group, and sequencing the remaining signal interconnection lines in the interconnection line group to obtain a wiring queue of the interconnection line group.

4. The method of claim 3, wherein determining whether the failure queue meets a preset requirement, if so, searching for an optimal routing result from the preset database based on a preset condition, and otherwise, increasing the operation priority of the interconnection lines in the failure queue comprises:

when all the interconnection lines in the wiring queue complete wiring operation, taking the signal interconnection line in the latest failure queue in the wiring queue as a failure sub-queue of the wiring queue;

sequentially judging whether the failure sub-queues meet preset requirements, if so, searching the optimal queue wiring results corresponding to the wiring queues from the preset database, and otherwise, re-sequencing the corresponding interconnection line groups based on the failure sub-queues;

and after the optimal queue wiring results corresponding to all the interconnection line groups are obtained, the optimal queue wiring results form the optimal wiring results.

5. The method of claim 1, wherein the predetermined routing operation is a-algorithm, and the cost function of the a-algorithm is a sum of a corner cost, a process cost, a compensation cost, a shift cost, and a prediction cost.

6. The method of claim 1, wherein storing the operation result in a predetermined database comprises:

judging whether the wiring result is a multi-fan-out path or not, if the wiring result is the multi-fan-out path, adding the wiring result into a multi-fan-out path queue corresponding to the node, judging whether all the interconnection lines in the node complete wiring operation or not, if so, merging the corresponding multi-fan-out path queues, and storing a merging result into the preset database, otherwise, not merging, and if the wiring result is a single-fan-out path, storing the wiring result into the preset database.

7. The method of claim 1, wherein the reduced path delay mode comprises a long distance josephson junction replacement mode and a passive transmission line replacement mode, and the increased path delay mode comprises a mode of replacing with more delay units containing josephson junctions and a mode of searching for vacant positions for clock extension.

8. A wiring optimization device of a superconducting integrated circuit is characterized by comprising a coordinate interconnection line acquisition module, a wiring operation module, an optimal wiring result acquisition module, a clock optimization module and a wiring optimization module,

the coordinate interconnection line acquisition module is used for acquiring coordinate positions of all logic gates in the circuit to be optimized based on layout information of the circuit to be optimized, acquiring interconnection relations among all logic gates in the circuit to be optimized based on a circuit netlist of the circuit to be optimized, matching the coordinate positions of all the logic gates with the interconnection relations among all the logic gates, and acquiring coordinate interconnection lines of all the logic gates;

the wiring operation module is used for sequentially carrying out wiring operation on all the coordinate interconnection lines based on preset wiring operation to obtain operation results, judging whether the coordinate interconnection lines are successfully wired or not based on the operation results, if so, storing the operation results into a preset database, and otherwise, adding the corresponding coordinate interconnection lines into a failure queue;

the optimal wiring result acquisition module is used for judging whether the failure queue meets preset requirements or not, searching an optimal wiring result from the preset database based on preset conditions if the failure queue meets the preset requirements, otherwise, improving the operation priority of the interconnection lines in the failure queue, and performing wiring operation on all the coordinate interconnection lines in sequence based on preset wiring operation again to obtain an operation result;

the clock optimization module is used for optimizing the clock interconnection line in the optimal wiring result by reducing a path delay mode and/or increasing a path delay mode so as to reduce the deviation value of the clock interconnection line among different clock levels and obtain a primary optimization result;

the wiring optimization module is used for performing static time sequence analysis on the signal interconnection lines in the preliminary optimization result to obtain a time sequence violation signal queue and a normal time sequence signal queue, repairing the signal interconnection lines in the time sequence violation signal queue in a path delay reducing mode and/or a path delay increasing mode, and optimizing the signal interconnection lines in the normal time sequence signal queue in a path delay reducing mode to obtain an optimized wiring result of the circuit to be optimized.

9. A storage medium on which a computer program is stored, characterized in that the program, when executed by a processor, implements the wiring optimization method of a superconducting integrated circuit according to any one of claims 1 to 7.

10. A terminal, comprising: a processor and a memory;

the memory is used for storing a computer program, and the processor is used for executing the computer program stored by the memory to make the terminal execute the wiring optimization method of the superconducting integrated circuit according to any one of claims 1 to 7.

Technical Field

The present invention relates to the technical field of layout of a superconducting integrated circuit, and in particular, to a method and an apparatus for optimizing wiring of a superconducting integrated circuit, a storage medium, and a terminal.

Background

Superconducting integrated circuits refer to integrated circuits based on josephson junctions and superconducting materials, including Single-Flux-Quantum (SFQ) circuits.

The SFQ circuit is a relatively special superconducting integrated circuit, which is mainly composed of josephson junctions, and digital logic "0" and "1" are represented by the presence or absence of a magnetic flux quantum Φ 0. Compared with a traditional semiconductor CMOS (complementary Metal Oxide semiconductor) circuit, the micro and quantitative properties of the flux quanta obviously reduce the influence of crosstalk and power consumption, and narrow voltage pulses generated in the junctions when the flux quanta enter and exit the loop enable the flux quanta to obtain extremely high frequency. The circuit has the advantages of ultrahigh working speed and extremely low power consumption, so that the circuit has a remarkable prospect in the application of ultra-wide bandwidth Analog-to-Digital converters (ADC), superconducting computers and the like.

The large-scale design of SFQ circuits is largely limited by the performance of electronic design automation tools (EDAs), and the support of SFQ designs by current commercial and open-source EDA tools is insufficient to meet the requirements of SFQ circuits. Since the current EDA tools are mainly developed around CMOS circuits, it is difficult to fully support the automated design of the SFQ circuits on some key attributes, such as gate level pipeline, high fan-out concurrent clock tree, etc., so that it is only possible to rely on the existing EDA tools, and use a large number of flows for manual design, but the manual design cannot cover the higher scale circuits (circuit scale larger than ten thousand node level), and it takes a long time, which seriously affects the design iteration cycle of the SFQ circuits.

Disclosure of Invention

The invention aims to solve the technical problems that the existing wiring mode of the superconducting integrated circuit still has a large number of manual design processes, takes longer time, seriously influences the design iteration cycle of the superconducting integrated circuit and cannot be applied to a high-scale superconducting integrated circuit.

In order to solve the above technical problem, the present invention provides a wiring optimization method for a superconducting integrated circuit, including:

acquiring coordinate positions of all logic gates in the circuit to be optimized based on layout information of the circuit to be optimized, acquiring interconnection relations among all logic gates in the circuit to be optimized based on a circuit netlist of the circuit to be optimized, matching the coordinate positions of all the logic gates with the interconnection relations among all the logic gates, and acquiring coordinate interconnection lines of all the logic gates;

sequentially carrying out wiring operation on all the coordinate interconnection lines based on preset wiring operation to obtain operation results, judging whether the coordinate interconnection lines are successfully wired or not based on the operation results, if so, storing the operation results into a preset database, otherwise, adding the corresponding coordinate interconnection lines into a failure queue;

judging whether the failure queue meets preset requirements or not, if so, searching an optimal wiring result from the preset database based on preset conditions, otherwise, improving the operation priority of the interconnection lines in the failure queue, and performing wiring operation on all the coordinate interconnection lines in sequence based on preset wiring operation again to obtain an operation result;

optimizing the clock interconnection lines in the optimal wiring result by reducing a path delay mode and/or increasing a path delay mode so as to reduce the deviation values of the clock interconnection lines among different clock levels and obtain a primary optimization result;

and performing static time sequence analysis on the signal interconnection lines in the preliminary optimization result to obtain a time sequence violation signal queue and a normal time sequence signal queue, repairing the signal interconnection lines in the time sequence violation signal queue in a way of reducing path delay and/or increasing path delay, and optimizing the signal interconnection lines in the normal time sequence signal queue in a way of reducing path delay to obtain an optimized wiring result of the circuit to be optimized.

Preferably, the step of obtaining the coordinate interconnection line and the step of performing the wiring operation further include:

and grouping all the coordinate interconnecting lines based on the coordinates of the starting points of the coordinate interconnecting lines, the coordinates of the end points of the coordinate interconnecting lines and a preset grouping tolerance to obtain a plurality of interconnecting line groups.

Preferably, the step of acquiring the group of interconnect lines and the step of performing the routing operation further comprise:

sequencing each interconnection line group respectively to obtain a corresponding wiring queue;

wherein sorting the single group of interconnect lines to obtain a corresponding routing queue comprises:

sequencing the clock interconnection lines in the interconnection line group, sequencing the signal interconnection lines in the latest failure queue in the interconnection line group, and sequencing the remaining signal interconnection lines in the interconnection line group to obtain a wiring queue of the interconnection line group.

Preferably, whether the failure queue meets a preset requirement is judged, if yes, an optimal wiring result is searched from the preset database based on a preset condition, and otherwise, improving the operation priority of the interconnection lines in the failure queue comprises:

after all the interconnection lines in the wiring queue complete wiring operation, all the signal interconnection lines belonging to the latest failure queue in the wiring queue are used as failure sub-queues of the wiring queue;

sequentially judging whether the failure sub-queues meet preset requirements, if so, searching the optimal queue wiring results corresponding to the wiring queues from the preset database, and otherwise, re-sequencing the corresponding interconnection line groups based on the failure sub-queues;

and after the optimal queue wiring results corresponding to all the interconnection line groups are obtained, the optimal queue wiring results form the optimal wiring results.

Preferably, the preset routing operation is an a-algorithm, and the cost function of the a-algorithm is the sum of a corner cost, a process cost, a compensation cost, a movement cost and a prediction cost.

Preferably, the storing the operation result into a preset database includes:

judging whether the wiring result is a multi-fan-out path or not, if the wiring result is the multi-fan-out path, adding the wiring result into a multi-fan-out path queue corresponding to the node, judging whether all the interconnection lines in the node complete wiring operation or not, if so, merging the corresponding multi-fan-out path queues, and storing a merging result into the preset database, otherwise, not merging, and if the wiring result is a single-fan-out path, storing the wiring result into the preset database.

Preferably, the reduced path delay mode comprises a long-distance josephson junction replacement mode and a passive transmission line replacement mode, and the increased path delay mode comprises a mode of replacing by using more delay units containing josephson junctions and a mode of searching for vacant positions to perform clock extension.

In order to solve the above technical problems, the present invention further provides a wiring optimization apparatus for a superconducting integrated circuit, comprising a coordinate interconnection line acquisition module, a wiring operation module, an optimal wiring result acquisition module, a clock optimization module and a wiring optimization module,

the coordinate interconnection line acquisition module is used for acquiring coordinate positions of all logic gates in the circuit to be optimized based on layout information of the circuit to be optimized, acquiring interconnection relations among all logic gates in the circuit to be optimized based on a circuit netlist of the circuit to be optimized, matching the coordinate positions of all the logic gates with the interconnection relations among all the logic gates, and acquiring coordinate interconnection lines of all the logic gates;

the wiring operation module is used for sequentially carrying out wiring operation on all the coordinate interconnection lines based on preset wiring operation to obtain operation results, judging whether the coordinate interconnection lines are successfully wired or not based on the operation results, if so, storing the operation results into a preset database, and otherwise, adding the corresponding coordinate interconnection lines into a failure queue;

the optimal wiring result acquisition module is used for judging whether the failure queue meets preset requirements or not, searching an optimal wiring result from the preset database based on preset conditions if the failure queue meets the preset requirements, otherwise, improving the operation priority of the interconnection lines in the failure queue, and performing wiring operation on all the coordinate interconnection lines in sequence based on preset wiring operation again to obtain an operation result;

the clock optimization module is used for optimizing the clock interconnection line in the optimal wiring result by reducing a path delay mode and/or increasing a path delay mode so as to reduce the deviation value of the clock interconnection line among different clock levels and obtain a primary optimization result;

the wiring optimization module is used for performing static time sequence analysis on the signal interconnection lines in the preliminary optimization result to obtain a time sequence violation signal queue and a normal time sequence signal queue, repairing the signal interconnection lines in the time sequence violation signal queue in a path delay reducing mode and/or a path delay increasing mode, and optimizing the signal interconnection lines in the normal time sequence signal queue in a path delay reducing mode to obtain an optimized wiring result of the circuit to be optimized.

In order to solve the above technical problem, the present invention also provides a storage medium having stored thereon a computer program which, when executed by a processor, implements the wiring optimization method of the superconducting integrated circuit.

In order to solve the above technical problem, the present invention further provides a terminal, including: a processor and a memory;

the memory is used for storing computer programs, and the processor is used for executing the computer programs stored by the memory so as to enable the terminal to execute the wiring optimization method of the superconducting integrated circuit.

Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:

by applying the wiring optimization method of the superconducting integrated circuit provided by the embodiment of the invention, the automatic wiring problem after the superconducting integrated circuit is arranged is realized, the design cost is reduced, and the design time overhead caused by manual wiring is reduced; when further wiring optimization is carried out, wiring optimization of a clock tree and a signal line can be customized by using various types of Josephson transmission lines and wireless transmission lines, the compatibility of a superconducting integrated circuit (such as SFQ) process is better, flexible adjustment can be carried out according to process conditions, and the method is suitable for mixed wiring of the Josephson junction transmission lines and the passive transmission lines. The method is suitable for clock tree wiring of constant-flow and Counter-flow and signal line wiring of a Bit-slice circuit structure.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic flow chart showing a method for optimizing routing of a superconducting integrated circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating an analysis of obtaining coordinate interconnection lines according to a first embodiment of the present invention;

FIG. 3 is a diagram illustrating the effect of routing groups according to a first embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating the effect of the routing ordering according to the first embodiment of the present invention;

fig. 5 is a schematic flow chart of an improved a-algorithm in one embodiment of the present invention

FIG. 6 is a schematic diagram illustrating a flow chart of a routing operation performed by a single group of interconnect lines according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating an alternative node and an extended path in signal interconnect optimization according to a first embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating optimized clock interconnects in accordance with one embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating an overall flow of signal interconnect optimization according to a first embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating an effect of an SFQ interconnection line generator according to a first embodiment of the present invention;

FIG. 11 is a schematic diagram illustrating an optimized routing result of a circuit to be optimized according to a first embodiment of the present invention;

FIG. 12 is a schematic structural view showing a wiring optimization apparatus for a second superconducting integrated circuit according to an embodiment of the present invention;

fig. 13 shows a schematic structural diagram of a four-terminal according to an embodiment of the present invention.

Detailed Description

The following detailed description of the embodiments of the present invention will be provided with reference to the drawings and examples, so that how to apply the technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.

The large-scale design of superconducting integrated circuits such as SFQ circuits is largely limited by the performance of electronic design automation tools (EDAs), and the support of SFQ designs by current commercial and open source EDA tools is insufficient to meet the requirements of SFQ circuits. Since the current EDA tools are mainly developed around CMOS circuits, it is difficult to fully support the automated design of the SFQ circuits on some key attributes, such as gate level pipeline, high fan-out concurrent clock tree, etc., so that it is only possible to rely on the existing EDA tools, and use a large number of flows for manual design, but the manual design cannot cover the higher scale circuits (circuit scale larger than ten thousand node level), and it takes a long time, which seriously affects the design iteration cycle of the SFQ circuits.

Example one

In order to solve the technical problems in the prior art, the embodiment of the invention provides a wiring optimization method for a superconducting integrated circuit.

FIG. 1 is a schematic flow chart showing a method for optimizing routing of a superconducting integrated circuit according to an embodiment of the present invention; referring to fig. 1, a method for optimizing the wiring of a superconducting integrated circuit according to an embodiment of the present invention includes the following steps.

Step S101, obtaining coordinate positions of all logic gates in the circuit to be optimized based on layout information of the circuit to be optimized, obtaining interconnection relations among all logic gates in the circuit to be optimized based on a circuit netlist of the circuit to be optimized, matching the coordinate positions of all logic gates with the interconnection relations among all logic gates, and obtaining coordinate interconnection lines of all logic gates.

Specifically, during wiring optimization, layout information and a circuit netlist of a circuit to be optimized are acquired first, then coordinate positions of all logic gates in the circuit to be optimized are acquired based on the layout information of the circuit to be optimized, and interconnection relations among all the logic gates in the circuit to be optimized are acquired based on the circuit netlist of the circuit to be optimized. The path to be optimized can be a circuit with a Bit-slice structure.

In the invention, the interconnection relationship among all logic gates in the circuit to be optimized is obtained by adopting a method for analyzing the Verilog netlist. Extracting and storing a hierarchical structure of a circuit to be optimized, the name of an input/output port and the information of the instantiated device by a Verilog netlist compiler, acquiring a port of each logic gate and a node name corresponding to the port by using a port mapping statement in the information of the instantiated device, and storing the port of each logic gate and the node name corresponding to the port in a Hash table; after the storage of all the ports and the node names is completed, the logical gate ports corresponding to the nodes can be quickly extracted by utilizing the hash table, and then the interconnection relationship is obtained. The layout information can be derived through an interface program of a layout editor, then the analysis module is used for extracting models, ports, coordinates and rotation directions of all units in the layout, the spatial position coordinates of all ports of all the units are obtained through calculation by using the information and a graph calculation function, and the spatial position coordinates are stored in a hash table.

FIG. 2 is a schematic diagram illustrating an analysis of obtaining coordinate interconnection lines according to a first embodiment of the present invention; referring to fig. 2, after obtaining the coordinate positions of all the logic gates and the interconnection relationships among all the logic gates, matching the coordinate positions of all the logic gates and the interconnection relationships among all the logic gates, so as to obtain the coordinate interconnection lines among the logic gates expressed in the form of spatial position coordinates.

And S102, grouping all the coordinate interconnection lines based on the coordinates of the starting points of the coordinate interconnection lines, the coordinates of the end points of the coordinate interconnection lines and a preset grouping tolerance to obtain a plurality of interconnection line groups.

Specifically, after coordinate interconnection lines between logic gates are acquired, the coordinate interconnection lines need to be grouped. FIG. 3 is a diagram illustrating the effect of routing groups according to a first embodiment of the present invention; referring to fig. 3, grouping mainly uses the coordinates of the start point and the coordinates of the end point of the coordinate interconnection lines as a standard, and groups all the coordinate interconnection lines according to the grouping tolerance (i.e. the preset grouping tolerance) set by the program to obtain a plurality of interconnection line groups. The purpose of grouping the coordinate interconnection lines is to divide the coordinate interconnection lines into different wiring areas by taking the space position as a standard, limit the routing space of the coordinate interconnection lines in the routing calculation process and prevent unreasonable paths from being generated; meanwhile, different wiring groups can be added into the process pool, multi-core parallel operation is achieved, and the operation speed and efficiency of the wiring program are improved. It should be noted that the type of the coordinate interconnection line in the interconnection line group at least includes a signal interconnection line, and usually also includes a clock interconnection line, where the ordering modes of the clock interconnection line and the clock interconnection line are determined according to preset acquired or set clock data.

Step S103, sorting each interconnection line group to obtain a corresponding routing queue.

Specifically, after a plurality of interconnection line groups are obtained, coordinate interconnection lines in each interconnection line group need to be grouped, so that subsequent wiring operation can be performed according to a set sequence. Since all the interconnect line groups perform the same coordinate interconnect line sorting method, the following description will take the coordinate interconnect line sorting method in one interconnect line group as an example. FIG. 4 is a schematic diagram illustrating the effect of the routing ordering according to the first embodiment of the present invention; referring to FIG. 4, the coordinate interconnect lines within a single interconnect group are ordered in the following manner: firstly, determining coordinate interconnection lines (namely clock interconnection lines) belonging to clock properties in the coordinates of interconnection line groups based on clock data, and sequencing all the clock interconnection lines based on the clock data; then judging whether a latest failure queue exists, if so, selecting all coordinate interconnection lines (namely signal interconnection lines) belonging to the latest failure queue from the remaining coordinate interconnection lines in the interconnection line group, and sequencing the coordinate interconnection lines on the basis of current sequencing; if the latest failure queue does not exist or the coordinate interconnection lines belonging to the latest failure queue are sequenced, sequencing all the remaining coordinate interconnection lines (namely, signal interconnection lines) in the interconnection line group to obtain the wiring queue of the interconnection line group.

No matter the signal interconnection lines in the latest failure queue or the rest signal interconnection lines in the interconnection line group are sequenced by adopting the following sequencing mode: analyzing the node fan-out values of all the signal interconnection lines, sequencing all the signal interconnection lines in the sequence of the node fan-out values from large to small, and sequencing the signal interconnection lines with the same node fan-out values in the sequence of the Manhattan distance from large to small.

It should be noted that, the clock interconnection line may be routed after the signal interconnection line is routed, but the clock signal line needs to be inserted into the forefront of the signal interconnection line routing queue to ensure that the priority of the clock tree routing is highest.

And step S104, sequentially carrying out wiring operation on all the coordinate interconnection lines based on preset wiring operation to obtain operation results, judging whether the corresponding coordinate interconnection lines are successfully wired or not based on the operation results, if so, storing the operation results into a preset database, and otherwise, adding the corresponding coordinate interconnection lines into a failure queue.

Specifically, before each interconnection line group performs the routing operation, the logic gate in the routing area needs to be added into the routing map as a shielding area to prohibit routing units in the same layer from passing through the area; meanwhile, a protective layer is added at all the ports to prevent the ports which are not wired from being blocked by other interconnecting wires.

And then, carrying out wiring operation on the coordinate interconnection lines in all the interconnection line groups respectively based on preset wiring operation to obtain an operation result corresponding to each interconnection line. Fig. 6 is a schematic flow chart illustrating a routing operation performed by a single interconnect line group according to an embodiment of the present invention. It should be noted that each group of interconnect lines is a preset routing operation performed in the order of its corresponding routing queue. Further, after the operation result of each coordinate interconnection line is obtained, whether the corresponding coordinate interconnection line is successfully wired or not needs to be judged based on the operation result, if the wiring is successful, the operation result is stored into a preset database, otherwise, the corresponding coordinate interconnection line is added into a failure queue, and meanwhile, failure information is added into a log.

Further, the routing operation is preset to be an improved a routing algorithm, fig. 5 shows a schematic flow chart of the improved a routing algorithm in the first embodiment of the present invention, referring to fig. 5, an improved a routing algorithm in the first embodiment of the present invention adds a corner cost, a process layer cost, and a compensation cost on the basis of an original cost function of the a routing algorithm, so that the routing program finds, as far as possible, a path result with fewer corners and fewer layer changes, and determines a layer change capacity of the routing grid points according to the number of routing layers, that is, for each node, the primary cost function is f (n) ═ g (n) + h (n), where g (n) is a movement cost, and h (n) is a prediction cost; the improvement is f (n) ═ g (n) + h (n) + c (n) + l (n) + o (n), where c (n) is the corner cost, l (n) is the process cost, and o (n) is the compensation cost. In the process of routing and point taking, various constraint conditions are added according to a process library used by a user, so that a control program searches for a path which can be converted into a layout in the process of routing, for example, when an interconnection line cross unit with the size of a unit exists in the process library, if a current lattice point is crossed, the routing direction is limited to be straight, and the point can not be taken in another direction.

Further, the process of storing the operation result in the preset database specifically includes: judging whether the wiring result is a multi-fan-out path, if the wiring result is the multi-fan-out path, adding the wiring result into a multi-fan-out path queue corresponding to a node to which the corresponding coordinate interconnection line belongs, judging whether all the interconnection lines in the node to which the wiring result belongs complete wiring operation, if so, merging the corresponding multi-fan-out path queues, and storing a merging result into a preset database, otherwise, not merging, and if the wiring result is the single-fan-out path, directly storing the wiring result into the preset database. The preset database comprises a routing map and wiring grid point data.

And S105, judging whether the failure queue meets the preset requirement, if so, searching the optimal wiring result from a preset database based on the preset condition, otherwise, improving the operation priority of the interconnection lines in the failure queue, and performing wiring operation on the coordinate interconnection lines in sequence based on the preset wiring operation again to obtain the operation result.

Specifically, this step is also performed separately for each group of interconnect lines, and the operation performed for each group is as follows: and when all the coordinate interconnection lines in the wiring queue complete wiring operation, judging whether iterative wiring optimization is carried out or not according to the condition of the failed coordinate interconnection line. Namely, all signal interconnection lines belonging to the latest failure queue in the routing queue are firstly used as the failure sub-queue of the routing queue. After all coordinate interconnection lines in the wiring queue complete wiring operation, judging whether the failure sub-queue of the wiring queue meets the preset requirement or not, if so, searching the optimal queue wiring result of the wiring queue from a preset database, namely searching all wiring schemes of the existing wiring queue from the preset database, and searching one wiring scheme which best meets the set conditions from all the wiring schemes to serve as the optimal queue wiring result. If the failure sub-queue of the wiring queue does not meet the preset requirement, the operation priority in the failure sub-queue is improved, and the interconnection line groups corresponding to the failure sub-queue are sorted based on the failure sub-queue based on the preset wiring operation again to obtain a new wiring queue corresponding to the interconnection line groups. That is, when the failure sub-queue of the routing queue does not meet the preset requirement, the process goes to step S103, and the corresponding interconnect line group is reordered based on the failure sub-queue.

And after all the interconnection line groups acquire the corresponding optimal queue wiring result, all the optimal queue wiring results form the optimal wiring result of the circuit to be optimized.

And further, presetting a requirement that the coordinate interconnection lines in the failure sub-queue are 0 or entering an invalid wiring cycle, wherein the invalid wiring cycle is that the wiring sequence of the wiring queue repeatedly appears in the wiring scheme of the wiring queue. The setting conditions may be set according to user requirements, and preferably, the setting conditions may include limitations on conditions such as the number of successful wirings, the area utilization rate, and the wiring length.

It should be noted that the failure sub-queue here is a queue formed by all coordinate interconnection lines in the latest failure queue selected from the remaining coordinate interconnection lines in the interconnection line group in step S103.

And step S106, optimizing the clock interconnection line in the optimal wiring result by reducing the path delay mode and/or increasing the path delay mode so as to reduce the deviation value of the clock interconnection line among different clock levels and obtain a primary optimization result.

Specifically, after the optimal wiring result of the circuit to be optimized is obtained, the clock tree therein is subjected to incremental optimization, and the clock tree is reconstructed by using other types of Josephson junction transmission lines in the cell library, so that the deviation value of the clock interconnection line between different clock levels is reduced, and the initial optimization result is obtained. Further, the clock interconnection line in the optimal wiring result is optimized through a path delay reducing mode and/or a path delay increasing mode, wherein the path delay reducing mode comprises a long-distance Josephson junction replacing mode and an edge-free transmission line replacing mode, and the path delay increasing mode comprises a mode of replacing by using more delay units containing Josephson junctions and a mode of searching for vacant positions to conduct clock extension. FIG. 7 is a schematic diagram illustrating an alternative node and an extended path in signal interconnect optimization according to a first embodiment of the present invention; FIG. 8 is a diagram illustrating an optimized clock interconnect line according to one embodiment of the present invention.

FIG. 11 is a schematic diagram illustrating optimized clock interconnect lines in accordance with one embodiment of the present invention; as shown in fig. 7, the optimization process of the clock tree in the figure is: firstly, optimizing a connecting path between trunk nodes, and shortening the length of the short path by using a long-distance Josephson junction; and then optimizing the path length from each trunk node to the clock end, namely optimizing from back to front, wherein each level of optimization needs to ensure that the time from the current level of trunk node to each clock end is consistent as much as possible, and the arrival time is equal to the average value of the time from the current level of trunk node to the next level of trunk node plus the time point of the next level of clock end. For example, when the second-level clock interconnection line is optimized, the connection path length of the third-level clock interconnection line exists, the time point data of all clock ends of the second level and the optimization target of the second-level to third-level clock tree are (350+352+351+352+350)/5+20, and the optimization target is 0 for the third level of the last level.

Wherein the clock tree type is clock tree of current-flow or Counter-flow.

And S107, performing static time sequence analysis on the signal interconnection lines in the preliminary optimization result to obtain a time sequence violation signal queue and a normal time sequence signal queue, repairing the signal interconnection lines in the time sequence violation signal queue in a path delay reducing mode and/or a path delay increasing mode, and optimizing the signal interconnection lines in the normal time sequence signal queue in a path delay reducing mode to obtain an optimized wiring result of the circuit to be optimized.

Specifically, the optimization of the clock interconnection line in the optimal wiring result is realized to obtain a preliminary optimization result, and then the communication signal connection line in the preliminary optimization result needs to be optimized.

FIG. 9 is a schematic diagram illustrating an overall flow of signal interconnect optimization according to a first embodiment of the present invention; referring to fig. 9, static timing analysis is further performed on all signal interconnection lines to obtain a timing violation signal queue and a normal timing signal queue. And then, repairing the signal interconnection lines in the sequence violation signal queues in a way of reducing path delay and/or a way of increasing path delay, and optimizing the signal interconnection lines in the normal sequence signal queues in a way of reducing path delay to obtain an optimized wiring result of the circuit to be optimized. The reduced path delay mode comprises a long-distance Josephson junction replacement mode and a passive transmission line replacement mode, and the increased path delay mode comprises a mode of replacing by using more delay units containing Josephson junctions and a mode of searching for vacant positions to extend clocks. Therefore, the normal time sequence signal queue is optimized to repair by adopting a long-distance Josephson junction or a passive transmission line as much as possible so as to ensure that the delay of a path is shortened, the delay of the whole circuit is reduced, and meanwhile, the path is ensured to meet the requirement of the holding time of the circuit. Fig. 11 is a schematic diagram illustrating an optimized routing result of a circuit to be optimized according to a first embodiment of the present invention. If the repair of a certain path cannot be completed, outputting repair failure information of the path to be used as guidance for adjusting the previous-stage layout optimization and clock tree synthesis.

And after an optimized wiring result of the circuit to be optimized is obtained, generating an example statement of the coordinate interconnection line according to the preset database and the optimized wiring result. FIG. 10 is a schematic diagram illustrating an effect of an SFQ interconnection line generator according to a first embodiment of the present invention; referring to fig. 10, an exemplary statement is mainly determined by a Layout editor, taking Virtuoso Layout XL of Cadence corporation as an example, for a single path, a program acquires a grid point coordinate and a path direction of a current path from wiring grid point data in a preset database, acquires an interconnection line unit of the current path from an optimized wiring result, and generates a dbcreate statement after the two are matched; after generating the dbcreate sentences of all the coordinate interconnection lines, reading the dbcreate sentences of all the coordinate interconnection lines by a SKILL interface module in Virtuos Layout XL, generating the coordinate interconnection lines in the existing Layout, and realizing the conversion of the wiring result to the Layout.

After all the interconnection line groups are wired, the top layer information collection module analyzes the wiring condition of each wiring line group, and outputs information such as failure paths, wiring time, wiring space utilization rate and the like for a designer to refer to so as to perform feedback optimization of layout and clock tree synthesis.

The wiring optimization method of the superconducting integrated circuit provided by the embodiment of the invention realizes the automatic wiring problem after the superconducting integrated circuit is arranged, reduces the design cost and reduces the design time overhead caused by manual wiring; when further wiring optimization is carried out, wiring optimization of a clock tree and a signal line can be customized by using various types of Josephson transmission lines and wireless transmission lines, the compatibility of a superconducting integrated circuit (such as SFQ) process is better, flexible adjustment can be carried out according to process conditions, and the method is suitable for mixed wiring of the Josephson junction transmission lines and the passive transmission lines. The method is suitable for clock tree wiring of constant-flow and Counter-flow and signal line wiring of a Bit-slice circuit structure.

Example two

In order to solve the above technical problems in the prior art, an embodiment of the present invention further provides a wiring optimization apparatus for a superconducting integrated circuit.

FIG. 12 is a schematic structural view showing a wiring optimization apparatus for a second superconducting integrated circuit according to an embodiment of the present invention; referring to fig. 12, the apparatus for optimizing routing of a superconducting integrated circuit according to an embodiment of the present invention includes a coordinate interconnection line obtaining module, a routing operation module, an optimal routing result obtaining module, a clock optimizing module, and a routing optimizing module.

The coordinate interconnection line obtaining module is used for obtaining coordinate positions of all logic gates in the circuit to be optimized based on layout information of the circuit to be optimized, obtaining interconnection relations among all logic gates in the circuit to be optimized based on a circuit netlist of the circuit to be optimized, matching the coordinate positions of all logic gates with the interconnection relations among all logic gates, and obtaining coordinate interconnection lines of all logic gates.

The wiring operation module is used for sequentially carrying out wiring operation on all the coordinate interconnection lines based on preset wiring operation to obtain operation results, judging whether the corresponding coordinate interconnection lines are successfully wired or not based on the operation results, if so, storing the operation results into a preset database, and otherwise, adding the corresponding coordinate interconnection lines into a failure queue.

The optimal wiring result obtaining module is used for judging whether the failure queue meets preset requirements or not, if yes, searching the optimal wiring result from a preset database based on preset conditions, otherwise, improving the operation priority of the interconnection lines in the failure queue, and performing wiring operation on all coordinate interconnection lines in sequence based on preset wiring operation again to obtain operation results.

The clock optimization module is used for optimizing the clock interconnection lines in the optimal wiring result in a way of reducing path delay and/or increasing path delay so as to reduce the deviation values of the clock interconnection lines among different levels and obtain a preliminary optimization result.

The wiring optimization module is used for carrying out static time sequence analysis on the signal interconnection lines in the preliminary optimization result, obtaining a time sequence violation signal queue and a normal time sequence signal queue, repairing the signal interconnection lines in the time sequence violation signal queue in a path delay reducing mode and/or a path delay increasing mode, optimizing the signal interconnection lines in the normal time sequence signal queue in a path delay reducing mode, and obtaining an optimized wiring result of the circuit to be optimized.

The wiring optimization device for the superconducting integrated circuit provided by the embodiment of the invention realizes the automatic wiring problem after the superconducting integrated circuit is arranged, reduces the design cost and reduces the design time overhead caused by manual wiring; when further wiring optimization is carried out, wiring optimization of a clock tree and a signal line can be customized by using various types of Josephson transmission lines and wireless transmission lines, the compatibility of a superconducting integrated circuit (such as SFQ) process is better, flexible adjustment can be carried out according to process conditions, and the method is suitable for mixed wiring of the Josephson junction transmission lines and the passive transmission lines. The device is suitable for clock tree wiring of constant-flow and Counter-flow and signal line wiring of a Bit-slice circuit structure.

EXAMPLE III

To solve the technical problems in the prior art, an embodiment of the present invention further provides a storage medium storing a computer program, and the computer program, when executed by a processor, can implement all the steps in the method for optimizing the routing of a superconducting integrated circuit according to the embodiment.

The specific steps of the wiring optimization method of the superconducting integrated circuit and the beneficial effects obtained by applying the readable storage medium provided by the embodiment of the invention are the same as those of the first embodiment, and are not described herein again.

It should be noted that: the storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Example four

In order to solve the technical problems in the prior art, the embodiment of the invention also provides a terminal.

Fig. 13 is a schematic structural diagram of a four-terminal according to an embodiment of the present invention, and referring to fig. 13, the terminal according to this embodiment includes a processor and a memory, which are connected to each other; the memory is used for storing a computer program, and the processor is used for executing the computer program stored by the memory, so that the terminal can realize all the steps in the wiring optimization method of the superconducting integrated circuit.

The specific steps of the wiring optimization method of the superconducting integrated circuit and the beneficial effects obtained by applying the terminal provided by the embodiment of the invention are the same as those of the first embodiment, and are not described herein again.

It should be noted that the Memory may include a Random Access Memory (RAM), and may also include a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. Similarly, the Processor may also be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.