阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 蔡巧明 张云香 于 2020-06-09 设计创作，主要内容包括：一种半导体结构及其形成方法,形成方法包括：提供基底,包括第一区域和第二区域；形成位于第一区域基底上的多晶硅栅极、位于第二区域基底上的金属栅极、以及位于多晶硅栅极和金属栅极侧部基底上的层间介质层；在第二区域的层间介质层上形成覆盖金属栅极的保护层,保护层露出多晶硅栅极；在多晶硅栅极的顶面形成栅极硅化物层。栅极硅化物层形成在多晶硅栅极的顶面,有利于增加栅极接触孔插塞与多晶硅栅极之间的粘附性以及降低栅极接触孔插塞与多晶硅栅极之间的接触电阻；保护层能够对金属栅极起到保护的作用,有利于降低金属栅极受损的几率以及减小形成栅极硅化物层的过程对金属栅极的影响。(A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate comprising a first region and a second region; forming a polysilicon gate on the substrate of the first region, a metal gate on the substrate of the second region and an interlayer dielectric layer on the substrate at the side parts of the polysilicon gate and the metal gate; forming a protective layer covering the metal gate on the interlayer dielectric layer of the second region, wherein the protective layer exposes out of the polysilicon gate; and forming a gate silicide layer on the top surface of the polysilicon gate. The grid silicide layer is formed on the top surface of the polysilicon grid, so that the adhesion between the grid contact hole plug and the polysilicon grid is increased, and the contact resistance between the grid contact hole plug and the polysilicon grid is reduced; the protective layer can protect the metal gate, and is beneficial to reducing the damage probability of the metal gate and reducing the influence of the process of forming the gate silicide layer on the metal gate.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a first area used for forming a first device and a second area used for forming a second device, and the working voltage of the first device is larger than that of the second device;

forming a polysilicon gate on the substrate of the first region, a metal gate on the substrate of the second region, and an interlayer dielectric layer on the substrate at the side parts of the polysilicon gate and the metal gate, wherein the interlayer dielectric layer exposes the top surfaces of the polysilicon gate and the metal gate;

forming a protective layer covering the metal grid electrode on the interlayer dielectric layer of the second area, wherein the protective layer exposes the polysilicon grid electrode;

and forming a gate silicide layer on the top surface of the polysilicon gate after the protective layer is formed.

2. The method of claim 1, wherein forming the polysilicon gate, the metal gate, and the interlayer dielectric layer comprises: forming the polysilicon gate positioned in a first region and a dummy gate positioned in a second region on the substrate, wherein gate mask layers are also formed on the tops of the polysilicon gate and the dummy gate;

forming the interlayer dielectric layer on the substrate at the side parts of the polysilicon gate and the dummy gate; the step of forming the interlayer dielectric layer comprises the following steps: forming an initial dielectric layer on the substrate, wherein the initial dielectric layer covers the grid mask layer; removing the initial dielectric layer and the gate mask layer which are higher than the top surfaces of the polysilicon gate and the dummy gate by adopting a planarization process, wherein the rest initial dielectric layer is used as the interlayer dielectric layer;

removing the dummy gate of the second region, and forming a gate opening in the interlayer dielectric layer of the second region;

forming the metal gate in the gate opening.

3. The method of claim 1, wherein forming the polysilicon gate, the metal gate, and the interlayer dielectric layer comprises: forming a polysilicon gate positioned in a first region and a dummy gate positioned in a second region on the substrate, wherein gate mask layers are also formed on the tops of the polysilicon gate and the dummy gate;

forming an interlayer dielectric layer on the substrate at the side parts of the polysilicon grid, the dummy grid and the grid mask layer;

removing the grid mask layer and the dummy grid in the second area, and forming a grid opening in the interlayer dielectric layer in the second area;

forming the metal gate in the gate opening; the step of forming the metal gate comprises: forming a metal gate material layer which is filled in the gate opening and is positioned on the interlayer dielectric layer; and removing the metal gate material layer and the interlayer dielectric layer which are higher than the top surface of the polysilicon gate and the gate mask layer of the first area by adopting a planarization process.

4. The method as claimed in claim 2 or 3, wherein after forming the polysilicon gate in the first region and the dummy gate in the second region on the substrate, the method further comprises, before forming the interlayer dielectric layer: forming source and drain doped regions in the substrate of the first region at two sides of the polycrystalline silicon grid electrode and the substrate of the second region at two sides of the pseudo grid electrode; forming a source drain silicide layer on the top surface of the source drain doped region;

in the step of forming the interlayer dielectric layer, the interlayer dielectric layer covers the source drain silicide layer.

5. The method of claim 2 or 3, wherein the planarization process comprises a chemical mechanical polishing process.

6. The method of forming a semiconductor structure of claim 1, wherein forming the protective layer comprises: forming a protective material layer covering the polysilicon grid and the metal grid on the interlayer dielectric layer; and removing the protective material layer in the first area to form the protective layer.

7. The method of claim 6, wherein the protective material layer is formed using a deposition process having a process temperature of less than 450 ℃.

8. The method of claim 6 or 7, wherein the process of forming the protective material layer comprises a chemical vapor deposition process or a thermal oxidation process.

9. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the protective layer, a material of the protective layer comprises silicon oxide or silicon nitride.

10. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the protective layer, the protective layer has a thickness of 15nm to 50 nm.

11. The method of forming a semiconductor structure of claim 1, wherein forming the gate silicide layer comprises: forming a metal layer covering the protective layer, the polysilicon gate and the interlayer dielectric layer of the first region;

forming a capping layer on the metal layer;

after the covering layer is formed, annealing treatment is carried out, so that the metal layer in contact with the polycrystalline silicon grid and the polycrystalline silicon grid with partial thickness are converted into the grid silicide layer;

and removing the covering layer and the residual metal layer positioned on the protective layer and the interlayer dielectric layer.

12. The method of forming a semiconductor structure of claim 11, wherein the process parameters of the annealing process comprise: the annealing temperature is lower than 450 ℃, and the annealing time is 20S to 80S.

13. The method of forming a semiconductor structure of claim 11, wherein forming the gate silicide layer further comprises: and cleaning the top surface of the polysilicon gate before the metal layer is formed.

14. The method of claim 11, wherein the annealing process comprises a dynamic surface annealing process, a rapid thermal annealing process, or a laser annealing process.

15. A semiconductor structure, comprising:

a substrate including a first region for forming a first device and a second region for forming a second device, an operating voltage of the first device being greater than an operating voltage of the second device;

the polysilicon grid is positioned on the substrate of the first region;

the metal grid is positioned on the substrate of the second area;

the interlayer dielectric layer is positioned on the substrate at the side parts of the polysilicon gate and the metal gate;

the protective layer is positioned on the interlayer dielectric layer of the second area and covers the metal grid, and the protective layer exposes the polysilicon grid;

and the grid silicide layer is positioned on the top surface of the polycrystalline silicon grid.

16. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: the source-drain doped regions are positioned in the substrate of the first region on two sides of the polycrystalline silicon grid electrode and the substrate of the second region on two sides of the metal grid electrode;

the source and drain silicide layer is positioned on the top surface of the source and drain doped region;

the interlayer dielectric layer covers the source drain silicide layer.

17. The semiconductor structure of claim 15, wherein the protective layer has a thickness of 15nm to 50 nm.

18. The semiconductor structure of claim 15, wherein a material of the protective layer comprises silicon oxide or silicon nitride.

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

In MOS transistor processes, in order to improve ohmic Contact between a source and a drain of a transistor and a Contact plug (Contact), a metal silicide is generally formed on the surface of the source and the drain. Currently, a Self-Aligned metal Silicide (Self-Aligned Silicide) process is mostly used to form a metal Silicide. Specifically, after forming the source and drain electrodes, a metal layer composed of cobalt, titanium, nickel, or the like is formed over the source and drain electrodes, and then the metal layer is reacted with silicon in the source and drain electrodes through one or more rapid annealing processes (RTA) to form a low-resistivity metal silicide, thereby reducing the sheet resistance (Rs) of the source and drain electrodes.

With the decreasing feature size of transistors, nickel silicide and platinum silicide are widely used as Contact (Contact) salicide due to their characteristics of smaller sheet resistance, lower silicon consumption, and lower annealing temperature.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area used for forming a first device and a second area used for forming a second device, and the working voltage of the first device is larger than that of the second device; forming a polysilicon gate on the substrate of the first region, a metal gate on the substrate of the second region, and an interlayer dielectric layer on the substrate at the side parts of the polysilicon gate and the metal gate, wherein the interlayer dielectric layer exposes the top surfaces of the polysilicon gate and the metal gate; forming a protective layer covering the metal grid electrode on the interlayer dielectric layer of the second area, wherein the protective layer exposes the polysilicon grid electrode; and forming a gate silicide layer on the top surface of the polysilicon gate after the protective layer is formed.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a first region for forming a first device and a second region for forming a second device, an operating voltage of the first device being greater than an operating voltage of the second device; the polysilicon grid is positioned on the substrate of the first region; the metal grid is positioned on the substrate of the second area; the interlayer dielectric layer is positioned on the substrate at the side parts of the polysilicon gate and the metal gate; the protective layer is positioned on the interlayer dielectric layer of the second area and covers the metal grid, and the protective layer exposes the polysilicon grid; and the grid silicide layer is positioned on the top surface of the polycrystalline silicon grid.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the method for forming the semiconductor structure provided by the embodiment of the invention, after the polysilicon gate, the metal gate and the interlayer dielectric layer are formed, a protective layer covering the metal gate is formed on the interlayer dielectric layer of the second area, and the polysilicon gate is exposed out of the protective layer; forming a gate silicide layer on the top surface of the polysilicon gate after forming the protective layer; that is, by forming a gate silicide layer on the top surface of the polysilicon gate after the metal gate is formed, the gate silicide layer can be formed on the top surface of the polysilicon gate, and accordingly, in the subsequent process of forming a gate contact hole plug electrically connected with the polysilicon gate, the gate silicide layer is positioned between the gate contact hole plug and the polysilicon gate, which is beneficial to increasing the adhesiveness between the gate contact hole plug and the polysilicon gate, reducing the contact resistance between the gate contact hole plug and the polysilicon gate, and further beneficial to improving the performance of the semiconductor structure; in addition, the protective layer covering the metal gate is formed on the interlayer dielectric layer in the second region, and the protective layer can protect the metal gate, so that the probability of damage to the metal gate and the influence of the process for forming the gate silicide layer on the metal gate are reduced.

Drawings

Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;

fig. 4 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

The devices formed at present still have the problem of poor performance. The medium-voltage device or the high-voltage device is taken as an example, and the reason of poor performance of the device is analyzed by combining a forming method of a semiconductor structure.

Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.

Referring to fig. 1, providing a substrate including a first region I for forming a first device and a second region II for forming a second device, an operating voltage of the first device being greater than an operating voltage of the second device; a polysilicon gate 11 positioned in a first area I and a dummy gate 12 positioned in a second area II are formed on the substrate, and a gate mask layer 13 is further formed on the tops of the polysilicon gate 11 and the dummy gate 12.

Referring to fig. 2, source-drain doped regions 14 are formed in the substrate of the first region I on both sides of the polysilicon gate 11 and in the substrate of the second region II on both sides of the dummy gate 12; forming a source drain silicide layer 15 on the top surface of the source drain doped region 14; the step of forming the source-drain silicide layer 15 includes: forming a metal layer (not shown) which conformally covers the source-drain doped region 14, the sidewalls of the polysilicon gate 11 and the dummy gate 12, and the gate mask layer 13; and annealing treatment is carried out, so that the metal layer reacts with the source drain doped region 14 with partial thickness to be converted into a source drain silicide layer 15.

Referring to fig. 3, an interlayer dielectric layer 16 covering the source-drain silicide layers 15 is formed on the substrate at the side portions of the polysilicon gate 11, the dummy gate 12, and the gate mask layer 13.

Wherein the second region II is used to form a second device, which is typically a logic device; the first region II is used to form a first device, which is typically a medium voltage device or a high voltage device. The first device uses a dummy gate, followed by the formation of a metal gate at the location of the dummy gate.

In the above forming method, in the process of forming the source-drain silicide layer 15, the gate mask layer 13 is still remained on the top of the polysilicon gate 11, and the top surface of the polysilicon gate 11 is not exposed in the salicide process, so that the metal layer does not contact the top surface of the polysilicon gate 11, and accordingly, in the step of performing annealing, a gate silicide layer is not formed on the top surface of the polysilicon gate 11. The subsequent steps further comprise: forming a gate contact hole plug in contact with the polysilicon gate 11, where the material of the gate contact hole plug is usually a metal material, and there is no gate silicide layer between the gate contact hole plug and the polysilicon gate 11, which easily causes the contact resistance between the gate contact hole plug and the polysilicon gate 11 to be too large, and thus easily reduces the performance of the medium-voltage device or the high-voltage device.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first area used for forming a first device and a second area used for forming a second device, and the working voltage of the first device is larger than that of the second device; forming a polysilicon gate on the substrate of the first region, a metal gate on the substrate of the second region, and an interlayer dielectric layer on the substrate at the side parts of the polysilicon gate and the metal gate, wherein the interlayer dielectric layer exposes the top surfaces of the polysilicon gate and the metal gate; forming a protective layer covering the metal grid electrode on the interlayer dielectric layer of the second area, wherein the protective layer exposes the polysilicon grid electrode; and forming a gate silicide layer on the top surface of the polysilicon gate after the protective layer is formed.

In the method for forming the semiconductor structure provided by the embodiment of the invention, after the polysilicon gate, the metal gate and the interlayer dielectric layer are formed, a protective layer covering the metal gate is formed on the interlayer dielectric layer of the second area, and the polysilicon gate is exposed out of the protective layer; forming a gate silicide layer on the top surface of the polysilicon gate after forming the protective layer; that is, by forming a gate silicide layer on the top surface of the polysilicon gate after the metal gate is formed, the gate silicide layer can be formed on the top surface of the polysilicon gate, and accordingly, in the subsequent process of forming a gate contact hole plug electrically connected with the polysilicon gate, the gate silicide layer is positioned between the gate contact hole plug and the polysilicon gate, which is beneficial to increasing the adhesiveness between the gate contact hole plug and the polysilicon gate, reducing the contact resistance between the gate contact hole plug and the polysilicon gate, and further beneficial to improving the performance of the semiconductor structure; in addition, the protective layer covering the metal gate is formed on the interlayer dielectric layer in the second region, and the protective layer can protect the metal gate, so that the probability of damage to the metal gate and the influence of the process for forming the gate silicide layer on the metal gate are reduced.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 4 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 4, a substrate 100 is provided, including a first region I for forming a first device having an operating voltage greater than an operating voltage of a second device, and a second region II for forming a second device.

The substrate 100 provides a platform for subsequent processing.

In this embodiment, the first region I is used to form a first device, the second region II is used to form a second device, and an operating voltage of the first device is greater than an operating voltage of the second device.

Specifically, the first device is a logic device, and the second device is a medium voltage device or a high voltage device. Logic devices generally have a lower operating voltage and a higher operating frequency, while medium or high voltage devices generally have a higher voltage capability than the logic devices. In this embodiment, the operating voltage of the medium-voltage device or the high-voltage device is at least 3V. The medium-voltage device generally refers to a device with an operating voltage of 3V to 10V, and the operating voltage of the high-voltage device is greater than 10V.

As an example, the second region II includes an NMOS region (not labeled) and a PMOS region (not labeled).

In this embodiment, the substrate 100 is a planar substrate.

In this embodiment, the base 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.

In this embodiment, a trench (not shown) is further formed in the substrate 100, and an isolation structure 105 is formed in the trench. The trenches provide spatial locations for forming isolation structures 105.

In this embodiment, the substrate 100 is etched to form the trench, so as to define an Active Area (AA) and an isolation Area on the substrate 100. Specifically, a plurality of isolated trenches are formed in the substrate 100, and the substrate 100 isolated by the trenches is used as an active region.

Isolation structures 105 are used to isolate adjacent devices.

In this embodiment, the isolation structure 105 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxynitride.

With reference to fig. 4 to 9, a polysilicon gate 110 on the substrate 100 in the first region I, a metal gate 160 on the substrate 100 in the second region II, and an interlayer dielectric layer 150 on the substrate 100 at the side of the polysilicon gate 110 and the metal gate 160 are formed, wherein the interlayer dielectric layer 150 exposes the top surfaces of the polysilicon gate 110 and the metal gate 160.

The operating voltage of the first device is greater than that of the second device, the first device is generally a device with higher withstand voltage capability, and the second device is generally a device with lower operating voltage. For example: the first device is a medium-voltage or high-voltage device, the second device is a logic device, the working frequency of the second device is greater than that of the first device, and the performance requirement of the second device is higher than that of the first device. Therefore, by forming the polysilicon gate 110 in the first region I and forming the metal gate 160 in the second region II, the working voltage of the first device is increased, the process cost is reduced, the second device has a lower working voltage, and the performance of the second device meets the design requirement.

The polysilicon gate 110 and the metal gate 160 are device gates, and when the device works, the polysilicon gate 110 is used for controlling the conduction channel of the first device to be turned on or turned off, and the metal gate 160 is used for controlling the conduction channel of the second device to be turned on or turned off.

The material of the polysilicon gate 110 is polysilicon.

The metal gate 160 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.

The high-k gate dielectric layer is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO₂. In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al₂O₃And the like.

The work function layer is used to adjust the threshold voltage of the formed transistor. When forming PMOS, the work function layer is P-type work function layer, and the material of P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. When forming NMOS, the work function layer is N-type work function layer, and the material of P-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAl C.

The gate electrode layer is used to make electrical connection between the metal gate and external circuitry or other interconnect structures. In this embodiment, the gate electrode layer is made of Al. In other embodiments, the material of the gate electrode layer may also be W, Cu, Ag, Au, Pt, Ni, or Ti.

An interlevel dielectric layer 150 isolates adjacent devices.

The material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide.

As an example, the step of forming the polysilicon gate 110, the metal gate 160 and the interlayer dielectric layer 150 includes:

as shown in fig. 4, a polysilicon gate 110 located in a first region I and a dummy gate 115 located in a second region II are formed on the substrate 100, and a gate mask layer 120 is further formed on top of the polysilicon gate 110 and the dummy gate 115.

The dummy gate 115 is used for forming a metal gate occupying space position in the second region II.

In this embodiment, the material of the dummy gate 115 is the same as that of the polysilicon gate 110, and the material of the dummy gate 115 is polysilicon.

The gate mask layer 120 is used as an etching mask for forming the polysilicon gate 110 and the dummy gate 115.

In this embodiment, the gate mask layer 120 is made of silicon nitride.

In this embodiment, the steps of forming the polysilicon gate 110 and the dummy gate 115 include: forming a gate material layer (not shown) on the substrate 100; forming the gate mask layer 120 on the gate material layer; and etching the gate material layer by taking the gate mask layer 120 as a mask, wherein the part of the gate material layer which is remained on the substrate 100 in the first region I is used as the polysilicon gate 110, and the part of the gate material layer which is remained on the substrate 100 in the second region II is used as the dummy gate 115.

In this embodiment, the method for forming the semiconductor structure further includes: before forming the polysilicon gate 110 and the dummy gate 115, a gate oxide layer 101 is formed on the substrate 100 exposed by the isolation structure 105.

The gate oxide layer 101 is used to isolate the polysilicon gate 110 from the substrate 100 and to isolate the subsequent metal gate from the substrate 100. The material of the gate oxide layer 101 comprises silicon oxide or silicon oxynitride.

In order to improve the reliability of the first device (for example, increase the breakdown voltage), in this embodiment, the thickness of the gate oxide layer 101 in the first region I is greater than that of the gate oxide layer 101 in the second region II.

In this embodiment, the method for forming the semiconductor structure further includes: spacers (not shown) are formed on the sidewalls of the polysilicon gate 110 and the dummy gate 115. The side walls are used for protecting the side walls of the polysilicon gate 110 and the dummy gate 115, and are also used for defining a formation region of a subsequent source-drain doped region.

The side wall is made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride, and is of a single-layer structure or a laminated structure.

As an example, the sidewall spacer is a stacked structure, and the sidewall spacer includes a first sidewall on the sidewall of the polysilicon gate 110 and a second sidewall on the sidewall of the first sidewall, where the material of the first sidewall is silicon oxide, and the material of the second sidewall is silicon nitride.

The subsequent steps further comprise: an interlayer dielectric layer is formed on the substrate 100 at the side of the polysilicon gate 110, the dummy gate 115, and the gate mask layer 120.

As shown in fig. 5, in this embodiment, after forming the polysilicon gate 110 in the first region I and the dummy gate 115 in the second region II on the substrate 100, and before forming the interlayer dielectric layer, the method for forming the semiconductor structure further includes: forming source-drain doped regions 130 in the substrate 100 of the first region I on both sides of the polysilicon gate 110 and in the substrate 100 of the second region II on both sides of the dummy gate 115; source and drain silicide layers 135 are formed on top of the source and drain doped regions 130.

When the device is in operation, the source-drain doped region 130 is used for providing stress for a channel, so that the mobility of carriers is improved.

When an NMOS transistor is formed, the source-drain doped region 130 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doped region 130 comprises a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, wherein the P-type ions are B ions, Ga ions or In ions.

The source-drain silicide layer 135 is used to improve the adhesion between the source-drain doped region 130 and the subsequent source-drain contact hole plugs, and to reduce the contact resistance between the source-drain doped region and the source-drain contact hole plugs, thereby facilitating the improvement of the contact performance between the source-drain doped region and the source-drain contact hole plugs.

In this embodiment, the source/drain silicide layer 135 is made of TiSi, NiSi, CoSi, or NiPtSi.

In this embodiment, the source-drain silicide layer 135 is formed by a salicide process. As an example, the step of forming the source drain silicide layer 135 includes: forming a metal layer on the source-drain doped region 135, wherein the metal layer is also located on the isolation structure 105, the side wall of the side wall, and the top and the side wall of the gate mask layer 120; and performing annealing treatment to convert the metal layer in contact with the source/drain doped region 135 and the source/drain doped region 135 with a partial thickness into the source/drain silicide layer 135.

Since the gate mask layer 120 is further formed on the top of the polysilicon gate 110, in the step of forming a metal layer, the metal layer is not formed on the top of the polysilicon gate 110, and accordingly, in the process of performing the annealing process, a metal silicide layer is not formed on the top surface of the polysilicon gate 110.

As shown in fig. 6 and 7, an interlayer dielectric layer 150 is formed on the substrate 100 at the side of the polysilicon gate 110 and the dummy gate 115; the step of forming the interlayer dielectric layer 150 includes: forming an initial dielectric layer 145 on the substrate 100, wherein the initial dielectric layer 145 covers the gate mask layer 120; and removing the initial dielectric layer 145 and the gate mask layer 120 which are higher than the top surfaces of the polysilicon gate 110 and the dummy gate 115 by adopting a planarization process, wherein the rest of the initial dielectric layer 145 is used as the interlayer dielectric layer 150.

In this embodiment, in the process of forming the interlayer dielectric layer 150, a planarization process is used to remove the initial dielectric layer 145 higher than the top surface of the polysilicon gate 110 and the gate mask layer 120, which is beneficial to improving process compatibility and process integration.

Removing the gate mask layer 120 to expose the top surface of the dummy gate 115, so as to prepare for subsequently removing the dummy gate 115; removing the gate mask layer 120 also exposes the top surface of the polysilicon gate 110 in preparation for the subsequent formation of a gate silicide layer on the top surface of the polysilicon gate 110.

In this embodiment, the process for forming the initial dielectric layer 145 includes a deposition process such as a chemical vapor deposition process.

In this embodiment, a planarization process is used, for example: and removing the initial dielectric layer 145 above the top surface of the polysilicon gate 110 and the gate mask layer 120 by a chemical mechanical polishing process. The chemical mechanical polishing process is one of the global surface planarization techniques, and is beneficial to improving the top surface flatness of the interlayer dielectric layer 150 and providing a flat surface for the subsequent process.

In this embodiment, in the step of forming the interlayer dielectric layer 150, the interlayer dielectric layer 150 covers the source/drain silicide layer 135.

It should be noted that, in this embodiment, after the source-drain silicide layer 135 is formed and before the interlayer dielectric layer 150 is formed, the method for forming the semiconductor structure further includes: an etch stop layer 140 is formed to conformally cover the substrate 100, the isolation structures 105, and the sidewalls of the polysilicon gates 110 and the dummy gates 115 and the top surface of the gate mask layer 120.

The etching stop layer 140 is used for defining an etching stop position in a subsequent step of forming a source/drain contact hole, so that damage to a source/drain doped region is reduced.

In this embodiment, the material of the etch stop layer 140 is silicon nitride.

Wherein, in the step of forming the initial dielectric layer 145, the initial dielectric layer 145 covers the etch stop layer 140. Accordingly, in the step of removing the initial dielectric layer 145 and the gate mask layer 120 above the top surfaces of the polysilicon gate 110 and the dummy gate 115, the etch stop layer 140 on the gate mask layer 120 is removed.

As shown in fig. 8, the dummy gate 115 in the second region II is removed, and a gate opening 10 is formed in the interlayer dielectric layer 150 in the second region II.

The gate opening 10 is used to provide space for forming a metal gate in the second region II.

In this embodiment, the dummy gate 115 in the second region II is removed by one or two processes of dry etching and wet etching.

As shown in fig. 9, the metal gate 160 is formed in the gate opening 10.

In this embodiment, the step of forming the metal gate 160 includes: forming a metal gate material layer (not shown) filled in the gate opening 10 and located on the interlayer dielectric layer 150; and removing the metal gate material layer on the interlayer dielectric layer 150 by using a planarization process.

In this embodiment, the process of forming the metal gate material layer includes one or more of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and an electrochemical plating process.

In this embodiment, the planarization process includes a chemical mechanical polishing process. The chemical mechanical polishing process is one of surface global planarization technologies, is beneficial to improving the flatness of the top surfaces of the interlayer dielectric layer 150, the metal gate 160 and the polysilicon gate 110, is beneficial to providing a flat surface for a subsequent protective layer, and is correspondingly beneficial to improving the film quality of the protective layer.

It should be noted that the formation of the polysilicon gate, the metal gate and the interlayer dielectric layer is only an example. However, the steps of forming the polysilicon gate, the metal gate and the interlayer dielectric layer are not limited thereto. For example: in other embodiments, the step of forming the polysilicon gate, the metal gate and the interlayer dielectric layer includes: forming the polysilicon gate positioned in a first region and a dummy gate positioned in a second region on the substrate, wherein gate mask layers are also formed on the tops of the polysilicon gate and the dummy gate; forming the interlayer dielectric layer on the substrate at the side parts of the polysilicon gate and the dummy gate; removing the grid mask layer and the dummy grid in the second area, and forming a grid opening in the interlayer dielectric layer in the second area; forming the metal gate in the gate opening; the step of forming the metal gate comprises: forming a metal gate material layer which is filled in the gate opening and is positioned on the interlayer dielectric layer; and removing the metal gate material layer and the interlayer dielectric layer which are higher than the top surface of the polysilicon gate and the gate mask layer of the first area by adopting a planarization process.

In the process of forming the metal grid, a planarization process is adopted to remove the metal grid material layer and the interlayer dielectric layer which are higher than the top surface of the polycrystalline silicon grid and the grid mask layer of the first area, so that the process compatibility and the process integration degree are improved; and removing the grid mask layer in the first area, thereby exposing the top surface of the polysilicon grid and preparing for forming a grid silicide layer subsequently.

Specifically, the planarization process includes a chemical mechanical polishing process.

Referring to fig. 10 to 11, a protection layer 170 is formed on the interlayer dielectric layer 150 in the second region II to cover the metal gate 160, and the protection layer 170 exposes the polysilicon gate 110.

In the embodiment of the invention, the protective layer 170 covering the metal gate 160 is formed on the interlayer dielectric layer 150 in the second region II, and the protective layer 170 can protect the metal gate 160, so that the probability of damage to the metal gate 160 in a subsequent process is reduced, the influence of a process for forming a gate silicide layer on the metal gate 160 is reduced, and the process compatibility is further improved.

Moreover, in the present embodiment, the protection layer 170 covers the metal gate 160, which is also beneficial to prevent the metal gate 160 from being exposed to the subsequent process environment to generate metal contamination.

In this embodiment, the material of the protection layer 170 is a dielectric material. The material of the protection layer 170 is a dielectric material, which is beneficial to reducing the influence of the formation process of the protection layer 170 on the electrical performance or the insulation performance of the semiconductor structure, and the protection layer 170 can be remained in the semiconductor structure, so that the step of removing the protection layer 170 is omitted, and the process steps are simplified.

The material of the protection layer 170 includes silicon oxide or silicon nitride. As an example, the material of the protection layer 170 is silicon oxide. Silicon oxide is a commonly used dielectric material in a semiconductor process, which is beneficial to improving process compatibility and saving cost, and the interface contact performance between the silicon oxide and other film layers is good, for example: the adhesion between the silicon oxide and other layers is high, the process of forming the protection layer 170 includes a step of patterning, and the adhesion between the silicon oxide and the material (e.g., photoresist) of the patterned mask is high, so that the patterned mask is easy to form, and the difficulty of forming the protection layer 170 is reduced.

In the step of forming the protective layer 170, the thickness of the protective layer 170 is not too small, and is not too large. The subsequent formation of the gate silicide layer on the top surface of the polysilicon gate 110 includes a cleaning process, and if the thickness of the protection layer 170 is too small, the protection layer 170 is easily worn away during the cleaning process, so as to easily reduce the protection effect of the protection layer 170 on the metal gate 160; since the protection layer 170 is retained in the semiconductor structure in this embodiment, if the thickness of the protection layer 170 is too large, the height difference between the top surface of the first region I and the top surface of the second region II is too large, which is likely to affect the subsequent process, for example: the subsequent process comprises the steps of forming source and drain contact holes exposing the source and drain silicide layers 135 in the interlayer dielectric layer and forming a gate contact hole above the polysilicon gate 110, wherein the height difference between the top surface of the film layer of the first area I and the top surface of the film layer of the second area II is too large, so that the accuracy of the processes of forming the source and drain contact holes or the gate contact holes, such as alignment, exposure and the like, is easily influenced, and further, the process compatibility is easily reduced. For this reason, in the present embodiment, in the step of forming the protective layer 170, the thickness of the protective layer 170 is 15nm to 50 nm.

In this embodiment, the step of forming the protection layer 170 includes: forming a protective material layer 165 covering the polysilicon gate 110 and the metal gate 160 on the interlayer dielectric layer 150; the protective material layer 165 in the first region I is removed to form the protective layer 170.

In this embodiment, the protective material layer 165 is formed by a deposition process, and the process temperature of the deposition process is lower than 450 ℃. The lower temperature of the deposition process is beneficial to reduce the influence on the metal gate 160, such as: it is beneficial to reduce the probability of defects generated by the diffusion of the metal gate 160 at high temperature.

Specifically, the process of forming the protective material layer 165 includes a chemical vapor deposition process or a thermal oxidation process.

In this embodiment, the step of removing the protective material layer 165 located in the first region I includes: forming a mask layer 161 on the protective material layer 165 in the second region II; and removing the protective material layer 165 in the first region I by using the mask layer 161 as a mask to form the protective layer 170.

In this embodiment, the material of the mask layer 161 includes photoresist, and the mask layer 161 can be formed by a photolithography process such as photoresist coating, exposure, and development.

In this embodiment, the protective material layer 165 in the first region I is removed by a dry etching process.

After the protective layer 170 is formed, the mask layer 161 is removed. The process of removing the mask layer 161 includes one or both of ashing and wet stripping.

Referring to fig. 12, after forming the protective layer 170, a gate silicide layer 180 is formed on the top surface of the polysilicon gate 110.

By forming the gate silicide layer 180 on the top surface of the polysilicon gate 110 after the metal gate 160 is formed, the gate silicide layer 180 can be formed on the top surface of the polysilicon gate 110, and accordingly, in the subsequent process of forming a gate contact hole plug electrically connected with the polysilicon gate 110, the gate silicide layer 180 is positioned between the gate contact hole plug and the polysilicon gate 110, which is beneficial to increasing the adhesion between the gate contact hole plug and the polysilicon gate 110, reducing the contact resistance between the gate contact hole plug and the polysilicon gate 110, and further improving the performance of the semiconductor structure; in addition, in the embodiment of the present invention, the protective layer 170 covering the metal gate 160 is formed on the interlayer dielectric layer 150 in the second region II, and the protective layer 170 can protect the metal gate 160, which is beneficial to reducing the probability of damage to the metal gate 160 and reducing the influence of the process of forming the gate silicide layer 180 on the metal gate 160.

The material of the gate silicide layer 180 includes TiSi, NiSi, CoSi, or NiPtSi. In this embodiment, the material of the gate silicide layer 180 is NiPtSi. Since the RTA process temperature of the NiPt-saictide process is low, the influence on the metal gate 160 can be further reduced by selecting the NiPtSi material as the material of the gate silicide layer 180.

As an example, the step of forming the gate silicide layer 180 includes: forming a metal layer (not shown) covering the protection layer 170, the polysilicon gate 110 and the interlayer dielectric layer 150 in the first region I; forming a capping layer (not shown) on the metal layer; after the formation of the capping layer, annealing is performed to convert the metal layer in contact with the polysilicon gate 110 and the polysilicon gate 110 having a partial thickness into the gate silicide layer 180; and removing the covering layer and the metal layer on the protective layer 170 and the interlayer dielectric layer 150.

The material of the metal layer comprises Ti, Ni, Co or NiPt. In this embodiment, the metal layer is made of NiPt.

In this embodiment, the metal layer is formed by a Physical Vapor Deposition (PVD) process.

The covering layer is located on the metal layer and used for protecting the metal layer. The covering layer is also used for preventing the metal layer from flowing in the annealing process to cause the problems of low thickness uniformity and local non-uniform resistance value of the gate silicide layer.

In this embodiment, the material of the capping layer includes TiN.

In this embodiment, the capping layer is formed by a physical vapor deposition process.

In this embodiment, in order to reduce the influence of the process of forming the gate silicide layer on the metal gate 160, the annealing temperature of the annealing process is lower, for example: the annealing temperature of the annealing treatment is lower than 450 ℃.

Meanwhile, the annealing time of the annealing treatment is not too long, and in the embodiment, the annealing time is 20S (seconds) to 80S.

In this embodiment, the annealing process includes a Dynamic Surface Annealing (DSA) process, a rapid thermal annealing process, or a laser annealing process.

In this embodiment, since the metal layer does not react with the protection layer 170 or the interlayer dielectric layer 150, after the annealing process, the capping layer and the metal layer on the protection layer 170 and the interlayer dielectric layer 150 can be selectively removed, thereby being beneficial to preventing the problem of short circuit caused by bridging of the capping layer and the metal layer.

Specifically, in this embodiment, a wet etching process is used to remove the capping layer and the metal layer on the protective layer 170 and the interlayer dielectric layer 150.

In this embodiment, the step of forming the gate silicide layer 180 further includes: before the metal layer is formed, a cleaning process is performed on the top surface of the polysilicon gate 110.

By cleaning the top surface of the polysilicon gate 110, the natural oxide layer on the top surface of the polysilicon gate 110 is removed, so that the subsequent metal layer can be in contact with the clean surface of the polysilicon gate 110, a gate silicide layer is easier to form, and the formation quality of the gate silicide layer is improved.

In this embodiment, a wet etching process is used to clean the top surface of the polysilicon gate 110. In particular, NH is used successively₄The OH and HF solutions perform a cleaning process on the top surface of the polysilicon gate 110.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 12, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100 including a first region I for forming a first device and a second region II for forming a second device, an operating voltage of the first device being greater than an operating voltage of the second device; a polysilicon gate 110 on the substrate 100 in the first region I; a metal gate 160 located on the substrate 100 in the second region II; an interlayer dielectric layer 150 on the substrate 100 at the side of the polysilicon gate 110 and the metal gate 160; the protective layer 170 is positioned on the interlayer dielectric layer 150 in the second region I and covers the metal gate 160, and the protective layer 170 exposes the polysilicon gate 110; a gate silicide layer 180 is located on the top surface of the polysilicon gate 110.

In this embodiment, the top surface of the polysilicon gate 110 is further provided with a gate silicide layer 180, and accordingly, in the process of subsequently forming a gate contact hole plug electrically connected to the polysilicon gate 110, the gate silicide layer 180 is located between the gate contact hole plug and the polysilicon gate 110, which is beneficial to increasing the adhesion between the gate contact hole plug and the polysilicon gate 110, and reducing the contact resistance between the gate contact hole plug and the polysilicon gate 110, thereby being beneficial to improving the performance of the semiconductor structure; in addition, in the embodiment of the present invention, by disposing the protection layer 170 on the interlayer dielectric layer 150 in the second region II and covering the metal gate 160, the protection layer 170 can protect the metal gate 160, which is beneficial to reducing the probability of damage to the metal gate 160 and reducing the influence of the process of forming the gate silicide layer 180 on the metal gate 160.

The substrate 100 is used to provide a process platform for forming a semiconductor structure.

In this embodiment, the first region I is used to form a first device, the second region II is used to form a second device, and an operating voltage of the first device is greater than an operating voltage of the second device.

Specifically, in this embodiment, the first device is a logic device, and the second device is a medium voltage device or a high voltage device. Logic devices typically operate at a lower voltage and higher frequency, while medium or high voltage devices typically have higher withstand voltage capabilities, and the medium or high voltage devices operate at a higher voltage than the logic devices. In this embodiment, the operating voltage of the medium-voltage device or the high-voltage device is at least 3V. The medium-voltage device generally refers to a device with an operating voltage of 3V to 10V, and the high-voltage device refers to a device with an operating voltage of more than 10V.

As an example, the second region II includes an NMOS region (not labeled) and a PMOS region (not labeled).

In this embodiment, the substrate 100 is a planar substrate.

In this embodiment, the base 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other materials.

In this embodiment, a trench (not shown) is further formed in the substrate 100, and an isolation structure 105 is formed in the trench. The trenches provide spatial locations for forming isolation structures 105.

In this embodiment, the substrate 100 is etched to form the trench, so as to define an Active Area (Active Area) and an isolation Area on the substrate 100. Specifically, a plurality of isolated trenches are formed in the substrate 100, and the substrate 100 isolated by the trenches is used as an active region.

Isolation structures 105 are used to isolate adjacent devices.

In this embodiment, the isolation structure 105 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxynitride.

The operating voltage of the first device is greater than that of the second device, the first device is generally a device with higher withstand voltage capability, and the second device is generally a device with lower operating voltage. For example: the first device is a medium-voltage or high-voltage device, the second device is a logic device, the working frequency of the second device is greater than that of the first device, and the performance requirement of the second device is higher than that of the first device. Therefore, by forming the polysilicon gate 110 in the first region I and forming the metal gate 160 in the second region II, the working voltage of the first device is increased, the process cost is reduced, the second device has a lower working voltage, and the performance of the second device meets the design requirement.

The polysilicon gate 110 and the metal gate 160 are device gates, and when the device works, the polysilicon gate 110 is used for controlling the conduction channel of the first device to be turned on or turned off, and the metal gate 160 is used for controlling the conduction channel of the second device to be turned on or turned off.

The material of the polysilicon gate 110 is polysilicon.

The metal gate includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.

The high-k gate dielectric layer is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO₂. In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO₂HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al₂O₃And the like.

The work function layer is used to adjust the threshold voltage of the formed transistor. When forming PMOS, the work function layer is P-type work function layer, and the material of P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. When forming NMOS, the work function layer is N-type work function layer, and the material of P-type work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAl C.

The gate electrode layer is used to electrically connect the metal gate 160 to external circuitry or other interconnect structures. In this embodiment, the gate electrode layer is made of Al. In other embodiments, the material of the gate electrode layer may also be W, Cu, Ag, Au, Pt, Ni, or Ti.

In this embodiment, the semiconductor structure further includes: and the gate oxide layer 101 is positioned between the polysilicon gate 110 and the substrate 100 and between the metal gate 160 and the substrate 100.

The gate oxide layer 101 is used for isolating the polysilicon gate 110 from the substrate 100 and isolating the metal gate 160 from the substrate 100. The material of the gate oxide layer 101 comprises silicon oxide or silicon oxynitride.

In order to improve the reliability of the first device (for example, increase the breakdown voltage), in this embodiment, the thickness of the gate oxide layer 101 in the first region I is greater than that of the gate oxide layer 101 in the second region II.

In this embodiment, the semiconductor structure further includes: and spacers (not shown) on sidewalls of the polysilicon gate 110 and the metal gate 160. The side walls are used for protecting the side walls of the polysilicon gate 110 and the metal gate 160, and are also used for defining the formation region of the source-drain doped region.

As an example, the sidewall spacer is a stacked structure, and the sidewall spacer includes a first sidewall on the sidewall of the polysilicon gate 110 and a second sidewall on the sidewall of the first sidewall, where the material of the first sidewall is silicon oxide, and the material of the second sidewall is silicon nitride.

In this embodiment, the semiconductor structure further includes: the source-drain doped region 130 is located in the substrate 100 of the first region I on both sides of the polysilicon gate 110 and in the substrate 100 of the second region II on both sides of the metal gate 160; and a source/drain silicide layer 135 on the top surface of the source/drain doped region 130.

When the device is in operation, the source-drain doped region 130 is used for providing stress for a channel, so that the mobility of carriers is improved.

When an NMOS transistor is formed, the source-drain doped region 130 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doped region 130 comprises a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, wherein the P-type ions are B ions, Ga ions or In ions.

The source-drain silicide layer 135 is used to improve the adhesion between the source-drain doped region 130 and the subsequent source-drain contact hole plugs, and reduce the contact resistance between the source-drain doped region 130 and the source-drain contact hole plugs, thereby facilitating the improvement of the contact performance between the source-drain doped region 130 and the source-drain contact hole plugs.

In this embodiment, the source/drain silicide layer 135 is made of TiSi, NiSi, CoSi, or NiPtSi.

An interlevel dielectric layer 150 isolates adjacent devices. The interlayer dielectric layer 150 covers the source-drain silicide layer 135.

The material of the interlayer dielectric layer 150 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 150 is made of silicon oxide.

In this embodiment, the semiconductor structure further includes: and the etching stop layer 140 is positioned between the isolation structure 105 and the interlayer dielectric layer 150, between the source-drain silicide layer 135 and the interlayer dielectric layer 150, between the sidewall of the polysilicon gate 110 and the interlayer dielectric layer 150, and between the sidewall of the metal gate 160 and the interlayer dielectric layer 150.

The etching stop layer 140 is used for defining an etching stop position in a subsequent step of forming a source/drain contact hole, so that damage to the source/drain doped region 130 is reduced.

In this embodiment, the material of the etch stop layer 140 is silicon nitride.

In the embodiment of the invention, the protective layer 170 is arranged on the interlayer dielectric layer 150 in the second region II and covers the metal gate 160, and the protective layer 170 can protect the metal gate 160, so that the probability of damage to the metal gate 160 is reduced, the influence of the process for forming the gate silicide layer 180 on the metal gate 160 is reduced, and the process compatibility is improved.

Moreover, in the present embodiment, the protection layer 170 covers the metal gate 160, which is also beneficial to prevent the metal gate 160 from being exposed to the process environment to generate the metal contamination problem.

In this embodiment, the material of the protection layer 170 is a dielectric material. The material of the protection layer 170 is a dielectric material, which is beneficial to reducing the influence of the formation process of the protection layer 170 on the electrical performance or the insulation performance of the semiconductor structure, and the protection layer 170 can be remained in the semiconductor structure, so that the step of removing the protection layer 170 is omitted, and the process steps are simplified.

The material of the protection layer 170 includes silicon oxide or silicon nitride. As an example, the material of the protection layer 170 is silicon oxide. The silicon oxide is a commonly used dielectric material in a semiconductor process, which is beneficial to improving process compatibility and saving cost, and the interface contact performance between the silicon oxide and other film layers is good, for example: the adhesion between the silicon oxide and other layers is high, the process of forming the protection layer 170 includes a step of patterning, and the adhesion between the silicon oxide and the material (e.g., photoresist) of the patterned mask is high, so that the patterned mask is easy to form, and the difficulty of forming the protection layer 170 is reduced.

It should be noted that the thickness of the protective layer 170 is not too small, and is not too large. The subsequent formation of the gate silicide layer 180 on the top surface of the polysilicon gate 110 includes a cleaning process, and if the thickness of the protection layer 170 is too small, the protection layer 170 is easily worn away during the cleaning process, so as to easily reduce the protection effect of the protection layer 170 on the metal gate 160; since the protection layer 170 is retained in the semiconductor structure in this embodiment, if the thickness of the protection layer 170 is too large, the height difference between the top surface of the first region I and the top surface of the second region II is too large, which is likely to affect the subsequent process, for example: the subsequent processes include forming source and drain contact holes exposing the source and drain silicide layer 135 in the interlayer dielectric layer 150 and forming a gate contact hole above the polysilicon gate 110, and the height difference between the top surface of the film layer of the first region I and the top surface of the film layer of the second region II is too large, so that the accuracy of the processes of forming the source and drain contact holes or the gate contact holes, such as alignment, exposure and the like, is easily influenced, and further, the process compatibility is easily reduced. For this reason, in the present embodiment, the thickness of the protective layer 170 is 15nm to 50 nm.

The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.