阅读说明：本技术 高速存储器系统集成 (High speed memory system integration ) 是由 S·富岛 D·马利克 A·科克 于 2020-12-21 设计创作，主要内容包括：本文公开的实施例包括多管芯电子封装。在实施例中,电子封装包括封装衬底和电耦合到封装衬底的第一管芯。在实施例中,管芯堆叠体阵列电耦合到第一管芯。在实施例中,管芯堆叠体阵列在第一管芯与封装衬底之间。在实施例中,管芯堆叠体中的各个管芯堆叠体包括布置在垂直堆叠体中的多个第二管芯。(Embodiments disclosed herein include multi-die electronic packages. In an embodiment, an electronic package includes a package substrate and a first die electrically coupled to the package substrate. In an embodiment, the array of die stacks is electrically coupled to the first die. In an embodiment, the array of die stacks is between the first die and the package substrate. In an embodiment, each of the die stacks includes a plurality of second dies arranged in a vertical stack.)

1. An electronic package, comprising:

a package substrate;

a first die electrically coupled to the package substrate; and

an array of die stacks electrically coupled to the first die, wherein the array of die stacks is between the first die and the package substrate, and wherein each of the die stacks comprises:

a plurality of second dies disposed in the vertical stack.

2. The electronic package of claim 1, wherein the first die is a compute die, and wherein the second die is a memory die.

3. The electronic package of claim 1 or 2, further comprising:

a base substrate.

4. The electronic package of claim 3, wherein the base substrate is between the array of die stacks and the package substrate.

5. The electronic package of claim 3, wherein the base substrate is between the array of die stacks and the first die.

6. The electronic package of claim 3, wherein the first die is between the base substrate and the package substrate.

7. The electronic package of claim 3, wherein the base die is a passive substrate.

8. The electronic package of claim 3, wherein the base die is an active substrate.

9. The electronic package of claim 8, wherein the base die comprises circuitry for power transfer.

10. The electronic package of claim 1 or 2, wherein a power transfer path from the package substrate to the first die passes through one or more of the second dies.

11. The electronic package of claim 1 or 2, wherein a power transfer path from the package substrate to the first die passes between die stacks.

12. The electronic package of claim 1 or 2, further comprising:

a third die, wherein a first portion of the array of die stacks is under the first die, and wherein a second portion of the array of die stacks is under the third die.

13. An electronic package, comprising:

a package substrate;

a base substrate over the package substrate;

an array of die stacks over the base substrate; and

a first die over the array of die stacks.

14. The electronic package of claim 13, wherein the first die comprises a plurality of compute engine clusters, and wherein an individual one of the die stacks is positioned below an individual one of the compute engine clusters.

15. The electronic package of claim 14, wherein a single die stack comprises a plurality of second dies, and wherein each second die comprises a plurality of memory blocks.

16. The electronic package of claim 15, wherein each compute engine cluster includes a plurality of local compute engines, and wherein respective ones of the local compute engines are above respective ones of the memory blocks.

17. The electronic package of claim 13, 14, 15, or 16, wherein a power transfer path from the package substrate to the first die passes through the plurality of die stacks.

18. The electronic package of claim 13, 14, 15 or 16, wherein a power transfer path from the package substrate to the first die passes between die stacks.

19. The electronic package of claim 13, 14, 15 or 16, further comprising:

a third die, wherein a first portion of the array of die stacks is under the first die, and wherein a second portion of the array of die stacks is under the third die.

20. The electronic package of claim 13, 14, 15, or 16, wherein the array of die stacks comprises a four by four array of die stacks.

21. The electronic package of claim 13, 14, 15 or 16, wherein a single die stack comprises two or more second dies arranged in a vertical stack.

22. The electronic package of claim 21, wherein the first die is a compute die, and wherein the second die is a memory die.

23. An electronic system, comprising:

a plate;

a package substrate attached to the board;

a first die electrically coupled to the package substrate; and

an array of die stacks electrically coupled to the first die, wherein each of the die stacks comprises:

a plurality of second dies disposed in the vertical stack.

24. The electronic system of claim 23, further comprising:

a base substrate, wherein the base substrate is between the package substrate and the array of die stacks, between the array of die stacks and the first die, or over the first die.

25. The electronic system of claim 23 or 24, wherein a power transfer path from the package substrate to the first die passes between or through the die stacks.

Technical Field

Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to electronic packages having a compute die over an array of memory die stacks.

Background

The drive towards increasing computational performance has produced many different packaging solutions. In one such packaging solution, a die is disposed over a base substrate. The die may include a compute die and a memory die. Connections between the compute die and the memory die are provided in the base substrate. Although providing higher density, the lateral connections over the base substrate result in higher power consumption and reduced bandwidth. Such integration may not be sufficient to meet the memory capacity and bandwidth requirements of certain applications, such as High Performance Computing (HPC) applications.

Drawings

FIG. 1A is a plan view of an electronic package having a plurality of compute dies and a memory die over a base substrate.

Fig. 1B is a cross-sectional view of the electronic package of fig. 1A.

Fig. 2 is a perspective view of an electronic package including a first die and an array of die stacks under the first die according to an embodiment.

Fig. 3A is a cross-sectional view of an electronic package having a first die and an array of die stacks attached to a package substrate, according to an embodiment.

Fig. 3B is a cross-sectional view of an electronic package having a first die and an array of die stacks attached to a base substrate, according to an embodiment.

Fig. 3C is a cross-sectional view of an electronic package having a first die above a base substrate and an array of die stacks below the base substrate according to an embodiment.

Fig. 3D is a cross-sectional view of an electronic package having a first die over an array of die stacks, having a base substrate over the first die, according to an embodiment.

Fig. 3E is a cross-sectional view of an electronic package having a first die over an array of die stacks, having the first die directly connected to a package substrate, according to an embodiment.

Fig. 3F is a cross-sectional view of an electronic package having a first die over an array of die stacks, having the first die directly connected to a base substrate, according to an embodiment.

Fig. 3G is a cross-sectional view of an electronic package having a plurality of first dies over an array of die stacks with direct electrical connections from the first dies to a base substrate, according to an embodiment.

Fig. 3H is a cross-sectional view of an electronic package having a plurality of first dies over an array of die stacks with direct electrical connections from the first dies to a package substrate, according to an embodiment.

Fig. 3I is a cross-sectional view of an electronic package having a plurality of first dies over an array of die stacks, with power transfer paths through the die stacks from a base substrate to the first dies, according to an embodiment.

Fig. 4A is a plan view of a first die having power transfer pads in a grid and I/O pads within each compute engine cluster, according to an embodiment.

Fig. 4B is a plan view of a memory die that may be used in conjunction with the first die in fig. 4A, according to an embodiment.

Fig. 5A is a plan view of a first die having power transfer pads and I/O pads within each compute engine cluster according to an embodiment.

Fig. 5B is a plan view of a memory die that may be used in conjunction with the first die in fig. 5A, according to an embodiment.

Fig. 6 is a cross-sectional view of an electronic system having an electronic package including a first die over an array of die stacks according to an embodiment.

FIG. 7 is a schematic diagram of a computing device constructed according to an embodiment.

Detailed Description

Described herein are electronic packages having a compute die over an array of memory die stacks according to various embodiments. In the following description, various aspects of the illustrative embodiments will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. It will be apparent, however, to one skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As described above, existing electronic packaging architectures may not provide sufficient memory capacity and bandwidth for some High Performance Computing (HPC) systems. An example of one such prior art electronic package 100 is shown in fig. 1A and 1B. As shown, the electronic package 100 includes a package substrate 110 with a base substrate 120 over the package substrate 110. The base substrate 120 may be an active substrate. For example, base substrate 120 may include circuitry for memory (e.g., SRAM), I/O, and power management (e.g., Fully Integrated Voltage Regulator (FIVR)). The integration of these circuit components into the base substrate 120 requires relatively advanced process nodes (e.g., 10nm or less or greater). Since the area of the base substrate 120 is required to be relatively large (e.g., several hundred mm)²) This is further complicated. As such, the yield of such base substrate 120 is low, which drives up the cost of the base substrate 120. The base substrate 120 may be attached to the package substrate 110 by interconnects 112.

As shown, a plurality of first die 125 and second die 135 may be arranged in an array over base substrate 120. The first die 125 may be a compute die (e.g., CPU, GPU, etc.), and the second die 135 may be a memory die. First die 125 and second die 135 may be attached to base substrate 120 through interconnects 122. It should be understood that the number of second die 135 is limited by the footprint of base substrate 120. The number of second dies 135 is limited due to the difficulty in forming a large area base substrate 120. As such, the memory capacity of the electronic package 100 is limited. To provide additional memory, a High Bandwidth Memory (HBM)145 stack may be attached to the package substrate 110. HBM 145 may be electrically coupled to base substrate 120 through embedded bridge 144 or other conductive wiring architecture.

First die 125 may be electrically coupled to second die 135 through interconnects 136 (e.g., traces, vias, etc.) in base substrate 120. Similarly, an interconnect 146 through bridge 144 may electrically couple HBM 145 to base substrate 120. Such lateral routing increases power consumption and reduces the available bandwidth of the memory.

Accordingly, embodiments disclosed herein include an electronic packaging architecture that allows for improved memory capacity and bandwidth. In particular, embodiments disclosed herein include a first die (e.g., a computing die) and an array of die stacks including a second die (e.g., a memory die) coupled to the first die. The three-dimensional (3D) stacking of the second die allows for increased memory capacity within a limited footprint. In addition, each die stack may be located below the compute engine cluster of the first die. In some embodiments, the local compute engines within the cluster may be above the memory blocks of the respective ones of the second dies. Thus, each compute engine cluster has direct access to memory with minimal lateral routing. This reduces power consumption and provides an increase in bandwidth. In some embodiments, a power transfer path from the package substrate (or base substrate) to the first die may be routed between the die stacks. In other embodiments, the power transfer path may be routed through the die stack.

The additional memory capacity also allows memory to be offloaded from the base substrate. The processing node of the base substrate can be relaxed without the need to provide memory in the base substrate. For example, the base substrate may be processed at a 14nm or 22nm process node. Thus, the yield of the base substrate is improved and the cost is reduced. In addition, a larger area of the base substrate may be provided, which allows for even more memory capacity.

In an embodiment, a plurality of first dies may be included in an electronic package. For example, each first die may be positioned over a different portion of the array of die stacks. Thus, each first die may have a dedicated memory bank (bank). This allows for smaller computational dies and can therefore drive higher yields and lower costs. The use of a die stack may also improve the yield of electronic packages. For example, each die stack may be tested prior to assembly. In this way, only known good die stacks may be included in an electronic package.

Referring now to fig. 2, a perspective view of an electronic package 200 is shown, according to an embodiment. In fig. 2, only the first die 225 and the array of die stacks 230 are shown for simplicity. It should be understood that other components (as will be described in greater detail below) may be included in the electronic package 200. In an embodiment, the first die 225 may be a computing die. For example, first die 225 may include a processor (e.g., CPU), a graphics processor (e.g., GPU), an application processor (e.g., TPU, FPGA, etc.), or any other type of die that provides computing power. In an embodiment, the die stack 230 may include a plurality of second dies 235 arranged in a vertical stack. The second die 235 may be a memory die. In a particular embodiment, the memory die is SRAM memory, but other types of memory (e.g., eDRAM, STT-MRAM, ReRAM, 3DXP, etc.) may also be included in the die stack 230. In addition, the second die 235 may include a plurality of different types of memory.

In the illustrated embodiment, the array of die stacks 230 includes a four by four array. That is, there are 16 instances of the die stack 230 shown in fig. 2. However, it should be understood that the array may include any number of die stacks 230. Further, while a square array is shown, it should be understood that the array may be any shape. For example, the array of die stacks 230 may be a four by two array. In the embodiment shown, each die stack 230 includes four second dies 235. However, it should be understood that embodiments may include any number of second dies 235 in the die stack 230. For example, one or more second dies 235 may be included in each die stack 230.

Referring now to fig. 3A, a cross-sectional view of an electronic package 300 is shown, according to an embodiment. The electronic package 300 may include a package substrate 310, an array of die stacks 330, and a first die 325. A mold layer 350 may be disposed over the array of die stacks 330 and the first die 325.

In an embodiment, the package substrate 310 may be any suitable package substrate. For example, the package substrate 310 may be cored or coreless. In an embodiment, the package substrate 310 may include conductive features (not shown for simplicity) to provide routing. For example, conductive traces, via pads, and the like may be included in the package substrate.

In an embodiment, each die stack 330 may include a plurality of second dies 335. In the illustrated embodiment, five second dies 335 are shown in each die stack 330, but it should be understood that the die stack 330 may include two or more second dies 335. In an embodiment, the second dies 335 may be connected to each other by interconnects 337/338. Interconnect 338 represents a power supply interconnect, and interconnect 337 may represent a communication interconnect (e.g., I/O, CA, etc.). In an embodiment, a Through Substrate Via (TSV) may pass through the second die 335. For simplicity, the TSVs are not shown. In a particular embodiment, the interconnects 337/338 are implemented using a TSV/microbump architecture. In other embodiments, hybrid wafer bonding may be used to interconnect the stacked second die. However, it should be understood that other suitable interconnect architectures may also be used. As shown, a power transfer path is provided through the die stack 330 from the package substrate 310 to the first die 325. That is, the power interconnect 338 is shown coupling the topmost second die 335 to the first die 325.

In an embodiment, the first die 325 may be a computing die. For example, the first die 325 may include a processor (e.g., a CPU), a graphics processor (e.g., a GPU), or any other type of die that provides computing power. The second die 335 may be a memory die. In a particular embodiment, the memory die is SRAM memory, but other types of memory (e.g., eDRAM, STT-MRAM, ReRAM, 3DXP, etc.) may also be included in the die stack 330. In an embodiment, the first die 325 may be manufactured at a different process node than the second die 335. For example, the first die 325 may be fabricated with a more advanced process node than the second die 335.

In an embodiment, the die stack 330 integrated into the electronic package 300 may be a known good die stack 330. That is, individual die stacks 330 may be tested prior to assembly. As such, embodiments may include providing only a functional die stack 330 in the assembly of the electronic package 330. This provides an increase in the yield of the electronic package 300 and reduces costs.

Referring now to fig. 3B, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. The electronic package 300 in fig. 3B may be substantially similar to the electronic package 300 in fig. 3A, except that a base substrate 320 is provided between the array of die stacks 330 and the package substrate 310. In an embodiment, the base substrate 320 may be attached to the package substrate 310 by interconnects 312, such as solder bumps or the like.

In an embodiment, the base substrate 320 may be a semiconductor material. For example, the base substrate 320 may include silicon or the like. In an embodiment, the base substrate 320 may be a passive substrate without any active circuitry. In other embodiments, the base substrate 320 may be an active substrate including active circuitry. In an embodiment, base substrate 320 may include power conditioning circuit blocks (e.g., FIVR, etc.). Further, in some embodiments, base substrate 320 may be substantially free of memory circuitry (e.g., SRAM blocks). This is because the die stack 330 provides sufficient memory capacity for the electronic package 300.

In some embodiments, the base substrate 320 may be fabricated at a different process node than the process node of the first die 325 and the second die 335 in the die stack 330. For example, the first die 325 may be fabricated at a 7nm process node, the second die 335 may be fabricated at a 10nm process node, and the base substrate 320 may be fabricated at a 14nm process node or greater. In this way, the cost of the base substrate 320 is reduced. In addition, the footprint of the base substrate 320 may be increased to provide more area for the die stack 330. In an embodiment, the footprint of base substrate 320 may be greater than the footprint of the array of die stacks 330 and greater than the footprint of first die 325. In an embodiment, the footprint of the base substrate 320 may be approximately 100mm²Or greater, about 200mm²Or greater, or about 500mm²Or larger.

Referring now to fig. 3C, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. The electronic package 300 in fig. 3C is substantially similar to the electronic package 300 in fig. 3B, except for the location of the base substrate 320. As shown, the base substrate 320 may be positioned between the die stack 330 and the first die 325. In some embodiments, a direct electrical connection 313 may be provided from the base substrate 320 to the package substrate 310. That is, the electrical connections 313 from the base substrate 320 to the package substrate 310 may pass adjacent to the die stack 330. However, it should be understood that embodiments may also include electrical connections through the die stack 330 from the base substrate 320 to the package substrate 310.

Referring now to fig. 3D, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. In an embodiment, the electronic package 300 in fig. 3D is substantially similar to the electronic package 300 in fig. 3B, except for the location of the base substrate 320. As shown, the base substrate 320 may be positioned over the first die 325. In some embodiments, a direct electrical connection 313 may be provided from the base substrate 320 to the package substrate 310. That is, the electrical connections 313 from the base substrate 320 to the package substrate 310 may pass adjacent to the die stack 330 and the first die 325. However, it should be understood that embodiments may also include electrical connections through the die stack 330 from the base substrate 320 to the package substrate 310.

Referring now to fig. 3E, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. In an embodiment, the electronic package 300 in fig. 3E may be substantially similar to the electronic package 300 in fig. 3A, except that the power transfer path 326 from the package substrate 310 to the first die 325 may pass outside the die stack 330. As shown, power transfer paths 326 are positioned between die stacks 330. In embodiments, power transfer path 326 may include Through Mold Vias (TMVs), copper pillars, or any other suitable interconnect architecture for providing vertical connections through mold layer 350.

Since the power transfer path to the first die 325 is not provided through the die stack 330, the topmost second die 335 may only include communication interconnects 337. However, in other embodiments, dummy power interconnects (i.e., interconnects that provide structural support but are not an active portion of the circuit) may be provided over the topmost second die 335 to provide manufacturing and mechanical reliability. It should be understood that the power transfer path through the die stack 330 may be made with the interconnects 338.

Referring now to fig. 3F, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. In an embodiment, the electronic package in fig. 3F is substantially similar to the electronic package 300 in fig. 3E, except that a base substrate 320 is provided between the die stack 330 and the package substrate 310. In an embodiment, the base substrate 320 may be attached to the package substrate 310 by interconnects 312, such as solder bumps or the like. In an embodiment, the power transfer path 326 may provide a direct electrical coupling between the first die 325 and the base substrate 320.

Referring now to fig. 3G, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. In an embodiment, the electronic package 300 in fig. 3G is substantially similar to the electronic package 300 in fig. 3F, except that a plurality of first dies 325 are provided over the array of die stacks 330. For example, a first die 325 is shown_AAnd a first die 325_B. However, it should be understood that any number of first dies 325 may be included in the electronic package 300. In some embodiments, the first die 325_AAnd 325_BMay be substantially similar to each other. In other embodiments, the first die 325_AAnd 325_BMay have different functions. Further, although shown as substantially the same size in fig. 3G, it is understood that the first die 325_AAnd 325_BNeed not be of the same size. In the embodiment shown, the first die 325_AAnd 325_BOver a different die stack 330. In other embodiments, a single die stack 330 may underlie two or more different first dies 325.

In an embodiment, the first die 325_AAnd 325_BEach of which may be directly connected to the underlying base substrate 320. For example, the power transfer path 326 passes through a mold layer 350 outside the die stack 330 between the first die 325 and the base substrate 320. The power transfer path 326 may be a TMV, a post, or any other conductive structure for providing a vertical connection through the mold layer 350. Due to the power transmission path 326Not provided through the die stack 330, the topmost second die 335 may only include communication interconnects 337. However, in other embodiments, dummy power interconnects (i.e., interconnects that provide structural support but are not an active portion of the circuit) may be provided over the topmost second die 335 to provide manufacturing and mechanical reliability.

Referring now to fig. 3H, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. The electronic package 300 in fig. 3H may be substantially similar to the electronic package 300 in fig. 3G, except that the base substrate 320 is omitted. In such embodiments, the die stack 330 may be directly attached to the package substrate 310. Additionally, a power transfer path 326 may be provided from the first die 325_A/325_BDirect electrical connection to the package substrate 310.

Referring now to fig. 3I, a cross-sectional view of an electronic package 300 is shown, in accordance with additional embodiments. The electronic package 300 in fig. 3I may be substantially similar to the electronic package 300 in fig. 3G, except that the power transfer path 326 outside of the die stack 330 is omitted. Instead, it may be provided through the die stack 330 to the first die 325_A/325_BThe power transfer of (2). For example, the topmost second die 335 may be connected to the first die 325 through the communication interconnect 337 and the power interconnect 338_A/325_B。

Referring now to fig. 4A, a plan view of first die 425 is shown, according to an embodiment. In an embodiment, the first die 425 may include a plurality of compute engine clusters 462. A plurality of local compute engines 461 may be provided within each of the clusters 462. To minimize routing, memory resources dedicated to each cluster 462 are provided below the clusters 462. As such, each cluster 462 may be located above one of the die stacks. For example, the first die 425 includes sixteen clusters 462, and each of the clusters 462 may be positioned over one of the die stacks. Accordingly, embodiments disclosed herein require minimal, if any, lateral routing in order for first die 425 to access memory resources in the electronic package.

By singulating the memory diesMemory blocks are positioned below local compute engines 461 to further reduce lateral routing. For example, fig. 4B is a plan view of a second die 435 (e.g., a memory die) in a die stack that may be provided below the first die 425. In an embodiment, the second die 435 may include a plurality of blocks 471_A-D. Block 471_A-DEach of which may be located below a single one of the local compute engines 461. For example, each second die 435 may include four blocks 471, and the cluster 462 above may include four local compute engines 461, with a single one of the local compute engines 461 being above a single one of the blocks 471.

Fig. 4B also shows pads 472/473 and interconnects 437/438. A power transfer interconnect 438 may be provided on pad 472 and a communication interconnect 437 may be provided on pad 473. In the example of the topmost second die 435 in the die stack, the power transfer interconnect 438 may be omitted, or a dummy power transfer interconnect 438 may be provided. This is because the power transfer pads 464 on the first die 425 are outside the footprint of the die stack. As such, a power transfer path similar to power transfer path 326 shown in fig. 3E and 3F may be used to provide power to first die 425.

In an embodiment, a communication pad 463 may be provided within each cluster 462 of the first die 425. Communication pads 463 are positioned to interface with communication interconnects 437 of the second die 437. Although a simple linear layout of the communication interconnect 437 is shown, it should be understood that the communication interconnect 437 can have any suitable layout.

Referring now to fig. 5A and 5B, plan views of a surface of a first die 525 and a surface of a second die 535, respectively, are shown, according to an embodiment. The second die 535 may be substantially similar to the second die 435 in fig. 4B. That is, the second die 535 may include a plurality of blocks 571_A-DWith power transfer interconnects 538 provided on pads 572 and communication interconnects 537 provided on pads 573.

In an embodiment, the first die 525 in fig. 5A is similar to the first die 425 in fig. 4A except that the power transfer pad 564 is within the compute engine cluster 562. That is, the first die 525 is disposed through the die stack to receive power, similar to the embodiment shown in fig. 3A and 3B. Since power is transferred through the die-stack, the power transfer interconnect 538 on the topmost second die 535 is active to provide power to the power transfer pads 564 within each of the clusters 563.

Similar to the embodiments described with respect to fig. 4A and 4B, clusters 563 may each include a plurality of local compute engines 561. Each of the local compute engines 561 may be positioned above one of the blocks 571 in the second die 535 below. In addition, the pads 572/573 of the second die 535 may be aligned with the pads 564/563 of the first die 525. Although a cross pattern is shown, it should be understood that pads 572/573 and 564/563 may have any suitable layout.

Referring now to fig. 6, a cross-sectional view of an electronic system 690 is shown, according to an embodiment. In an embodiment, electronic system 690 may include electronic package 600 attached to board 691. The electronic package 600 may be attached to the board 691 by interconnects 692. In the illustrated embodiment, the interconnects 692 are shown as solder balls. However, it should be understood that interconnect 692 may be any suitable interconnect, such as a socket, a wire bond, and the like.

In an embodiment, the electronic package 600 may include a package substrate 610. The base substrate 620 may be disposed over the package substrate 610. In an embodiment, an array of die stacks 630 may be positioned over a base substrate 620. The die stacks 630 may each include a plurality of second dies 635. For example, the second die 635 may be a memory die. A first die 625 may be disposed above the die stack body 630. The first die 625 may be a compute die. In an embodiment, power may be provided to the first die 625 through a power transfer path 626 directly connected to the base substrate 620. In an embodiment, the mold layer 650 may surround the electronic package 600.

In fig. 6, an electronic package 600 is similar to the electronic package 300 shown in fig. 3F. However, it should be understood that electronic package 600 in electronic system 690 may be similar to an electronic package according to any embodiment disclosed herein. For example, the electronic package 600 may be similar to any of the electronic packages 300 in fig. 3A-5B.

FIG. 7 illustrates a computing device 700 according to an embodiment of the invention. The computing device 700 houses a board 702. The board 702 may include several components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations, at least one communication chip 706 is also physically and electrically coupled to the board 702. In other embodiments, the communication chip 706 is part of the processor 704.

These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.).

The communication chip 706 enables wireless communication for transferring data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 706 may implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol designated as 3G, 4G, 5G, and higher. The computing device 700 may include a plurality of communication chips 706. For example, a first communication chip 706 may be dedicated for shorter range wireless communications, such as Wi-Fi and Bluetooth, while a second communication chip 706 may be dedicated for longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and the like.

The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some implementations of the invention, the integrated circuit die of the processor may be part of an electronic package including a first die over an array of die stacks according to embodiments described herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip 706 also includes an integrated circuit die packaged within semiconductor chip 706. According to another implementation of the invention, the integrated circuit die of the communication chip may be part of an electronic package including a first die over an array of die stacks according to embodiments described herein.

The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments of the invention described in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example 1: an electronic package, comprising: a package substrate; a first die electrically coupled to the package substrate; and an array of die stacks electrically coupled to the first die, wherein the array of die stacks is between the first die and the package substrate, and wherein each of the die stacks comprises: a plurality of second dies disposed in the vertical stack.

Example 2: the electronic package of example 1, wherein the first die is a compute die and wherein the second die is a memory die.

Example 3: the electronic package of example 1 or example 2, further comprising: a base substrate.

Example 4: the electronic package of example 3, wherein the base substrate is between the array of die stacks and the package substrate.

Example 5: the electronic package of example 3, wherein the base substrate is between the array of die stacks and the first die.

Example 6: the electronic package of example 3, wherein the first die is between the base substrate and the package substrate.

Example 7: the electronic package of examples 3-6, wherein the base die is a passive substrate.

Example 8: the electronic package of examples 3-6, wherein the base die is an active substrate.

Example 9: the electronic package of example 8, wherein the base die includes circuitry for power transfer.

Example 10: the electronic package of examples 1-9, wherein a power transfer path from the package substrate to the first die passes through one or more of the second dies.

Example 11: the electronic package of examples 1-10, wherein a power transfer path from the package substrate to the first die passes between the die stacks.

Example 12: the electronic package of examples 1-11, further comprising: a third die, wherein the first portion of the array of die stacks is under the first die, and wherein the second portion of the array of die stacks is under the third die.

Example 13: an electronic package, comprising: a package substrate; a base substrate over the package substrate; an array of die stacks over a base substrate; and a first die over the array of die stacks.

Example 14: the electronic package of example 13, wherein the first die includes a plurality of compute engine clusters, and wherein an individual one of the die stacks is positioned below an individual one of the compute engine clusters.

Example 15: the electronic package of example 14, wherein the single die stack includes a plurality of second dies, and wherein each second die includes a plurality of memory blocks.

Example 16: the electronic package of example 15, wherein each compute engine cluster includes a plurality of local compute engines, and wherein respective ones of the local compute engines are above respective ones of the memory blocks.

Example 17: the electronic package of examples 13-16, wherein a power transfer path from the package substrate to the first die passes through the plurality of die stacks.

Example 18: the electronic package of examples 13-17, wherein a power transfer path from the package substrate to the first die passes between the die stacks.

Example 19: the electronic package of examples 13-18, further comprising: a third die, wherein the first portion of the array of die stacks is under the first die, and wherein the second portion of the array of die stacks is under the third die.

Example 20: the electronic package of examples 13-19, wherein the array of die stacks comprises a four by four array of die stacks.

Example 21: the electronic package of examples 13-20, wherein the single die stack includes two or more second dies arranged in a vertical stack.

Example 22: the electronic package of example 21, wherein the first die is a compute die and wherein the second die is a memory die.

Example 23: an electronic system, comprising: a plate; a package substrate attached to the board; a first die electrically coupled to the package substrate; and an array of die stacks electrically coupled to the first die, wherein each of the die stacks comprises: a plurality of second dies disposed in the vertical stack.

Example 24: the electronic system of example 23, further comprising: a base substrate, wherein the base substrate is between the package substrate and the array of die stacks, between the array of die stacks and the first die, or over the first die.

Example 25: the electronic system of example 23 or example 24, wherein the power transfer path from the package substrate to the first die passes between or through the die stacks.