阅读说明：本技术 一种数字隔离器及其共模干扰抑制电路 (Digital isolator and common mode interference suppression circuit thereof ) 是由 林涛 罗頔 诸弘超 盛云 于 2021-07-22 设计创作，主要内容包括：本发明公开了一种数字隔离器及其共模干扰抑制电路,其中,该电路,包括差分电路,共模电流补偿电路。差分电路包括第一电阻和第二电阻,第一电阻和第二电阻的自由端分别与差分信号输入端连接。共模电流补偿电路包括至少一个电流镜,电流镜包括第一开关管和第二开关管,第一开关管和第二开关管的控制端相互连接作为电流镜的控制端,并与第一电阻和第二电阻的公共端连接。当数字隔离器受到共模干扰且电流镜控制端电压未达到导通电压时,差分电路起作用以降低共模干扰。当电流镜的控制端的电压达到电流镜的导通电压时,电流镜导通以补偿输入的共模电流,避免了共模电压超出差分结构的共模范围,导致通信失效,增强了数字隔离器的抗干扰能力。(The invention discloses a digital isolator and a common-mode interference suppression circuit thereof, wherein the circuit comprises a differential circuit and a common-mode current compensation circuit. The differential circuit comprises a first resistor and a second resistor, and free ends of the first resistor and the second resistor are respectively connected with the differential signal input end. The common mode current compensation circuit comprises at least one current mirror, the current mirror comprises a first switch tube and a second switch tube, and control ends of the first switch tube and the second switch tube are connected with each other to serve as a control end of the current mirror and are connected with a common end of a first resistor and a second resistor. When the digital isolator is subjected to common mode interference and the voltage of the control end of the current mirror does not reach the conducting voltage, the differential circuit acts to reduce the common mode interference. When the voltage of the control end of the current mirror reaches the conduction voltage of the current mirror, the current mirror is conducted to compensate the input common mode current, the communication failure caused by the fact that the common mode voltage exceeds the common mode range of the differential structure is avoided, and the anti-interference capability of the digital isolator is enhanced.)

1. A common mode interference suppression circuit applied to a digital isolator comprises: a differential circuit, a common mode current compensation circuit;

the differential circuit comprises a first resistor and a second resistor which are connected in series, and free ends of the first resistor and the second resistor are respectively connected with a differential signal input end of a signal demodulation circuit of the digital isolator;

the common mode current compensation circuit comprises at least one current mirror, the current mirror comprises a first switch tube and a second switch tube, the control end of the first switch tube and the control end of the second switch tube are connected to serve as the control end of the current mirror, the first resistor and the common end of the second resistor are connected, when the voltage of the common end reaches the breakover voltage of the current mirror, the current mirror is conducted to compensate the common mode current input by the differential signal input end.

2. A common-mode interference rejection circuit according to claim 1, wherein said common-mode current compensation circuit comprises two current mirrors, a first current mirror and a second current mirror;

when the isolation capacitor in the digital isolator injects current to the signal demodulation circuit, the first current mirror works, and when the isolation capacitor sucks current to the signal demodulation circuit, the second current mirror works.

3. The common mode interference rejection circuit according to claim 2, further comprising a third resistor, a fourth resistor, a first capacitor and a second capacitor;

the third resistor is connected with the fourth resistor in series, and free ends of the third resistor and the fourth resistor are respectively connected with the differential signal input end;

the common end of the first resistor and the second resistor is connected with the control end of the first current mirror, and the common end of the third resistor and the fourth resistor is connected with the control end of the second current mirror;

the first capacitor is connected with the common end of the first resistor and the second resistor and is commonly grounded with the first resistor and the second resistor;

the second capacitor is connected with a common end of the third resistor and the fourth resistor and is connected with the third resistor and the fourth resistor in common.

4. A common-mode interference rejection circuit according to claim 3,

the first switch tube and the second switch tube in the first current mirror are N-type MOS tubes;

the first switch tube and the second switch tube in the second current mirror are P-type MOS tubes.

5. The common mode interference rejection circuit according to claim 4, wherein said N-type MOS transistor and said P-type MOS transistor comprise:

the grid electrodes of the two N-type MOS tubes in the first current mirror are mutually connected to serve as the control end of the first current mirror, the drain electrodes of the two N-type MOS tubes in the first current mirror are respectively connected with the differential signal input end, and the source electrodes of the two N-type MOS tubes in the first current mirror are grounded;

the grid electrodes of the two P-type MOS tubes in the second current mirror are mutually connected to serve as the control end of the second current mirror, the source electrodes of the two P-type MOS tubes in the second current mirror are respectively connected with the differential signal input end, and the drain electrodes of the two P-type MOS tubes in the second current mirror are grounded.

6. A common-mode interference rejection circuit according to claim 5, wherein said common-mode current compensation circuit further comprises a third current mirror and a fourth current mirror;

the first switch tube and the second switch tube in the third current mirror are N-type MOS tubes, gates of two N-type MOS tubes in the third current mirror are connected with each other to serve as a control end of the third current mirror, the control end of the third current mirror is connected with the control end of the first current mirror, sources of two N-type MOS tubes in the third current mirror are respectively connected with sources of two N-type MOS tubes in the first current mirror, and drains of two N-type MOS tubes in the third current mirror are grounded with the first capacitor;

the first switch tube and the second switch tube in the fourth current mirror are P-type MOS tubes, two of the fourth current mirror are connected with each other through grid electrodes of the P-type MOS tubes to serve as a control end of the fourth current mirror, the control end of the fourth current mirror is connected with the control end of the second current mirror, drain electrodes of the P-type MOS tubes in the fourth current mirror are respectively connected with drain electrodes of the P-type MOS tubes in the second current mirror, and source electrodes of the P-type MOS tubes in the fourth current mirror are connected with the second capacitor in common.

7. A common-mode interference rejection circuit according to claim 3,

the first switching tube and the second switching tube in the first current mirror are NPN type triodes;

the first switch tube and the second switch tube in the second current mirror are PNP type triodes.

8. A common-mode interference rejection circuit according to claim 7, wherein said NPN transistor and said PNP transistor comprise:

bases of two NPN triodes in the first current mirror are mutually connected to serve as a control end of the first current mirror, collectors of the two NPN triodes in the first current mirror are respectively connected with the differential signal input end, and emitters of the two NPN triodes in the first current mirror are grounded;

two in the second current mirror base interconnect of PNP type triode is regarded as the control end of second current mirror, two in the second current mirror the collecting electrode of PNP type triode respectively with the difference signal input end is connected, two in the second current mirror the projecting pole ground connection of PNP type triode.

9. A common-mode interference rejection circuit according to any one of claims 1-8 wherein said first switching transistor and said second switching transistor are the same size.

10. A digital isolator comprising a common mode interference rejection circuit according to any one of claims 1 to 9.

Technical Field

The invention relates to the field of digital isolators, in particular to a digital isolator and a common-mode interference suppression circuit thereof.

Background

The digital isolator can be divided into optical coupling isolation, capacitance isolation, magnetic coupling isolation, giant magnetoresistance isolation and other types according to different technical modes, in a complex application environment, a comprehensive electronic system is provided with a plurality of subsystems, crosstalk can be generated during data transmission of each subsystem, and the digital isolator can isolate any subsystem from other subsystems and protect the subsystems from noise and high voltage. With the intelligentization of industrial and communication equipment, the demand of the market for digital isolators is increasing day by day, and the performance requirements are higher and higher. One of the problems to be solved by designing the digital isolator of the present invention is common mode transient interference, and currently, a differential circuit is usually adopted to improve the common mode transient interference of the digital isolator.

Fig. 1 is a schematic diagram of a digital isolator principle based on a differential structure. Referring to fig. 1, a differential signal output end of a signal modulation circuit is respectively connected with an isolation capacitor, the isolation capacitor is respectively connected with a differential signal input end VINN and VINP of a signal conditioning circuit, and meanwhile, the differential signal input end VINN and VINP are respectively connected with free ends of a resistor R1 and a resistor R2 which are connected in series in the differential circuit, when common-mode interference is generated between a first chip 1 and a second chip 2, common-mode interference voltage is superposed on the differential signal input ends VINN and VINP of the signal demodulation circuit, at the moment, two resistors in the differential circuit act, and therefore the common-mode interference is reduced. However, since the common mode range of the differential structure adopted by the digital isolator is limited, communication failure can be caused when the common mode voltage exceeds the common mode range.

Therefore, solving the problem of communication failure caused by the common mode voltage exceeding the common mode range is an urgent problem to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a digital isolator and a common-mode interference suppression circuit thereof, which can limit the common-mode voltage at the input end of the digital isolator within a smaller fluctuation range, thereby ensuring the normal transmission of signals and enhancing the anti-interference capability of the digital isolator.

To solve the above technical problem, the present invention provides a common mode interference suppression circuit applied to a digital isolator, including: a differential circuit, a common mode current compensation circuit;

the differential circuit comprises a first resistor and a second resistor which are connected in series, and free ends of the first resistor and the second resistor are respectively connected with a differential signal input end of a signal demodulation circuit of the digital isolator;

the common mode current compensation circuit comprises at least one current mirror, the current mirror comprises a first switch tube and a second switch tube, the control end of the first switch tube and the control end of the second switch tube are connected to serve as the control end of the current mirror, the first resistor and the common end of the second resistor are connected, when the voltage of the common end reaches the breakover voltage of the current mirror, the current mirror is conducted to compensate the common mode current input by the differential signal input end.

Preferably, the common mode current compensation circuit comprises two current mirrors, wherein the two current mirrors are a first current mirror and a second current mirror respectively;

when the isolation capacitor in the digital isolator injects current to the signal demodulation circuit, the first current mirror works, and when the isolation capacitor sucks current to the signal demodulation circuit, the second current mirror works.

Preferably, the common mode interference rejection circuit further includes a third resistor, a fourth resistor, a first capacitor and a second capacitor;

the third resistor is connected with the fourth resistor in series, and free ends of the third resistor and the fourth resistor are respectively connected with the differential signal input end;

the common end of the first resistor and the second resistor is connected with the control end of the first current mirror, and the common end of the third resistor and the fourth resistor is connected with the control end of the second current mirror;

the first capacitor is connected with the common end of the first resistor and the second resistor and is commonly grounded with the first resistor and the second resistor;

the second capacitor is connected with a common end of the third resistor and the fourth resistor and is connected with the third resistor and the fourth resistor in common.

Preferably, the first switching tube and the second switching tube in the first current mirror are N-type MOS tubes;

the first switch tube and the second switch tube in the second current mirror are P-type MOS tubes.

Preferably, the N-type MOS transistor and the P-type MOS transistor include:

the grid electrodes of the two N-type MOS tubes in the first current mirror are mutually connected to serve as the control end of the first current mirror, the drain electrodes of the two N-type MOS tubes in the first current mirror are respectively connected with the differential signal input end, and the source electrodes of the two N-type MOS tubes in the first current mirror are grounded;

the grid electrodes of the two P-type MOS tubes in the second current mirror are mutually connected to serve as the control end of the second current mirror, the source electrodes of the two P-type MOS tubes in the second current mirror are respectively connected with the differential signal input end, and the drain electrodes of the two P-type MOS tubes in the second current mirror are grounded.

Preferably, the common mode current compensation circuit further comprises a third current mirror and a fourth current mirror;

the first switch tube and the second switch tube in the third current mirror are N-type MOS tubes, gates of two N-type MOS tubes in the third current mirror are connected with each other to serve as a control end of the third current mirror, the control end of the third current mirror is connected with the control end of the first current mirror, sources of two N-type MOS tubes in the third current mirror are respectively connected with sources of two N-type MOS tubes in the first current mirror, and drains of two N-type MOS tubes in the third current mirror are grounded with the first capacitor;

the first switch tube and the second switch tube in the fourth current mirror are P-type MOS tubes, two of the fourth current mirror are connected with each other through grid electrodes of the P-type MOS tubes to serve as a control end of the fourth current mirror, the control end of the fourth current mirror is connected with the control end of the second current mirror, drain electrodes of the P-type MOS tubes in the fourth current mirror are respectively connected with drain electrodes of the P-type MOS tubes in the second current mirror, and source electrodes of the P-type MOS tubes in the fourth current mirror are connected with the second capacitor in common.

Preferably, the first switching tube and the second switching tube in the first current mirror are NPN-type triodes;

the first switch tube and the second switch tube in the second current mirror are PNP type triodes.

Preferably, the NPN type transistor and the PNP type transistor include:

bases of two NPN triodes in the first current mirror are mutually connected to serve as a control end of the first current mirror, collectors of the two NPN triodes in the first current mirror are respectively connected with the differential signal input end, and emitters of the two NPN triodes in the first current mirror are grounded;

two in the second current mirror base interconnect of PNP type triode is regarded as the control end of second current mirror, two in the second current mirror the collecting electrode of PNP type triode respectively with the difference signal input end is connected, two in the second current mirror the projecting pole ground connection of PNP type triode.

Preferably, the first switching tube and the second switching tube are the same size.

In order to solve the technical problem, the invention also provides a digital isolator which comprises the common-mode interference suppression circuit.

The invention provides a common mode interference suppression circuit, comprising: a differential circuit and a common mode current compensation circuit. The differential circuit comprises a first resistor and a second resistor which are connected in series, free ends of the first resistor and the second resistor are respectively connected with a differential signal input end of a signal demodulation circuit of the digital isolator, and a common end of the first resistor and the second resistor is grounded. The common mode current compensation circuit comprises at least one current mirror, the current mirror comprises a first switch tube and a second switch tube, and the control end of the first switch tube and the control end of the second switch tube are connected to be used as the control end of the current mirror and connected with the common end of a first resistor and a second resistor. When the digital isolator is subjected to common mode interference and the voltage of the common end of the first resistor and the second resistor does not reach the conduction voltage of the current mirror, the differential circuit acts, and therefore common mode interference is reduced. When the common-mode voltage of the first resistor and the second resistor reaches the conduction voltage of the current mirror, the current mirror is conducted to compensate the common-mode current input by the differential signal input end, and the common-mode voltage is limited in a small fluctuation range, so that normal signal transmission is ensured, communication failure caused by the fact that the common-mode voltage exceeds the common-mode range of the differential structure is avoided, and the anti-interference capability of the digital isolator is enhanced.

In addition, the digital isolator provided by the invention comprises the common-mode interference suppression circuit, and the effect is the same as that of the common-mode interference suppression circuit.

Drawings

In order to illustrate the embodiments of the present invention more clearly, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained by those skilled in the art without inventive effort.

FIG. 1 is a schematic diagram of a digital isolator principle based on a differential structure;

FIG. 2 is a voltage waveform diagram of the digital isolator based on the differential architecture of FIG. 1;

FIG. 3 is a schematic diagram of a common mode interference rejection circuit according to the present invention;

FIG. 4 is a schematic diagram of a digital isolator based on a common mode interference rejection circuit;

FIG. 5 is a voltage waveform diagram of the digital isolator based on the common mode interference rejection circuit of FIG. 4;

FIG. 6 is a schematic diagram of another common mode interference rejection circuit according to the present invention;

the reference numbers are as follows: 1 is a first chip and 2 is a second chip.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.

The core of the invention is to provide a digital isolator and a common mode interference suppression circuit thereof. When the digital isolator is subjected to common-mode interference, the common-mode interference suppression circuit plays a role in compensating common-mode current input by a signal demodulation circuit in digital isolation, and common-mode voltage is limited in a small fluctuation range, so that normal transmission of signals is guaranteed, and the anti-interference capability of the digital isolator is enhanced.

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, the digital isolator is composed of a plurality of channels, a first chip 1 is arranged on the left side, an isolation capacitor is arranged in the middle, a second chip 2 is arranged on the right side, the second chip 2 includes a signal demodulation circuit, a spike-resistant circuit, and a differential circuit for suppressing common mode interference, the differential circuit is composed of a first resistor R1 and a second resistor R2 which are connected in series, free ends of the first resistor R1 and the second resistor R2 are respectively connected with a differential signal input terminal VINN and VINP of the second chip 2, and a common terminal is grounded. The input signal is transmitted from DIN _1 to the signal modulation circuit and converted into differential signal by the signal modulation circuit, and the differential signal is isolated by the isolating capacitor C_ISO1And C_ISO2To the second chip 2. When common-mode interference is generated between the first chip 1 and the second chip 2, interference signals are superposed on the differential signal input ends VINN and VINP of the signal demodulation circuit, and at the moment, the differential circuit acts to reduce the common-mode interference so as to enhance the common-mode interference resistance of the digital isolator. However, because the differential structure adopted by the digital isolator has a limited input common mode range, when the input common mode voltage exceeds the input common mode range, communication failure can be caused. Therefore, the common mode interference generated between the first chip 1 and the second chip 2 can be improved by using the differential circuit, but the possibility of communication failure cannot be avoided。

Fig. 2 is a voltage waveform diagram of the digital isolator based on the differential structure in fig. 1. As shown in FIG. 2, the digital isolator adopts a differential structure to obviously improve common-mode interference in stages T3-T4 and T5-T6. However, in the stage T7-T8, since the reference ground of the first chip 1 and the second chip 2 changes by Δ V within the time Δ T, the isolation capacitor C is used to isolate the reference ground_ISO1And C_ISO2The common-mode current Δ I ═ Δ V/# Δ T × C injected into the second chip 2_ISO1,2Wherein, C_ISO1,2Is the isolation capacitance between the first chip 1 and the second chip 2. The second chip 2 is fed with a common-mode current DeltaI, which results in an increase DeltaI R of the common-mode voltage at the differential signal inputs VINN and VINP of the signal demodulation circuit_1,2Wherein R is_1,2Is the resistance value of the resistor in the differential circuit. It should be noted that if the isolation capacitor C_ISO1And C_ISO2The capacitance values of the first resistor R1 and the second resistor R2 in the differential circuit are different in setting, the differential structure characteristics of the digital isolator can be damaged, the risk of communication failure is increased, and therefore the isolation capacitor C is_ISO1And C_ISO2The capacitance values of (a) and (b) are set the same, and the resistance values of the first resistor R1 and the second resistor R2 in the differential circuit are set the same. Due to the limited input common mode range of the differential structure adopted by the digital isolator, communication failure occurs on the output DOUT _1 due to the fact that the input common mode voltage exceeds the input common mode range of the differential structure in the stages T7-T8.

Similarly, in the phases T9-T10, since the reference grounds of DIE1 and DIE2 change Δ V within the time Δ T, the common mode current Δ I absorbed by the isolation capacitor to the second chip 2 is Δ V/Δ T × C_ISO1,2Resulting in a common-mode voltage reduction Δ I R of the inputs VINN and VINP of the differential signal_1,2Therefore, a communication failure occurs at output DOUT _1 during stages T9-T10 due to the input common mode voltage exceeding the input common mode range of the differential structure.

Fig. 3 is a schematic diagram of a common mode interference rejection circuit according to the present invention. Fig. 4 is a schematic diagram of a digital isolator based on a common mode interference rejection circuit. Based on the above analysis, it can be seen that the use of the differential structure by the digital isolator can improve the common mode interference generated between the first chip 1 and the second chip 2, but cannot avoid the possibility of communication failure. Referring to fig. 4, a common mode interference rejection circuit as shown in fig. 3 is provided between the first chip 1 and the second chip 2. When common mode interference is generated between the first chip 1 and the second chip 2, the common mode interference suppression circuit acts to compensate the common mode current.

As shown in fig. 3, the common mode interference rejection circuit provided by the present invention includes: a differential circuit and a common mode current compensation circuit. The differential circuit comprises a first resistor R1 and a second resistor R2 which are connected in series, and free ends of the first resistor R1 and the second resistor R2 are respectively connected with differential signal input ends VINN and VINP of a signal demodulation circuit of the digital isolator.

The common mode current compensation circuit comprises at least one current mirror, and the current mirror comprises a first switching tube and a second switching tube. In a specific embodiment, the first switching tube and the second switching tube may be MOS tubes or triodes, and the invention is not limited thereto. As shown in fig. 3, the common mode current of the compensation digital isolator of the common mode interference rejection circuit is described in detail by taking a triode as an example. The first switch tube NPN1 and the second switch tube NPN2 form a current mirror, the control end of the first switch tube NPN1 and the control end of the second switch tube NPN2 are connected as the control end of the current mirror, and are connected with the common end of the first resistor R1 and the second resistor R2, when the voltage of the common end of the first resistor R1 and the second resistor R2 reaches the conduction voltage of the current mirror, the current mirror is conducted to compensate the common mode current of the differential signal input terminals VINN and VINP. It should be noted that the first switching tube and the second switching tube may be the same or different in size, and the present invention is not limited thereto.

In a specific embodiment, the isolation capacitors of the digital isolator may be one as shown in fig. 1, or two as shown in fig. 4, but the present invention is not limited thereto, and two isolation capacitors are preferably provided in view of the signal fluctuation range and the degree of withstand voltage. Fig. 5 is a voltage waveform diagram of the digital isolator based on the common mode interference rejection circuit in fig. 4. As shown in fig. 5, the dotted line is a voltage waveform structure of the digital isolator based on the differential structure, and the solid line is a voltage waveform structure of the digital isolator based on the common mode interference suppression circuit provided by the present invention. Referring to fig. 5, the common-mode interference suppression circuit provided by the invention has the advantages that the variation ranges of the differential signal input ends VINN and VINP in the stages of T7-T8 and T9-T10 are obviously reduced when common-mode interference occurs, the common-mode interference in the stages of T7-T8 and T9-T10 is effectively improved, and the common-mode interference resistance of the digital isolator is further enhanced.

Of course, in an implementation, the isolation capacitor sinks or sinks the common mode current to DIE2, so the common mode current compensation circuit includes two current mirrors (see below for details) for sinking and compensating the common mode current at the differential signal input terminals VINN and VINP, respectively.

The common mode interference suppression circuit provided by the invention comprises a differential circuit and a common mode current compensation circuit. The differential circuit comprises a first resistor and a second resistor which are connected in series, free ends of the first resistor and the second resistor are respectively connected with a differential signal input end of a signal demodulation circuit of the digital isolator, and a common end of the first resistor and the second resistor is grounded. The common mode current compensation circuit comprises at least one current mirror, the current mirror comprises a first switch tube and a second switch tube, and the control end of the first switch tube and the control end of the second switch tube are connected to be used as the control end of the current mirror and connected with the common end of a first resistor and a second resistor. When the digital isolator is subjected to common mode interference and the voltage of the common end of the first resistor and the second resistor does not reach the conduction voltage of the current mirror, the differential circuit acts, and therefore common mode interference is reduced. When the common-mode voltage of the first resistor and the second resistor reaches the conduction voltage of the current mirror, the current mirror is conducted to compensate the common-mode current input by the differential signal input end, and the common-mode voltage is limited in a small fluctuation range, so that normal signal transmission is ensured, communication failure caused by the fact that the common-mode voltage exceeds the common-mode range of the differential structure is avoided, and the anti-interference capability of the digital isolator is enhanced.

In a specific implementation, when the digital isolator is subjected to common-mode interference, the isolation capacitor is caused to sink currents and absorb currents to the differential signal input terminals VINN and VINP, so that in order to ensure normal transmission of signals, the common-mode current compensation circuit is provided with two current mirrors, the two current mirrors are respectively a first current mirror and a second current mirror, when the isolation capacitor sinks currents to the signal demodulation circuit, the first current mirror works as a common-mode current absorption circuit to absorb common-mode currents of the signal input terminals VINN and VINP, and when the isolation capacitor absorbs currents to the signal demodulation circuit, the second current mirror works as a common-mode current compensation circuit to compensate common-mode currents of the signal input terminals VINN and VINP. As shown in fig. 3, the common mode current absorption circuit and the common mode current compensation circuit are described in detail by taking a triode as an example. The first switching tube NPN1 and the second switching tube NPN2 form a first current mirror, and the first switching tube PNP1 and the second switching tube PNP2 form a second current mirror. The control end of the first switch tube NPN1 and the control end of the second switch tube NPN2 are connected as the control end of the first current mirror, the control end of the first switch tube PNP1 and the control end of the second switch tube PNP2 are connected as the control end of the second current mirror, when the isolation capacitor sinks current to the signal demodulation current, the common mode current absorption circuit composed of the control end of the first switch tube NPN1 and the second switch tube NPN2 works to absorb the common mode current of the signal input ends VINN and VINP, and when the isolation capacitor sinks current to the signal demodulation current, the common mode current compensation circuit composed of the control end of the first switch tube PNP1 and the second switch tube PNP2 works to compensate the common mode current of the signal input ends VINN and VINP.

Therefore, the common-mode interference suppression circuit provided by the invention has the advantages that the common-mode current compensation circuit is arranged into the two current mirrors, and when the digital isolator is subjected to common-mode interference, the common-mode voltage can be limited to fluctuate within a small range no matter the isolation capacitor feeds current or absorbs current to the differential signal input ends VINN and VINP, so that the normal transmission of signals is ensured, and the common-mode interference resistance of the digital isolator is enhanced.

Fig. 6 is a schematic diagram of another common mode interference rejection circuit according to the present invention. Based on the above-described embodiment, considering filtering signals received by the input terminals VINN and VINP of the signal demodulation circuit, as shown in fig. 6, the third resistor R3, the fourth resistor R4, the first capacitor C1, and the second capacitor C2 are provided in the common mode interference suppression circuit. It should be noted that the first switching tube and the second switching tube may be MOS tubes or triodes, and the present invention is not limited thereto, and reference is made to fig. 6, which is described in detail by taking MOS tubes as an example. The first switch tube NM1 and the second switch tube NM2 form a first current mirror, the control ends of the first switch tube NM1 and the second switch tube NM2 are connected to serve as the control end of the first current mirror, the first resistor R1 and the second resistor R2 are connected in series, the common end of the first switch tube NM1 and the second switch tube NM2 is connected with the control end of the first current mirror, the free ends of the first switch tube NM1 and the second switch tube NM2 are connected with the differential signal input end VINN and VINP respectively, and the first capacitor C1 is connected with the common end of the first resistor R1 and the second resistor R2 and is connected with the first resistor R1 and the second resistor R2 in common ground. The first switch tube PM1 and the second switch tube PM2 form a second current mirror, the control ends of the first switch tube PM1 and the second switch tube PM2 are connected to a control end serving as a second current, the third resistor R3 and the fourth resistor R4 are connected in series, free ends of the third resistor R3 and the fourth resistor R4 are respectively connected with the differential signal input ends VINN and VINP, a common end of the third resistor R3 and the fourth resistor R4 are connected with the control end of the second current mirror, and the second capacitor C2 is connected with the common end of the third resistor R3 and the fourth resistor R4 and is connected with the third resistor R3 and the fourth resistor R4 in common. A third resistor R3, a fourth resistor R4, a first capacitor C1 and a second capacitor C2 are added in the common mode interference suppression circuit to form two RC networks, so that the turning frequency of the compensation circuit common mode interference suppression circuit to the gain of the circuit is determined, and then the signal in the common mode interference suppression circuit is filtered.

According to the common mode interference suppression circuit provided by the invention, the third resistor R3, the fourth resistor R4, the first capacitor C1 and the second capacitor C2 are added in the circuit, so that the signal bandwidth is adjusted, the influence of high-frequency signals and low-frequency signals on the compensation circuit is prevented, a filtering effect is realized, the compensation of the common mode interference suppression circuit on common mode signals is further realized, and the common mode interference resistance of the system is enhanced.

In a specific embodiment, two situations of current sinking and current sucking of the isolation capacitor to the differential signal input terminals VINN and VINP are considered, and in addition, since the N-type MOS transistor is turned on when the voltage passing through the N-type MOS transistor is greater than the threshold voltage of the N-type MOS transistor, the P-type MOS transistor is turned on when the voltage passing through the P-type MOS transistor is less than the threshold voltage of the P-type MOS transistor. Therefore, as shown in fig. 6, the first and second switching tubes NM1 and NM2 in the first current mirror may be configured as N-type MOS transistors, and the first and second switching tubes PM1 and PM2 in the second current mirror may be configured as P-type MOS transistors, due to the conductive nature of the N-type and P-type MOS transistors.

The grid electrodes of the two N-type MOS tubes in the first current mirror are mutually connected to serve as the control end of the first current mirror, the drain electrodes of the two N-type MOS tubes in the first current mirror are respectively connected with the differential signal input end VINN and the VINP, and the source electrodes of the two N-type MOS tubes in the first current mirror are grounded. The grid electrodes of the two P-type MOS tubes in the second current mirror are mutually connected to be used as the control end of the second current mirror, the source electrodes of the two P-type MOS tubes in the second current mirror are respectively connected with the differential signal input end VINN and the VINP, and the drain electrodes of the two P-type MOS tubes in the second current mirror are grounded.

When the isolation capacitor sinks current to the differential signal input ends VINN and VINP, the voltage of the control end of the first current mirror reaches the conduction voltage of the N-type MOS tube, the first current mirror is conducted to absorb the common-mode current, and when the isolation capacitor sinks current to the differential signal input ends VINN and VINP, the voltage of the control end of the second current mirror reaches the conduction voltage of the P-type MOS tube, the second current mirror is conducted to compensate the common-mode current.

Therefore, the common-mode interference suppression circuit provided by the invention has the advantages that the first switch tube and the second switch tube in the first current mirror are set to be the N-type MOS tubes, the first switch tube and the second switch tube in the second current mirror are set to be the P-type MOS tubes, and the common-mode voltage can be limited to fluctuate within a small range no matter the isolation capacitor feeds current or absorbs current to the differential signal input ends VINN and VINP, so that the normal transmission of signals is ensured, and the common-mode interference resistance of the digital isolator is enhanced.

In addition to the above embodiments, considering the case that the differential signal input terminals VINN and VINP are leaky due to the positive or negative common-mode interference, as shown in fig. 6, a third current mirror and a fourth current mirror are added to the common-mode current compensation circuit. The first switching tube NM1 and the second switching tube NM2 form a first current mirror, the first switching tube PM1 and the second switching tube PM2 form a second current mirror, the first switching tube NM3 and the second switching tube NM4 form a third current mirror, and the first switching tube PM3 and the second switching tube PM4 form a fourth current mirror.

In a first current mirrorThe first and second switching tubes NM1 and NM2 and the first and second switching tubes NM3 and NM4 in the third current mirror are N-type MOS transistors, gates of the first and second switching tubes NM3 and NM4 are connected to each other to serve as a control terminal of the third current mirror, and the control terminal of the third current mirror is connected to the control terminal of the first current mirror. In addition, sources of the first and second switching tubes NM3 and NM4 are connected to sources of the first and second switching tubes NM1 and NM2, respectively, and drains of the first and second switching tubes NM3 and NM4 are commonly grounded to the first capacitor C1. The first current mirror, the third current mirror and the first capacitor C1 form a common mode interference absorption circuit, when the digital isolator has no common mode interference, the common mode voltage is low and is not enough to lead the N-type MOS tube in the first current mirror and the third current mirror to be conducted, when the common mode interference occurs, the voltage VTH _ H at the common end of the first resistor R1 and the second resistor R2 rises to the conducting voltage of the N-type MOS tube, the common mode interference absorption circuit acts, and the switching tube NM acts_1-4Absorbing the common mode current injected by the isolation capacitor.

The first switching tube PM1 and the second switching tube PM2 in the second current mirror and the first switching tube PM3 and the second switching tube PM4 in the fourth current mirror are P-type MOS tubes, gates of the first switching tube PM3 and the second switching tube PM4 are connected with each other to serve as a control end of the fourth current mirror, and the control end of the fourth current mirror is connected with the control end of the second current mirror. In addition, the drains of the first switching tube PM3 and the second switching tube PM4 are connected to the drains of the first switching tube PM1 and the second switching tube PM2, respectively, and the sources of the first switching tube PM3 and the second switching tube PM4 are connected to the second capacitor C2 in common. The second current mirror, the fourth current mirror and the second capacitor C2 form a common mode interference compensation circuit, similarly, when common mode interference occurs, the voltage VTH _ L at the common end of the third resistor R3 and the fourth resistor R4 is reduced to the conduction voltage of the P-type MOS tube, the common mode interference compensation circuit acts, and the switching tube PM acts_1-4Compensating the common mode current injected by the isolation capacitor.

Therefore, when the common-mode interference suppression circuit provided by the invention is additionally provided with the third current mirror and the fourth current mirror, and the first switch tube NM1 and the first switch tube NM3 are connected in series to effectively block the electric leakage caused when the differential signal input ends VINN and VINP become negative voltage when the first current mirror and the third current mirror are conducted and the common-mode interference absorption circuit acts to absorb the common-mode current. Similarly, when the second current mirror and the fourth current mirror are turned on and the common mode interference compensation circuit is operated to compensate the common mode current, the first switch tube PM2 and the first switch tube PM4 are connected in series to effectively block the leakage current caused when the differential signal input terminals VINN and VINP become positive due to the common mode interference.

In a specific embodiment, the first switch tube and the second switch tube may be MOS tubes or triodes, and the invention is not limited, in consideration of cost, and since the triodes have the same conduction property as the MOS tubes and also have a leakage prevention function, as shown in fig. 3, the first switch tube NPN1 and the second switch tube NPN2 in the first current mirror may be configured as NPN triodes, and the first switch tube PNP1 and the second switch tube PNP2 in the second current mirror are configured as PNP triodes.

Referring to fig. 3, bases of a first switch NPN1 and a second switch NPN2 in the first current mirror are connected to each other to serve as a control terminal of the first current mirror, collectors of the first switch NPN1 and the second switch NPN2 are connected to a differential signal input terminal VINN and VINP, respectively, and emitters of the first switch NPN1 and the second switch NPN2 are grounded. When the digital isolator is subjected to common mode interference, when the voltage at the control end of the first current mirror reaches the conducting voltage of the NPN type triode, the first current mirror is conducted, and the NPN type triode is switched on_1-2Absorbing the common mode current injected by the isolation capacitor.

The bases of the first switch tube PNP1 and the second switch tube PNP2 in the second current mirror are connected with each other to serve as the control terminal of the second current mirror, the collectors of the first switch tube PNP1 and the second switch tube PNP2 are respectively connected with the differential signal input terminals VINN and VINP, and the emitters of the first switch tube PNP1 and the second switch tube PNP2 are grounded. When the digital isolator is interfered by common mode, the control end voltage of the second current mirror reaches the conducting voltage of the PNP type triode, the second current mirror is conducted, and the switching tube PNP_1-2Compensating the common mode current injected by the isolation capacitor.

Therefore, the common-mode interference suppression circuit provided by the invention has the advantages that the first switch tube NPN1 and the second switch tube NPN2 in the first current mirror are set as NPN type triodes, and the first switch tube PNP1 and the second switch tube PNP2 in the second current mirror are set as PNP type triodes, so that the cost is saved, the current is filled into or absorbed by the isolation capacitor to the differential signal input ends VINN and VINP, the common-mode voltage can be limited to fluctuate in a small range, the normal transmission of signals is ensured, and the common-mode interference resistance of the digital isolator is enhanced.

On the basis of the above-mentioned embodiment, the first switch tube and the second switch tube are equally sized from the viewpoint of the probability of converting a common-mode signal into a differential-mode signal.

According to the common mode interference suppression circuit provided by the invention, the sizes of the first switching tube and the second switching tube are set to be the same, so that the probability of converting a common mode signal into a differential mode signal can be effectively reduced, the high-efficiency compensation of the common mode interference suppression circuit on the common mode signal is further ensured, and the common mode interference resistance of the digital isolator is enhanced.

The invention also provides a digital isolator which comprises the common-mode interference suppression circuit, and the common-mode interference suppression circuit is used for compensating the common-mode current in the digital isolator. Since the common mode interference suppression circuit is described in detail above, the description of the present embodiment is omitted.

Therefore, the invention provides a digital isolator, which comprises a common-mode interference suppression circuit, wherein the common-mode interference suppression circuit comprises a differential circuit and a common-mode current compensation circuit. The differential circuit comprises a first resistor and a second resistor which are connected in series, free ends of the first resistor and the second resistor are respectively connected with a differential signal input end of a signal demodulation circuit of the digital isolator, and a common end of the first resistor and the second resistor is grounded. The common mode current compensation circuit comprises at least one current mirror, the current mirror comprises a first switch tube and a second switch tube, and the control end of the first switch tube and the control end of the second switch tube are connected to be used as the control end of the current mirror and connected with the common end of a first resistor and a second resistor. When the digital isolator is subjected to common mode interference and the voltage of the common end of the first resistor and the second resistor does not reach the conduction voltage of the current mirror, the differential circuit acts, and therefore common mode interference is reduced. When the common-mode voltage of the first resistor and the second resistor reaches the conduction voltage of the current mirror, the current mirror is conducted to compensate the common-mode current input by the differential signal input end, and the common-mode voltage is limited in a small fluctuation range, so that normal signal transmission is ensured, communication failure caused by the fact that the common-mode voltage exceeds the common-mode range of the differential structure is avoided, and the anti-interference capability of the digital isolator is enhanced.

Finally, in order to make those skilled in the art better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the common mode interference suppression circuit diagram shown in fig. 6.

As shown in fig. 6, the first switching transistor NM1 and the second switching transistor NM2 are N-type MOS transistors and constitute a first current mirror, the first switching transistor NM3 and the second switching transistor NM4 are N-type MOS transistors and constitute a third current mirror, the first switching transistor PM1 and the second switching transistor PM2 are P-type MOS transistors and constitute a second current mirror, and the first switching transistor PM3 and the second switching transistor PM4 are P-type MOS transistors and constitute a fourth current mirror.

Gates of the first switching tube NM1 and the second switching tube NM2 are connected to each other as a control terminal of the first current mirror, gates of the first switching tube NM3 and the second switching tube NM4 are connected to each other as a control terminal of the third current mirror, the control terminals of the first current mirror and the third current mirror are connected to a common terminal of the first resistor R1 and the second resistor R2, sources of the first switching tube NM3 and the second switching tube NM4 are connected to sources of the first switching tube NM1 and the second switching tube NM2, respectively, and drains of the first switching tube NM3 and the second switching tube NM4 are connected to the first capacitor C1 in common. The first current mirror, the third current mirror, the first resistor R1, the second resistor R2 and the first capacitor C1 form a common mode interference absorption circuit.

The gates of the first switch tube PM1 and the second switch tube PM2 are connected with each other to serve as the control end of the second current mirror, the gates of the first switch tube PM3 and the second switch tube PM4 are connected with each other to serve as the control end of the fourth current mirror, the control end of the second current mirror and the control end of the fourth current mirror are connected with the common end of the third resistor R3 and the fourth resistor R4, the drains of the first switch tube PM3 and the second switch tube PM4 are connected with the drains of the first switch tube PM1 and the second switch tube PM2, respectively, and the sources of the first switch tube PM3 and the second switch tube PM4 are connected with the second capacitor C2 in common. The fourth current mirror, the third resistor R3, the fourth resistor R4 and the second capacitor C2 form a common mode interference compensation circuit.

In the present invention, it is preferable that the first capacitor and the second capacitor have the same capacitance value, the first switching tube NM1, the second switching tube NM2, the first switching tube NM3 and the second switching tube NM4 have the same size, the first switching tube PM1, the second switching tube PM2, the first switching tube PM3 and the second switching tube PM4 have the same size, and the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 have the same resistance value.

When common-mode interference exists, the isolation capacitor feeds current to the differential signal input ends VINN and VINP, the common-mode interference absorption circuit acts to clamp the common-mode voltage of the differential signal input ends VINN and VINP to the conduction voltage of the control ends of the first current mirror and the third current mirror, and the first current mirror and the third current mirror are conducted to absorb the common-mode current fed by the isolation capacitor. When the isolation capacitor absorbs current to the differential signal input ends VINN and VINP, the common-mode interference compensation circuit acts to clamp the common-mode voltage of the differential signal input ends VINN and VINP to the conducting voltage of the control ends of the second current mirror and the fourth current mirror, and the second current mirror and the fourth current mirror are conducted to compensate the common-mode current absorbed by the isolation capacitor.

Taking the common mode interference absorption circuit as an example for details, the voltage VTH _ H of the first current mirror control terminal is (VINN + VINP)/2, which is the common mode voltage of the input signal, and when there is no common mode interference, the common mode voltage VTH _ H is very low and is not enough to turn on the N-type MOS transistor. When the common mode interference occurs, if the common mode interference absorption circuit is not added (see fig. 1), the input common mode voltage is V ═ Δ V/. Δ T × C_ISO1,2*R_1,2Wherein, C_ISO1,2Is the isolation capacitance value, R, between the first chip 1 and the second chip 2_1,2For the resistance values of the resistors in the differential circuit, when the common mode interference absorption circuit is added (see fig. 6), after the common mode voltage VTH _ H rises to the on-state voltage of the first current mirror and the third current mirror, the first current mirror and the third current mirror absorb the injected common mode current of the isolation capacitor.

It is noted that the first switch NM1, the second switch NM2, the first switch NM3, the second switch NM4, the first resistor R1, the second resistor R2 and the first capacitor C1 form a common mode interference absorption circuit, which has high impedance for the differential signal input terminals VINN and VINP, and has small load impedance for the common mode signals of VINN and VINP, which is the effective transconductance of the first switch NM1, the second switch NM2, the first switch NM3 and the second switch NM 4.

Therefore, the common mode interference suppression circuit provided by the invention has large common mode gain and small differential mode gain, and is complementary with the characteristics of small common mode gain and large differential mode gain of a signal demodulation circuit in the digital isolator, the common mode interference is compensated by the common mode interference suppression circuit, and a modulated high-frequency signal is received and amplified by the signal demodulation circuit, so that the normal transmission of the signal is ensured, and the anti-interference capability of the digital isolator is enhanced.

The digital isolator and the common mode interference suppression circuit thereof provided by the invention are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.